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mmapped_ipr.hh
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28  * Authors: Ali Saidi
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30 
31 #ifndef __ARCH_SPARC_MMAPPED_IPR_HH__
32 #define __ARCH_SPARC_MMAPPED_IPR_HH__
33 
41 #include "arch/sparc/tlb.hh"
42 #include "cpu/thread_context.hh"
43 #include "mem/packet.hh"
44 
45 namespace SparcISA
46 {
47 
48 inline Cycles
50 {
52  return GenericISA::handleGenericIprRead(xc, pkt);
53  else
54  return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
55 }
56 
57 inline Cycles
59 {
61  return GenericISA::handleGenericIprWrite(xc, pkt);
62  else
63  return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
64 }
65 
66 
67 } // namespace SparcISA
68 
69 #endif
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
Cycles handleGenericIprWrite(ThreadContext *xc, Packet *pkt)
Handle generic IPR writes.
Definition: mmapped_ipr.cc:71
ThreadContext is the external interface to all thread state for anything outside of the CPU...
virtual TheISA::TLB * getDTBPtr()=0
Cycles handleIprRead(ThreadContext *xc, Packet *pkt)
Definition: mmapped_ipr.hh:49
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:245
Cycles handleIprWrite(ThreadContext *xc, Packet *pkt)
Definition: mmapped_ipr.hh:58
Declaration of the Packet class.
ISA-generic helper functions for memory mapped IPR accesses.
Cycles handleGenericIprRead(ThreadContext *xc, Packet *pkt)
Handle generic IPR reads.
Definition: mmapped_ipr.cc:54
bool isGenericIprAccess(const Packet *pkt)
Check if this is an platform independent IPR access.
Definition: mmapped_ipr.hh:103

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