traffic_gen.hh

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/*
 * Copyright (c) 2012-2013, 2016 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Thomas Grass
 *          Andreas Hansson
 *          Sascha Bischoff
 */
#ifndef __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
#define __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__

#include <unordered_map>

#include "base/statistics.hh"
#include "cpu/testers/traffic_gen/generators.hh"
#include "mem/mem_object.hh"
#include "mem/qport.hh"
#include "params/TrafficGen.hh"

class TrafficGen : public MemObject
{

  private:

    void transition();

    void enterState(uint32_t newState);

    std::string resolveFile(const std::string &name);

    void parseConfig();

    void update();

    void recvReqRetry();

    void noProgress();

    struct Transition {
        uint32_t from;
        uint32_t to;
        double p;
    };

    System* system;

    MasterID masterID;

    const std::string configFile;

    const bool elasticReq;

    const Tick progressCheck;

    EventWrapper<TrafficGen, &TrafficGen::noProgress> noProgressEvent;

    Tick nextTransitionTick;

    Tick nextPacketTick;

    std::vector<std::vector<double> > transitionMatrix;

    uint32_t currState;

    std::unordered_map<uint32_t, BaseGen*> states;

    class TrafficGenPort : public MasterPort
    {
      public:

        TrafficGenPort(const std::string& name, TrafficGen& traffic_gen)
            : MasterPort(name, &traffic_gen), trafficGen(traffic_gen)
        { }

      protected:

        void recvReqRetry() { trafficGen.recvReqRetry(); }

        bool recvTimingResp(PacketPtr pkt);

        void recvTimingSnoopReq(PacketPtr pkt) { }

        void recvFunctionalSnoop(PacketPtr pkt) { }

        Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }

      private:

        TrafficGen& trafficGen;

    };

    TrafficGenPort port;

    PacketPtr retryPkt;

    Tick retryPktTick;

    EventWrapper<TrafficGen, &TrafficGen::update> updateEvent;

    uint64_t numSuppressed;

    Stats::Scalar numPackets;

    Stats::Scalar numRetries;

    Stats::Scalar retryTicks;

  public:

    TrafficGen(const TrafficGenParams* p);

    ~TrafficGen() {}

    BaseMasterPort& getMasterPort(const std::string &if_name,
                                  PortID idx = InvalidPortID) override;

    void init() override;

    void initState() override;

    DrainState drain() override;

    void serialize(CheckpointOut &cp) const override;
    void unserialize(CheckpointIn &cp) override;

    void regStats() override;

};

#endif //__CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__