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decoder.hh
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28  * Authors: Gabe Black
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30 
31 #ifndef __ARCH_X86_DECODER_HH__
32 #define __ARCH_X86_DECODER_HH__
33 
34 #include <cassert>
35 #include <unordered_map>
36 #include <vector>
37 
38 #include "arch/x86/regs/misc.hh"
39 #include "arch/x86/types.hh"
40 #include "base/bitfield.hh"
41 #include "base/misc.hh"
42 #include "base/trace.hh"
43 #include "base/types.hh"
44 #include "cpu/decode_cache.hh"
45 #include "cpu/static_inst.hh"
46 #include "debug/Decoder.hh"
47 
48 namespace X86ISA
49 {
50 
51 class ISA;
52 class Decoder
53 {
54  private:
55  //These are defined and documented in decoder_tables.cc
56  static const uint8_t SizeTypeToSize[3][10];
57  typedef const uint8_t ByteTable[256];
59 
64 
70 
71  protected:
72  struct InstBytes
73  {
78 
80  {}
81  };
82 
83  static InstBytes dummy;
84 
85  //The bytes to be predecoded
88  int chunkIdx;
89  //The pc of the start of fetchChunk
91  //The pc the current instruction started at
93  //The offset into fetchChunk of current processing
94  int offset;
95  //The extended machine instruction being generated
97  //Predecoding state
98  X86Mode mode;
100  uint8_t altOp;
101  uint8_t defOp;
102  uint8_t altAddr;
103  uint8_t defAddr;
104  uint8_t stack;
105 
106  uint8_t getNextByte()
107  {
108  return ((uint8_t *)&fetchChunk)[offset];
109  }
110 
111  void getImmediate(int &collected, uint64_t &current, int size)
112  {
113  //Figure out how many bytes we still need to get for the
114  //immediate.
115  int toGet = size - collected;
116  //Figure out how many bytes are left in our "buffer"
117  int remaining = sizeof(MachInst) - offset;
118  //Get as much as we need, up to the amount available.
119  toGet = toGet > remaining ? remaining : toGet;
120 
121  //Shift the bytes we want to be all the way to the right
122  uint64_t partialImm = fetchChunk >> (offset * 8);
123  //Mask off what we don't want
124  partialImm &= mask(toGet * 8);
125  //Shift it over to overlay with our displacement.
126  partialImm <<= (immediateCollected * 8);
127  //Put it into our displacement
128  current |= partialImm;
129  //Update how many bytes we've collected.
130  collected += toGet;
131  consumeBytes(toGet);
132  }
133 
135  {
136  assert(offset <= sizeof(MachInst));
137  if (offset == sizeof(MachInst)) {
138  DPRINTF(Decoder, "At the end of a chunk, idx = %d, chunks = %d.\n",
139  chunkIdx, instBytes->chunks.size());
140  chunkIdx++;
141  if (chunkIdx == instBytes->chunks.size()) {
142  outOfBytes = true;
143  } else {
144  offset = 0;
146  basePC += sizeof(MachInst);
147  }
148  }
149  }
150 
151  void consumeByte()
152  {
153  offset++;
155  }
156 
157  void consumeBytes(int numBytes)
158  {
159  offset += numBytes;
161  }
162 
163  //State machine state
164  protected:
165  //Whether or not we're out of bytes
167  //Whether we've completed generating an ExtMachInst
168  bool instDone;
169  //The size of the displacement value
171  //The size of the immediate value
173  //This is how much of any immediate value we've gotten. This is used
174  //for both the actual immediate and the displacement.
176 
177  enum State {
193  //We should never get to this state. Getting here is an error.
195  };
196 
198 
199  //Functions to handle each of the states
202  State doPrefixState(uint8_t);
203  State doVex2Of2State(uint8_t);
204  State doVex2Of3State(uint8_t);
205  State doVex3Of3State(uint8_t);
206  State doVexOpcodeState(uint8_t);
207  State doOneByteOpcodeState(uint8_t);
208  State doTwoByteOpcodeState(uint8_t);
211  State doModRMState(uint8_t);
212  State doSIBState(uint8_t);
215 
216  //Process the actual opcode found earlier, using the supplied tables.
217  State processOpcode(ByteTable &immTable, ByteTable &modrmTable,
218  bool addrSizedImm = false);
219  // Process the opcode found with VEX / XOP prefix.
221 
222  protected:
224 
225  typedef MiscReg CacheKey;
226 
229  typedef std::unordered_map<CacheKey, DecodePages *> AddrCacheMap;
231 
233  typedef std::unordered_map<CacheKey, DecodeCache::InstMap *> InstCacheMap;
235 
236  public:
237  Decoder(ISA* isa = nullptr) : basePC(0), origPC(0), offset(0),
238  outOfBytes(true), instDone(false),
240  {
241  memset(&emi, 0, sizeof(emi));
242  mode = LongMode;
244  emi.mode.mode = mode;
245  emi.mode.submode = submode;
246  altOp = 0;
247  defOp = 0;
248  altAddr = 0;
249  defAddr = 0;
250  stack = 0;
251  instBytes = &dummy;
252  decodePages = NULL;
253  instMap = NULL;
254  }
255 
256  void setM5Reg(HandyM5Reg m5Reg)
257  {
258  mode = (X86Mode)(uint64_t)m5Reg.mode;
259  submode = (X86SubMode)(uint64_t)m5Reg.submode;
260  emi.mode.mode = mode;
261  emi.mode.submode = submode;
262  altOp = m5Reg.altOp;
263  defOp = m5Reg.defOp;
264  altAddr = m5Reg.altAddr;
265  defAddr = m5Reg.defAddr;
266  stack = m5Reg.stack;
267 
268  AddrCacheMap::iterator amIter = addrCacheMap.find(m5Reg);
269  if (amIter != addrCacheMap.end()) {
270  decodePages = amIter->second;
271  } else {
272  decodePages = new DecodePages;
273  addrCacheMap[m5Reg] = decodePages;
274  }
275 
276  InstCacheMap::iterator imIter = instCacheMap.find(m5Reg);
277  if (imIter != instCacheMap.end()) {
278  instMap = imIter->second;
279  } else {
281  instCacheMap[m5Reg] = instMap;
282  }
283  }
284 
286  {
287  mode = old->mode;
288  submode = old->submode;
289  emi.mode.mode = mode;
290  emi.mode.submode = submode;
291  altOp = old->altOp;
292  defOp = old->defOp;
293  altAddr = old->altAddr;
294  defAddr = old->defAddr;
295  stack = old->stack;
296  }
297 
298  void reset()
299  {
300  state = ResetState;
301  }
302 
303  void process();
304 
305  //Use this to give data to the decoder. This should be used
306  //when there is control flow.
307  void moreBytes(const PCState &pc, Addr fetchPC, MachInst data)
308  {
309  DPRINTF(Decoder, "Getting more bytes.\n");
310  basePC = fetchPC;
311  offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
312  fetchChunk = data;
313  outOfBytes = false;
314  process();
315  }
316 
318  {
319  return outOfBytes;
320  }
321 
322  bool instReady()
323  {
324  return instDone;
325  }
326 
327  void
329  {
330  if (!nextPC.size()) {
331  int size = basePC + offset - origPC;
333  "Calculating the instruction size: "
334  "basePC: %#x offset: %#x origPC: %#x size: %d\n",
335  basePC, offset, origPC, size);
336  nextPC.size(size);
337  nextPC.npc(nextPC.pc() + size);
338  }
339  }
340 
341  public:
343 
349 };
350 
351 } // namespace X86ISA
352 
353 #endif // __ARCH_X86_DECODER_HH__
#define DPRINTF(x,...)
Definition: trace.hh:212
void process()
Definition: decoder.cc:74
static ByteTable UsesModRMThreeByte0F38
Definition: decoder.hh:62
int displacementSize
Definition: decoder.hh:170
State doVex3Of3State(uint8_t)
Definition: decoder.cc:316
ExtMachInst emi
Definition: decoder.hh:96
bool needMoreBytes()
Definition: decoder.hh:317
State doVex2Of3State(uint8_t)
Definition: decoder.cc:275
static ByteTable Prefixes
Definition: decoder.hh:58
MiscReg CacheKey
Caching for decoded instruction objects.
Definition: decoder.hh:225
void updateOffsetState()
Definition: decoder.hh:134
void moreBytes(const PCState &pc, Addr fetchPC, MachInst data)
Definition: decoder.hh:307
State doTwoByteOpcodeState(uint8_t)
Definition: decoder.cc:398
static ByteTable ImmediateTypeVex[10]
Definition: decoder.hh:69
X86Mode mode
Definition: decoder.hh:98
static const uint8_t SizeTypeToSize[3][10]
Definition: decoder.hh:56
X86SubMode submode
Definition: decoder.hh:99
Bitfield< 19 > pc
Definition: misc.hh:806
bool instReady()
Definition: decoder.hh:322
std::unordered_map< CacheKey, DecodePages * > AddrCacheMap
Definition: decoder.hh:229
uint8_t altOp
Definition: decoder.hh:100
const char data[]
Definition: circlebuf.cc:43
State doPrefixState(uint8_t)
Definition: decoder.cc:178
StaticInstPtr decodeInst(ExtMachInst mach_inst)
void reset()
Definition: decoder.hh:298
Addr pc() const
Definition: types.hh:138
Addr instAddr() const
Returns the memory address the bytes of this instruction came from.
Definition: types.hh:60
uint8_t defOp
Definition: decoder.hh:101
State doSIBState(uint8_t)
Definition: decoder.cc:564
int immediateCollected
Definition: decoder.hh:175
static ByteTable ImmediateTypeThreeByte0F3A
Definition: decoder.hh:68
static ByteTable UsesModRMOneByte
Definition: decoder.hh:60
DecodePages * decodePages
Definition: decoder.hh:228
uint8_t getNextByte()
Definition: decoder.hh:106
static ByteTable UsesModRMTwoByte
Definition: decoder.hh:61
static InstCacheMap instCacheMap
Definition: decoder.hh:234
std::unordered_map< TheISA::ExtMachInst, StaticInstPtr > InstMap
Hash for decoded instructions.
Definition: decode_cache.hh:50
X86SubMode
Definition: types.hh:191
uint8_t stack
Definition: decoder.hh:104
mask
Definition: misc.hh:797
State processOpcode(ByteTable &immTable, ByteTable &modrmTable, bool addrSizedImm=false)
Definition: decoder.cc:449
void consumeBytes(int numBytes)
Definition: decoder.hh:157
State doVexOpcodeState(uint8_t)
Definition: decoder.cc:353
std::unordered_map< CacheKey, DecodeCache::InstMap * > InstCacheMap
Definition: decoder.hh:233
void setM5Reg(HandyM5Reg m5Reg)
Definition: decoder.hh:256
uint64_t MachInst
Definition: types.hh:54
static ByteTable ImmediateTypeTwoByte
Definition: decoder.hh:66
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
AddrCacheMap addrCacheMap
Definition: decoder.hh:230
static ByteTable ImmediateTypeOneByte
Definition: decoder.hh:65
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a machine instruction.
Definition: decoder.cc:681
A sparse map from an Addr to a Value, stored in page chunks.
Definition: decode_cache.hh:54
DecodeCache::AddrMap< Decoder::InstBytes > DecodePages
Definition: decoder.hh:227
State doResetState()
Definition: decoder.cc:43
State doVex2Of2State(uint8_t)
Definition: decoder.cc:245
int size()
Definition: pagetable.hh:146
State doModRMState(uint8_t)
Definition: decoder.cc:509
Decoder(ISA *isa=nullptr)
Definition: decoder.hh:237
Addr npc() const
Definition: types.hh:141
static InstBytes dummy
Definition: decoder.hh:83
uint64_t MiscReg
Definition: registers.hh:94
std::vector< MachInst > masks
Definition: decoder.hh:76
InstBytes * instBytes
Definition: decoder.hh:87
State doDisplacementState()
Definition: decoder.cc:586
State doOneByteOpcodeState(uint8_t)
Definition: decoder.cc:376
void consumeByte()
Definition: decoder.hh:151
State doThreeByte0F38OpcodeState(uint8_t)
Definition: decoder.cc:421
OperatingMode mode
Definition: types.hh:231
const uint8_t ByteTable[256]
Definition: decoder.hh:57
DecodeCache::InstMap * instMap
Definition: decoder.hh:232
static ByteTable ImmediateTypeThreeByte0F38
Definition: decoder.hh:67
void takeOverFrom(Decoder *old)
Definition: decoder.hh:285
State doImmediateState()
Definition: decoder.cc:634
MachInst fetchChunk
Definition: decoder.hh:86
uint8_t size() const
Definition: types.hh:310
State doFromCacheState()
Definition: decoder.cc:144
void updateNPC(X86ISA::PCState &nextPC)
Definition: decoder.hh:328
std::vector< MachInst > chunks
Definition: decoder.hh:75
State doThreeByte0F3AOpcodeState(uint8_t)
Definition: decoder.cc:435
State processExtendedOpcode(ByteTable &immTable)
Bitfield< 3 > addr
Definition: types.hh:81
uint8_t altAddr
Definition: decoder.hh:102
uint8_t defAddr
Definition: decoder.hh:103
static ByteTable UsesModRMThreeByte0F3A
Definition: decoder.hh:63
void getImmediate(int &collected, uint64_t &current, int size)
Definition: decoder.hh:111

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