CS/ECE 752 Advanced Computer Architecture I Fall 2004 Section 1
Instructor Mark D. Hill and T. A. Andrey Litvin
URL: http://www.cs.wisc.edu/~markhill/cs752/Fall2004/

H&P is John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Third Edition, 2002.

HJ&S is Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi, Readings in Computer Architecture, Morgan Kaufmann Publishers, 2000.

Static ILP, Vectors, Multimedia

H&P Chapter 4.

C. McNairy and D. Soltis, Itanium 2 Processor Microarchitecture, IEEE Micro, Mar-Apr 2003, pp. 44-55. Online PDF for University of Wisconsin only.

Intel (R) Itanium (R) Architecture Software Development Manual, URL: http://www.intel.com/design/itanium/manuals/iiasdmanual.htm. See especially Volume 1's (Application Architecture) Chapter 4 (Application Programming Model), 36 pages (reference).

H&P Appendix G: Vector Processors. URL http://books.elsevier.com/companions/1558605967/appendices/1558605967-appe ndix-g.pdf.

Richard M. Russell. The Cray-1 Computer System, Communications of the ACM, January 1978. Reprinted in HJ&S pp. 40-49.

Memory Hierarchy Design

H&P Chapter 5.

Norman P. Jouppi. Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers, Proc. International Symposium on Computer Architecture , June 1990. Reprinted in HJ&S pp. 395-404.

Harold W. Cain and Mikko H. Lipasti. Memory Ordering: A Value-based Approach, Proc. International Symposium on Computer Architecture (ISCA), June 2004. Online PDF for University of Wisconsin only.

The PC Guide: DRAM Technologies, http://www.pcguide.com/ref/ram/tech.htm URL http://www.pcguide.com/ref/ram/tech.htm and ten Next pages (reference).

Bruce Jacob and Trevor Mudge. Virtual Memory on Contemporary Processors, IEEE Micro, vol. 18, no. 4, 1998. Online PDF for University of Wisconsin only.

Wen-Hann Wang, Jean-Loup Baer, and Henry M. Levy. Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy, Proc. International Symposium on Computer Architecture , June 1989. Reprinted in HJ&S pp. 434-442.

Changkyu Kim, Doug Burger, and Stephen W. Keckler. An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches, Proc. Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002. Online PDF for University of Wisconsin only.

I/O

H&P Chapter 7.

David A. Patterson, Garth Gibson, and Randy H. Katz, A Case for Redundant Arrays of Inexpensive Disks (RAID), Proc. ACM SIGMOD Conference, June 1988 David A. Patterson, Garth Gibson, and Randy H. Katz. A Case for Redundant Arrays of Inexpensive Disks (RAID), Proc. ACM SIGMOD Conference, June 1988. Reprinted in HJ&S pp. 474-481.

Matthew Adiletta, Mark Rosenbluth, Debra Bernstein, Gilbert Wolrich, and Hugh Wilkinson. The Next Generation of Intel IXP Network Processors, Intel Technical Journal (ITJ), Volume 6, Issue 3, August 15, 2002. Online PDF.

Multiprocessors

H&P Chapter 6 Sections 6.1, 6.3, & 6.8.