CS/ECE 757 Advanced Computer Architecture II Spring 2005 Section 1
Instructor Mark D. Hill and T. A. Bhavesh Mehta
URL: http://www.cs.wisc.edu/~markhill/cs757/Spring2005/

Likely to be updated.

H&P is John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Third Edition, 2002.

HJ&S is Mark D. Hill, Norman P. Jouppi, and Gurindar S. Sohi, Readings in Computer Architecture, Morgan Kaufmann Publishers, 2000.

Distributed Shared Memory

H&P Sections 6.5 & 6.6 (DSMs and DSM Performance).

James Laudon and Daniel Lenoski The SGI Origin: A ccNUMA Highly Scalable Server, In Proceedings of International Symposium on Computer Architecture, pages 241-251, June 1997. Online PDF for University of Wisconsin only.

H&P Section 6.8 (Memory Consistency).

Sarita V. Adve and Kourosh Gharachorloo, Shared Memory Consistency Models: A Tutorial, IEEE Computer, 29(12):66-76, December 1996. Online PDF for University of Wisconsin only.

Mark D. Hill, Multiprocessors Should Support Simple Memory Consistency Models, IEEE Computer, August 1998, pp. 28-34. Online PDF for University of Wisconsin only.

H&P Sections 6.9-6.15 (Rest of Chapter 6).

Cristiana Amza, et al., TreadMarks: Shared Memory Computing on Networks of Workstation, IEEE Computer, 29(2):18-28, February 1996. Online PDF for University of Wisconsin only.

J. M. Tendler, J. S. Dodson, J. S. Fields, Jr., H. Le, and B. Sinharoy, POWER4 system microarchitecture, IBM J. of Research and Development,, 2002, vol. 46, no. 1, pp 5., Online PDF for University of Wisconsin only.

Ron Kalla, Balaram Simharoy, and Joel Tendler, POWER5 Slides, Hot Chips,, 2003 Online PDF for University of Wisconsin only. Reference.

Luiz Andre Barroso, et al., Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing, Proc. International Symposium on Computer Architecture, June 2000, pp. 282-293. Online PDF for University of Wisconsin only.

Milo M. K. Martin, Mark D. Hill, and David A. Wood, Token Coherence: Decoupling Performance and Correctness, International Symposium on Computer Architecture, June 2003 Online PDF.

Alaa R. Alameldeen, Milo M.K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Daniel J. Sorin, Mark D. Hill and David A. Wood, Simulating a $2M Commercial Server on a $2K PC, IEEE Computer, February 2003. Online PDF. Reference.

Scalable Systems

H&P Sections 8.10-8.12 (Clusters with Google Case Study).

Luiz Andre Barroso, Jeffrey Dean, Urs Holzle, Web Search For a Planet: The Google Cluster Architecture, IEEE Micro, 23(2):22-28, March-April 2003. Online PDF for University of Wisconsin only.

Steven L. Scott, Synchronization and Communication in the T3E Multiprocessor, Proceedings of International Conference on Architectural Support for Programming Languages and Operating Systems, pages 26-36, October 1996. Online PDF for University of Wisconsin only.

Steve Scott, Cray X1 Slides, Wisconsin,, 2003. Online PDF for University of Wisconsin only. Reference.

Interconnection Networks

H&P Sections 8.1-8.9 & 8.14-8.16 (Interconnection Networks).

Shubhendu S. Mukherjee, Peter Bannon, Steven Lang, Aaron Spink, and David Webb The Alpha 21364 Network Architecture, IEEE Micro, January-Febraury 2002, pp. 45-54. Online PDF for University of Wisconsin only.

Availability, Dataflow, & Single Instruction Multiple Data (SIMD)

Shubhendu S. Mukherjee, Joel Emer, and Steven K. Reinhardt, The Soft Error Problem: An Architectural Perspective, High-Performance Computer Architecture, Febraury 2005, pp. TBA. Online PDF for University of Wisconsin only. Reference.

Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood, SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery, International Symposium on Computer Architecture, May 2002, pp. 123-134. Online PDF. Online Talk PPT.

Milos Prvulovic, Zheng Zhang, and Josep Torrellas, ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors, International Symposium on Computer Architecture, May 2002, pp. 111-122. Online PDF for University of Wisconsin only.

Arvind and R. S. Nikhil, Executing a Program on the {MIT} Tagged-Token Dataflow Architecture, IEEE Trans. on Computers, March 1990, pp. 300-318. Online PDF for University of Wisconsin only. Reprinted in HJ&S pp. 323-341.

Steve Swanson, Andrew Schwerin, Andrew Petersen, Mark Oskin and Susan Eggers, Threads on the Cheap: Multithreaded Execution in a WaveCache Processor, ISCA Workshop on Complexity-effective Design, June 2004. Online PDF for University of Wisconsin only.

Charles E. Leiserson and others, The Network Architecture of the Connection Machine CM-5, The Journal of Parallel and Distributed Computing, March 15, 1996 (revised from SPAA 1992). Online PDF for University of Wisconsin only.

M. Gokhale, B. Holmes, and K. Iobst, Processing in Memory: The Terasys Massively Parallel PIM Array, IEEE Computer, April 1995, pp. 23-31. Online PDF for University of Wisconsin only. Reprinted in HJ&S pp. 542-550.