Wireline Business Group-DSL Broadband ASICs

Aug 2006 - Jul 2010

I was part of the wireline business group (which was spun off as Lantiq in Nov 2010). I was responsible for the microarchitecture, RTL design and verification of the system interface and the block encoder/decoder blocks that went into the Vinax family of ASICs that targeted the central office broadband DSL market. Having worked in three full chip design cycles, I have good experience working with all aspects of front end design : From specification, architecture, microarchitecture, design, verification, firmware development, emulation, synthesis and timing closure.

Our team designed chips that enabled broadband over DSL. I was involved in design cycles of 3 chips. I worked on two modules for the most part :

System interface module

I was responsible for the module that implemented a family of packet-oriented, chip-to-chip interfaces such as PL-3, Utopia, SPI3 and SSSMII and (S)GMII. I supported synthesis and STA teams to ease timing closure of this multi-clock module. And I got a chance to interact closely with the firmware team to enhance programmability that enabled multiple customer support.

Block encoder and decoder design

I designed and functionally verified Reed Solomon encoder. I helped integrate a Welch-Berlekamp decoder delivered as a third party IP . Also I verified the framer, block encoder-decoder and interleaver sub-modules using Specman-e.

Microsoft Research, Redmond, WA

eXtreme Computing Group

May 2012 - Aug 2012

I ported the GEMS simulator code to Windows and integrated it with the Microsoft E2 dynamic multicore simulator and helped create memory subsystem and cache coherence configurations to help in E2’s evaluations.

Infineon, Munich

Wireline Business Group

Jun 2005 - Jul 2006

I got introduced to FGPAs here. I worked on the bring up of a “Generalized emulation and debugging board”, which tried to create an interface independent emulation platform. I made the system accessible remotely by putting together a processor (NIOS II from Altera) and Ethernet mac (OpenCores) on board an Altera Cyclone FPGA.