In MICRO'46 we introduce a circuit failure prediction technique called Virtually Aged Sampling-DMR. As the gates in a microprocessor wear-out, their threshold voltage and their propagation delay increase. Reducing supply voltage or increasing the frequency of operation has a similar effect. Using existing circuitry like DVS, we mimic aging during short periods of processor operation. Errors occuring in the sampling windows indicate an impending failure - we detect them using Sampling-DMR. Wearout in the critical paths are naturally exposed by design. For non-critical paths, we design circuitry that exposes the degradation as faults.

Cross-layered ideas are hard to evaluate. For example, the one above tackles wear-out (we understand how that happens at the gate level) at the architecture level. I developed a platform that uses {Xilinx Zynq FPGA + OpenRISC Processor + VCS + HSPICE + MOSRA + Transient fault models} to evaluate such ideas.

Here is a poster we presented at the Affiliates Conference in October 2012 : The World's First Free and OpenSource Out of Order Processor

I developed a superscalar (2 issue) out of order processor, a 2 issue in-order processor. The OpenRISC OR1K architecture now has an ASIC proven RTL implementation (single issue in order), the GNU toolchain adapted, and several lightweight linux kernels ported.