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gem5
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#include "arch/alpha/generated/max_inst_regs.hh"#include "arch/alpha/ipr.hh"#include "base/types.hh"Go to the source code of this file.
Classes | |
| union | AlphaISA::AnyReg |
Namespaces | |
| AlphaISA | |
Typedefs | |
| typedef uint8_t | AlphaISA::RegIndex |
| typedef uint64_t | AlphaISA::IntReg |
| typedef double | AlphaISA::FloatReg |
| typedef uint64_t | AlphaISA::FloatRegBits |
| typedef uint64_t | AlphaISA::MiscReg |
| typedef uint8_t | AlphaISA::CCReg |
Enumerations | |
| enum | AlphaISA::MiscRegIndex { AlphaISA::MISCREG_FPCR = NumInternalProcRegs, AlphaISA::MISCREG_UNIQ, AlphaISA::MISCREG_LOCKFLAG, AlphaISA::MISCREG_LOCKADDR, AlphaISA::MISCREG_INTR, AlphaISA::NUM_MISCREGS } |
| enum | AlphaISA::DependenceTags { AlphaISA::FP_Reg_Base = NumIntRegs, AlphaISA::CC_Reg_Base = FP_Reg_Base + NumFloatRegs, AlphaISA::Misc_Reg_Base = CC_Reg_Base + NumCCRegs, AlphaISA::Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs } |
Variables | |
| const int | AlphaISA::MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1 |
| const RegIndex | AlphaISA::ZeroReg = 31 |
| const RegIndex | AlphaISA::StackPointerReg = 30 |
| const RegIndex | AlphaISA::GlobalPointerReg = 29 |
| const RegIndex | AlphaISA::ProcedureValueReg = 27 |
| const RegIndex | AlphaISA::ReturnAddressReg = 26 |
| const RegIndex | AlphaISA::ReturnValueReg = 0 |
| const RegIndex | AlphaISA::FramePointerReg = 15 |
| const RegIndex | AlphaISA::SyscallNumReg = 0 |
| const RegIndex | AlphaISA::FirstArgumentReg = 16 |
| const RegIndex | AlphaISA::SyscallPseudoReturnReg = 20 |
| const RegIndex | AlphaISA::SyscallSuccessReg = 19 |
| const int | AlphaISA::NumIntArchRegs = 32 |
| const int | AlphaISA::NumPALShadowRegs = 8 |
| const int | AlphaISA::NumFloatArchRegs = 32 |
| const int | AlphaISA::NumIntRegs = NumIntArchRegs + NumPALShadowRegs |
| const int | AlphaISA::NumFloatRegs = NumFloatArchRegs |
| const int | AlphaISA::NumCCRegs = 0 |
| const int | AlphaISA::NumMiscRegs = NUM_MISCREGS |
| const int | AlphaISA::TotalNumRegs |