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Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
[detail level 12345]
oNAlphaISA
oNArmISA
oNBigEndianGuest
oNBitfieldBackend
oNBrig
oNContextSwitchTaskIdSpecial TaskIds that are used for per-context-switch stats dumps and Cache Occupancy
oNCopyEngineReg
oNcp
oNDebug
oNDecodeCache
oNDRAMSimForward declaration to avoid includes
oNFreeBSD
oNGenericISA
oNHsailISA
oNiGbReg
oNKernel
oNLinux
oNLittleEndianGuest
oNm5
oNMinorMinor contains all the definitions within the MinorCPU apart from the CPU class itself
oNMipsISA
oNNet
oNNullISA
oNPowerISA
oNProbePointsName space containing shared probe point declarations
oNProtoMessage
oNPs2
oNPseudoInst
oNRiscvISA
oNSimClockThese are variables that are set based on the simulator frequency
oNSinic
oNSparcISA
oNStats
oNstdOverload hash function for BasicBlockRange type
oNTheISA
oNTrace
oNUnitTest
oNX86ISAThis is exposed globally, independent of the ISA
oNX86ISAInst
oC_cl_event
oCA9SCU
oCAbstractBloomFilter
oCAbstractCacheEntry
oCAbstractController
oCAbstractEntry
oCAbstractMemoryAn abstract memory represents a contiguous block of physical memory, with an associated address range, and also provides basic functionality for reading and writing this memory without any timing information
oCAbstractNVMThis is an interface between the disk interface (which will handle the disk data transactions) and the timing model
oCAbstractReplacementPolicy
oCAccessTraceForAddress
oCActivityRecorderActivityRecorder helper class that informs the CPU if it can switch over to being idle or not
oCAddressProfiler
oCAddrMapperAn address mapper changes the packet addresses in going from the slave port side of the mapper to the master port side
oCAddrOperandBase
oCAddrRangeEncapsulates an address range, and supports a number of tests to check if two ranges intersect, if a range contains a specific address etc
oCAddrRangeMapThe AddrRangeMap uses an STL map to implement an interval tree for address decoding
oCAlphaAccess
oCAlphaBackdoorMemory mapped interface to the system console
oCAlphaLinux
oCAlphaProcess
oCAlphaSystem
oCAmbaDevice
oCAmbaDmaDevice
oCAmbaFake
oCAmbaIntDevice
oCAmbaPioDevice
oCAnnotateDumpCallback
oCaout_exechdrFunky Alpha 64-bit a.out header used for PAL code
oCAoutObject
oCArchTimerPer-CPU architected timer
oCArguments
oCArmFreebsd32
oCArmFreebsd64
oCArmFreebsdProcess32A process with emulated Arm/Freebsd syscalls
oCArmFreebsdProcess64A process with emulated Arm/Freebsd syscalls
oCArmFreebsdProcessBits
oCArmKvmCPUARM implementation of a KVM-based hardware virtualized CPU
oCArmLinux32
oCArmLinux64
oCArmLinuxProcess32A process with emulated Arm/Linux syscalls
oCArmLinuxProcess64A process with emulated Arm/Linux syscalls
oCArmLinuxProcessBits
oCArmProcess
oCArmProcess32
oCArmProcess64
oCArmSystem
oCArmV8KvmCPUThis is an implementation of a KVM-based ARMv8-compatible CPU
oCAtagCmdline
oCAtagCore
oCAtagHeader
oCAtagMem
oCAtagNone
oCAtagRev
oCAtagSerial
oCataparams
oCAtomicOpAdd
oCAtomicOpAnd
oCAtomicOpCAS
oCAtomicOpDec
oCAtomicOpExch
oCAtomicOpFunctor
oCAtomicOpInc
oCAtomicOpMax
oCAtomicOpMin
oCAtomicOpOr
oCAtomicOpSub
oCAtomicOpXor
oCAtomicSimpleCPU
oCAUXU
oCAuxVector
oCBackingStoreEntryA single entry for the backing store
oCBadDeviceBadDevice This device just panics when accessed
oCBankedArray
oCBareIronMipsSystemThis class contains linux specific system code (Loading, Events)
oCBarrier
oCBaseArmKvmCPU
oCBaseBufferArgBase class for BufferArg and TypedBufferArg, Not intended to be used directly
oCBaseCacheA basic cache interface
oCBaseCPU
oCBaseDynInst
oCBaseGenBase class for all generators, with the shared functionality and virtual functions for entering, executing and leaving the generator
oCBaseGic
oCBaseGicRegisters
oCBaseGlobalEventCommon base class for GlobalEvent and GlobalSyncEvent
oCBaseGlobalEventTemplateFunky intermediate class to support CRTP so that we can have a common constructor to create the local events, even though the types of the local events are defined in the derived classes
oCBaseKvmCPUBase class for KVM based CPU models
oCBaseKvmTimerTimer functions to interrupt VM execution after a number of simulation ticks
oCBaseMasterPortA BaseMasterPort is a protocol-agnostic master port, responsible only for the structural connection to a slave port
oCBaseMemProbeBase class for memory system probes accepting Packet instances
oCBaseO3CPU
oCBaseO3DynInst
oCBaseOperand
oCBasePixelPumpTiming generator for a pixel-based display
oCBasePrefetcher
oCBaseRegOperand
oCBaseRemoteGDB
oCBaseSetAssocA BaseSetAssoc cache tag store
oCBaseSimpleCPU
oCBaseSlavePortA BaseSlavePort is a protocol-agnostic slave port, responsible only for the structural connection to a master port
oCBaseTagsA common base class of Cache tagstore objects
oCBaseTagsCallback
oCBaseTagsDumpCallback
oCBaseTLB
oCBaseXBarThe base crossbar contains the common elements of the non-coherent and coherent crossbar
oCBasicBlock
oCBasicExtLink
oCBasicIntLink
oCBasicLink
oCBasicPioDevice
oCBasicRouter
oCBasicSignal
oCBiModeBPImplements a bi-mode branch predictor
oCBitmap
oCBlockBloomFilter
oCBPredUnitBasically a wrapper class to hold both the branch predictor and the BTB
oCBreakPCEvent
oCBridgeA bridge is used to interface two different crossbars (or in general a memory-mapped master and slave), with buffering for requests and responses
oCBrigObject
oCBrigRegOperandInfo
oCBufferArgBufferArg represents an untyped buffer in target user space that is passed by reference to an (emulated) system call
oCBulkBloomFilter
oCCacheA template-policy based cache
oCCacheBlkA Basic Cache block
oCCacheBlkIsDirtyVisitorCache block visitor that determines if there are dirty blocks in a cache
oCCacheBlkPrintWrapperSimple class to provide virtual print() method on cache blocks without allocating a vtable pointer for every single cache block
oCCacheBlkVisitorBase class for cache block visitor, operating on the cache block base class (later subclassed for the various tag classes)
oCCacheBlkVisitorWrapperWrap a method and present it as a cache block visitor
oCCacheMemory
oCCacheRecorder
oCCacheSetAn associative set of cache blocks
oCCallArgMem
oCCallbackGeneric callback class
oCCallbackQueue
oCCheck
oCCheckerTemplated Checker class
oCCheckerCPUCheckerCPU class
oCCheckerThreadContextDerived ThreadContext class for use with the Checker
oCCheckpointIn
oCCheckTable
oCChunkGeneratorThis class takes an arbitrary memory region (address/length pair) and generates a series of appropriately (e.g
oCCircleBufCircular buffer backed by a vector
oCClDriver
oCClockDomainThe ClockDomain provides clock to group of clocked objects bundled under the same clock domain
oCClockedHelper class for objects that need to be clocked
oCClockedObjectExtends the SimObject with a clock and accessor functions to relate ticks to the cycles of the object
oCClockedObjectDumpCallback
oCCoherentXBarA coherent crossbar connects a number of (potentially) snooping masters and slaves, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses
oCCommandReg
oCCommMonitorThe communication monitor is a MemObject which can monitor statistics of the communication happening between two ports in the memory system
oCComputeUnit
oCConditionRegisterState
oCConsumer
oCControlFlowInfo
oCCopyEngine
oCCountedExitEvent
oCCowDiskCallback
oCCowDiskImageSpecialization for accessing a copy-on-write disk image layer
oCCPA
oCCPAIgnoreSymbol
oCCpuEventThis class creates a global list of events that need a pointer to a thread context
oCCpuEventWrapper
oCCpuLocalTimer
oCCredit
oCCreditLink
oCCRegOperand
oCCrossbarSwitch
oCCustomNoMaliGpu
oCCxxConfigDirectoryEntryConfig details entry for a SimObject
oCCxxConfigFileBaseConfig file wrapper providing a common interface to CxxConfigManager
oCCxxConfigManagerThis class allows a config file to be read into gem5 (generating the appropriate SimObjects) from C++
oCCxxConfigParamsBase for peer classes of SimObjectParams derived classes with parameter modifying member functions
oCCxxIniFileCxxConfigManager interface for using .ini files
oCCyclesCycles is a wrapper class for representing cycle counts, i.e
oCDataBlock
oCDataTranslationThis class represents part of a data address translation
oCDebugBreakEvent
oCDecoderFaultInst
oCDefaultBTB
oCDefaultCommitDefaultCommit handles single threaded and SMT commit
oCDefaultDecodeDefaultDecode class handles both single threaded and SMT decode
oCDefaultDecodeDefaultRenameStruct that defines the information passed from decode to rename
oCDefaultFetchDefaultFetch class handles both single threaded and SMT fetch
oCDefaultFetchDefaultDecodeStruct that defines the information passed from fetch to decode
oCDefaultIEWDefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback)
oCDefaultIEWDefaultCommitStruct that defines the information passed from IEW to commit
oCDefaultRenameDefaultRename handles both single threaded and SMT rename
oCDefaultRenameDefaultIEWStruct that defines the information passed from rename to IEW
oCDependencyEntryNode in a linked list
oCDependencyGraphArray of linked list that maintains the dependencies between producing instructions and consuming instructions
oCDerivedClockDomainThe derived clock domains provides the notion of a clock domain that is connected to a parent clock domain that can either be a source clock domain or a derived clock domain
oCDerivO3CPU
oCDeviceFDEntryHolds file descriptors needed to simulate devices opened with pseudo files (commonly with calls to ioctls)
oCDirectedGenerator
oCDirectoryMemory
oCDiskImageBasic interface for accessing a disk image
oCDisplayTimings
oCDistEtherLinkModel for a fixed bandwidth full duplex ethernet link
oCDistHeaderPkt
oCDistIfaceThe interface class to talk to peer gem5 processes
oCDmaCallbackDMA callback class
oCDmaDevice
oCDmaPort
oCDmaReadFifoBuffered DMA engine helper class
oCDMARequest
oCDMASequencer
oCDmesgEntry
oCDNR
oCdp_regsEthernet device registers
oCdp_rom
oCDrainableInterface for objects that might require draining before checkpointing
oCDrainManagerThis class coordinates draining of a System
oCDRAMCtrlThe DRAM controller is a single-channel memory controller capturing the most important timing constraints associated with a contemporary DRAM
oCDramGenDRAM specific generator is for issuing request with variable page hit length and bank utilization
oCDRAMPowerDRAMPower is a standalone tool which calculates the power consumed by a DRAM in the system
oCDramRotGen
oCDRAMSim2
oCDRAMSim2WrapperWrapper class to avoid having DRAMSim2 names like ClockDomain etc clashing with the normal gem5 world
oCDRegOperand
oCDtbObject
oCDumbTODDumbTOD simply returns some idea of time when read
oCDummyCheckerSpecific non-templated derived class used for SimObject configuration
oCDumpStatsPCEvent
oCDVFSHandlerDVFS Handler class, maintains a list of all the domains it can handle
oCecoff_aouthdr
oCecoff_exechdr
oCecoff_extsym
oCecoff_fdr
oCecoff_filehdr
oCecoff_scnhdr
oCecoff_sym
oCecoff_symhdr
oCEcoffObject
oCElasticTraceThe elastic trace is a type of probe listener and listens to probe points in multiple stages of the O3CPU
oCElfObject
oCEmbeddedPyBind
oCEmbeddedPython
oCEmulatedDriverEmulatedDriver is an abstract base class for fake SE-mode device drivers
oCEndQuiesceEventEvent for timing out quiesce instruction
oCEnergyCtrl
oCEtherBus
oCEtherDevBaseDummy class to keep the Python class hierarchy in sync with the C++ object hierarchy
oCEtherDeviceThe base EtherObject class, allows for an accesor function to a simobj that returns the Port
oCEtherDump
oCEtherInt
oCEtherLink
oCEtherObjectThe base EtherObject class, allows for an accesor function to a simobj that returns the Port
oCEtherSwitch
oCEtherTapBase
oCEtherTapInt
oCEtherTapStub
oCEthPacketData
oCEvent
oCEventBaseCommon base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions
oCEventManager
oCEventQueueQueue of events sorted in time order
oCEventWrapper
oCExecContextThe ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model
oCExecStage
oCExitLogger
oCExternalMaster
oCExternalSlave
oCFailUnimplementedStatic instruction class for unimplemented instructions that cause simulator termination
oCFALRUA fully associative LRU cache
oCFALRUBlkA fully associative cache block
oCFaultBase
oCFaultModel
oCFDArray
oCFDEntryHolds a single file descriptor mapping and that mapping's data for processes running in syscall emulation mode
oCFetchStage
oCFetchUnit
oCFifoSimple FIFO implementation backed by a circular buffer
oCFileFDEntryHolds file descriptors for host-backed files; host-backed files are files which were opened on the physical machine where the simulation is running (probably the thing on/under your desk)
oCFlags
oCFlashDeviceFlash Device model The Flash Device model is a timing model for a NAND flash device
oCflit
oCflitBuffer
oCFloat16
oCFrameBufferInternal gem5 representation of a frame buffer
oCFreeBSDThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha FreeBSD syscall interface
oCFreebsdAlphaSystem
oCFreebsdArmSystem
oCFSTranslatingPortProxyA TranslatingPortProxy in FS mode translates a virtual address to a physical address and then calls the read/write functions of the port
oCFUDesc
oCFullO3CPUFullO3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages
oCFuncPageTableDeclaration of functional page table
oCFunctionProfile
oCFunctionRefOperand
oCFuncUnit
oCFUPoolPool of FU's, specific to the new CPU model
oCFutexKeyFutexKey class defines an unique identifier for a particular futex in the system
oCFutexMapFutexMap class holds a map of all futexes used in the system
oCFXSave
oCGarnetExtLink
oCGarnetIntLink
oCGarnetNetwork
oCGarnetSyntheticTraffic
oCGdbCommand
oCGDBListener
oCGenericAlignmentFault
oCGenericArmPciHost
oCGenericArmSystem
oCGenericPageTableFault
oCGenericPciHostConfigurable generic PCI host interface
oCGenericTimer
oCGenericTimerISA
oCGenericTimerMem
oCGenericTLB
oCGicv2m
oCGicv2mFrameUltimately this class should be embedded in the Gicv2m class, but this confuses Python as 'Gicv2m::Frame' gets interpreted as 'Frame' in namespace Gicv2m
oCGlobalEventThe main global event class
oCGlobalMemPipeline
oCGlobalsContainer for serializing global variables (not associated with any serialized object)
oCGlobalSimLoopExitEvent
oCGlobalSyncEventA special global event that synchronizes all threads and forces them to process asynchronously enqueued events
oCGPUCoalescer
oCGPUCoalescerRequest
oCGpuDispatcher
oCGPUDynInst
oCGPUExecContext
oCGPUStaticInst
oCH3BloomFilter
oCHBFDEntryExtends the base class to include a host-backed file descriptor field that records the integer used to represent the file descriptor on the host and the file's flags
oCHDLcd
oCHexFile
oCHistogram
oCHMCControllerHMC Controller, in general, is responsible for translating the host protocol (AXI for example) to serial links protocol
oCHostState
oCHsaCode
oCHsaDriverSizes
oCHsailCode
oCHsaKernelInfo
oCHsaObject
oCHsaQueueEntry
oCI2CBus
oCI2CDevice
oCIdeControllerDevice model for an Intel PIIX4 IDE controller
oCIdeDiskIDE Disk device model
oCIdleGenThe idle generator does nothing
oCIdleStartEvent
oCIGbE
oCIGbEInt
oCImmOp
oCImmOperand
oCIndirectPredictor
oCIniFileThis class represents the contents of a ".ini" file
oCInputUnit
oCInstructionQueueA standard instruction queue class
oCIntel8254TimerProgrammable Interval Timer (Intel 8254)
oCIntrControl
oCInvalidateGenerator
oCIob
oCIsaFakeIsaFake is a device that returns, BadAddr, 1 or 0 on all reads and rites
oCIssueStruct
oCKernelLaunchStaticInst
oCKvmKVM parent interface
oCKvmDeviceKVM device wrapper
oCKvmFPReg
oCKvmKernelGicV2KVM in-kernel GIC abstraction
oCKvmVMKVM VM container
oCLabel
oCLabelMap
oCLabelOperand
oCLdsChunkThis represents a slice of the overall LDS, intended to be associated with an individual workgroup
oCLdsState
oCLinearEquationThis class describes a linear equation with constant coefficients
oCLinearGenThe linear generator generates sequential requests from a start to an end address, with a fixed block size
oCLinearSystem
oCLinkEntry
oCLinkOrder
oCLinuxThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha Linux syscall interface
oCLinuxAlphaSystemThis class contains linux specific system code (Loading, Events)
oCLinuxArmSystem
oCLinuxMipsSystemThis class contains linux specific system code (Loading, Events)
oCLinuxX86System
oCListenSocket
oCListOperand
oCLocalBPImplements a local predictor that uses the PC to index into a table of counters
oCLocalMemPipeline
oCLocalSimLoopExitEvent
oCLockedAddrLocked address class that represents a physical address and a context id
oCLogger
oCLRU
oCLRUPolicy
oCLSB_CountingBloomFilter
oCLSQ
oCLSQUnitClass that implements the actual LQ and SQ for each specific thread
oCLTAGE
oCltseqnum
oCm5_twin32_t
oCm5_twin64_t
oCMachineID
oCMakeCallbackHelper template class to turn a simple class member function into a callback
oCMaltaTop level class for Malta Chipset emulation
oCMaltaCChipMalta CChip CSR Emulation
oCMaltaIOMalta I/O device is a catch all for all the south bridge stuff we care to implement
oCMasterPortA MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the three different level of transport functions
oCMathExpr
oCMathExprPowerModelA Equation power model
oCMC146818Real-Time Clock (MC146818)
oCMcrMrcMiscInstCertain mrc/mcr instructions act as nops or flush the pipe based on what register the instruction is trying to access
oCMcrrOp
oCMemCheckerMemChecker
oCMemCheckerMonitorImplements a MemChecker monitor, to be inserted between two ports
oCMemCmd
oCMemDepUnitMemory dependency unit class
oCMemFootprintProbeProbe to track footprint of accessed memory Two granularity of footprint measurement i.e
oCMemObjectExtends the ClockedObject with accessor functions to get its master and slave ports
oCMemStateThis class holds the memory state for the Process class and all of its derived, architecture-specific children
oCMemTestTests a cache coherent memory system by generating false sharing and verifying the read data against a reference updated on the completion of writes
oCMemTraceProbe
oCMessage
oCMessageBuffer
oCMessageMasterPort
oCMessageSlavePort
oCMicrocodeRom
oCMinorCPUMinorCPU is an in-order CPU model with four fixed pipeline stages:
oCMinorFUA functional unit that can execute any of opClasses operations with a single op(eration)Lat(ency) and issueLat(ency) associated with the unit rather than each operation (as in src/FuncUnit)
oCMinorFUPoolA collection of MinorFUs
oCMinorFUTimingExtra timing capability to allow individual ops to have their source register dependency latencies tweaked based on the ExtMachInst of the source instruction
oCMinorOpClassBoxing for MinorOpClass to get around a build problem with C++11 but also allow for future additions to op class checking
oCMinorOpClassSetWrapper for a matchable set of op classes
oCMipsAccess
oCMipsLinux
oCMipsLinuxProcessA process with emulated Mips/Linux syscalls
oCMipsProcess
oCMipsSystem
oCMiscRegRegImmOp
oCMmDisk
oCMrrcOp
oCMrsOp
oCMSHRMiss Status and handling Register
oCMSHRQueueA Class for maintaining a list of pending and allocated memory requests
oCMSICAPDefines the MSI Capability register and its associated bitfields for the a PCI/PCIe device
oCMSIXDefines the MSI-X Capability register and its associated bitfields for a PCIe device
oCMSIXCAP
oCMSIXPbaEntry
oCMSIXTable
oCMsrBase
oCMsrImmOp
oCMsrRegOp
oCMultiBitSelBloomFilter
oCMultiGrainBloomFilter
oCMultiLevelPageTableThis class implements an in-memory multi-level page table that can be configured to follow ISA specifications
oCMuxingKvmGic
oCNamed
oCNDRange
oCNetDest
oCNetwork
oCNetworkInterface
oCNetworkLink
oCNoArchPageTableFaux page table class indended to stop the usage of an architectural page table, when there is none defined for a particular ISA
oCNoMaliGpu
oCNoncoherentXBarA non-coherent crossbar connects a number of non-snooping masters and slaves, and routes the request and response packets based on the address
oCNonCountingBloomFilter
oCNoRegAddrOperand
oCns_desc32
oCns_desc64
oCNSGigENS DP83820 Ethernet device model
oCNSGigEInt
oCO3CheckerSpecific non-templated derived class used for SimObject configuration
oCO3CPUImplImplementation specific struct that defines several key types to the CPU, the stages within the CPU, the time buffers, and the DynInst
oCO3ThreadContextDerived ThreadContext class for use with the O3CPU
oCO3ThreadStateClass that has various thread state, such as the status, the current instruction being processed, whether or not the thread has a trap pending or is being externally updated, the ThreadContext pointer, etc
oCObjectFile
oCObjectMatch
oCOFSchedulingPolicy
oCOpDesc
oCOperatingSystemThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to an operating system syscall interface
oCOPTR
oCOutputDirectoryInterface for creating files in a gem5 output directory
oCOutputFile
oCOutputStream
oCOutputUnit
oCOutVcState
oCP9MsgHeader
oCP9MsgInfo
oCPacketA Packet is used to encapsulate a transfer between two objects in the memory system (e.g., the L1 and L2 cache)
oCPacketFifo
oCPacketFifoEntry
oCPacketQueueA packet queue is a class that holds deferred packets and later sends them using the associated slave port or master port
oCPageTableBaseDeclaration of base class for page table
oCPAL
oCPanicPCEvent
oCPc
oCpcap_file_header
oCpcap_pkthdr
oCPCEvent
oCPCEventQueue
oCPciBusAddr
oCPCIConfig
oCPciDevicePCI device, base implementation is only config space
oCPciHostThe PCI host describes the interface between PCI devices and a simulated system
oCPciVirtIO
oCpdr
oCPerfectCacheLineState
oCPerfectCacheMemory
oCPerfectSwitch
oCPerfKvmCounterAn instance of a performance counter
oCPerfKvmCounterConfigPerfEvent counter configuration
oCPerfKvmTimerPerfEvent based timer using the host's CPU cycle counter
oCPersistentTable
oCPersistentTableEntry
oCPhysicalMemoryThe physical memory encapsulates all memories in the system and provides basic functionality for accessing those memories without going through the memory system and interconnect
oCPhysRegFileSimple physical register file class
oCPioDeviceThis device is the base class which all devices senstive to an address range inherit from
oCPioPortProgrammed i/o port that all devices that are sensitive to an address range use
oCPipeFDEntryHolds the metadata needed to maintain the mappings for file descriptors allocated with the pipe() system calls and its variants
oCPixelInternal gem5 representation of a Pixel
oCPixelConverterConfigurable RGB pixel converter
oCPl011
oCPL031
oCPl050
oCPl111
oCPl390
oCPlatform
oCPMCAPDefines the Power Management capability register and all its associated bitfields for a PCIe device
oCPollEvent
oCPollQueue
oCPoolManager
oCPortPorts are used to interface memory objects to each other
oCPortProxyThis object is a proxy for a structural port, to be used for debug accesses
oCPosixKvmTimerTimer based on standard POSIX timers
oCPowerLinux
oCPowerLinuxProcessA process with emulated PPC/Linux syscalls
oCPowerModelA PowerModel is a class containing a power model for a SimObject
oCPowerModelStateA PowerModelState is an abstract class used as interface to get power figures out of SimObjects
oCPowerProcess
oCPrdEntry
oCPrdTableEntry
oCPrefetchEntry
oCPrefetcher
oCPrintableAbstract base class for objects which support being printed to a stream for debugging
oCProbeListenerProbeListener base class; here to simplify things like containers containing multiple types of ProbeListener
oCProbeListenerArgProbeListenerArg generates a listener for the class of Arg and the class type T which is the class containing the function that notify will call
oCProbeListenerArgBaseProbeListenerArgBase is used to define the base interface to a ProbeListenerArg (i.e the notify method on specific type)
oCProbeListenerObjectThis class is a minimal wrapper around SimObject
oCProbeManagerProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners with probe points
oCProbePointProbeListener base class; again used to simplify use of ProbePoints in containers and used as to define interface for adding removing listeners to the ProbePoint
oCProbePointArgProbePointArg generates a point for the class of Arg
oCProcess
oCProfileNode
oCProfiler
oCProtoInputStreamA ProtoInputStream wraps a coded stream, potentially with decompression, based on looking at the file name
oCProtoOutputStreamA ProtoOutputStream wraps a coded stream, potentially with compression, based on looking at the file name
oCProtoStreamA ProtoStream provides the shared functionality of the input and output streams
oCProxyThreadContextProxyThreadContext class that provides a way to implement a ThreadContext without having to derive from it
oCPseudoLRUPolicyImplementation of tree-based pseudo-LRU replacement
oCPXCAPDefines the PCI Express capability register and its associated bitfields for a PCIe device
oCPybindSimObjectResolverResolve a SimObject name using the Pybind configuration
oCPyEventPyBind wrapper for Events
oCQueueA high-level queue interface, to be used by both the MSHR queue and the write buffer
oCQueuedMasterPortThe QueuedMasterPort combines two queues, a request queue and a snoop response queue, that both share the same port
oCQueuedPrefetcher
oCQueuedSlavePortA queued port is a port that has an infinite queue for outgoing packets and thus decouples the module that wants to send request/responses from the flow control (retry mechanism) of the port
oCQueueEntryA queue entry base class, to be used by both the MSHRs and write-queue entries
oCRandom
oCRandomGenThe random generator is similar to the linear one, but does not generate sequential addresses
oCRandomRepl
oCRangeAddrMapperRange address mapper that maps a set of original ranges to a set of remapped ranges, where a specific range is of the same size (original and remapped), only with an offset
oCRawDiskImageSpecialization for accessing a raw disk image
oCRawObject
oCRealView
oCRealViewCtrl
oCRealViewOscThis is an implementation of a programmable oscillator on the that can be configured through the RealView/Versatile Express configuration interface
oCRealViewTemperatureSensorThis device implements the temperature sensor used in the RealView/Versatile Express platform
oCReconvergenceStackEntryA reconvergence stack entry conveys the necessary state to implement control flow divergence
oCReExec
oCRefCountedDerive from RefCounted if you want to enable reference counting of this class
oCRefCountingPtrIf you want a reference counting pointer to a mutable object, create it like this:
oCRegAddrOperand
oCRegImmImmOp
oCRegImmOp
oCRegImmRegOp
oCRegImmRegShiftOp
oCRegMiscRegImmOp
oCRegOrImmOperand
oCRegRegImmImmOp
oCRegRegImmImmOp64
oCRegRegImmOp
oCRegRegOp
oCRegRegRegImmOp
oCRegRegRegImmOp64
oCRegRegRegOp
oCRegRegRegRegOp
oCRejectException
oCReqPacketQueue
oCRequest
oCRequestDesc
oCRespPacketQueue
oCReturnAddrStackReturn address stack class, implements a simple RAS
oCRiscvLinux
oCRiscvLinuxProcessA process with emulated Riscv/Linux syscalls
oCRiscvProcess
oCRiscvSystem
oCRNDXR
oCROBROB class
oCRoot
oCRouteInfo
oCRouter
oCRoutingUnit
oCRRSchedulingPolicy
oCRubyDirectedTester
oCRubyPort
oCRubyPortProxy
oCRubyRequest
oCRubyStatsCallback
oCRubySystem
oCRubyTester
oCSatCounterPrivate counter class for the internal saturating counters
oCScheduler
oCScheduleStage
oCSchedulingPolicy
oCScoreboardImplements a simple scoreboard to track which registers are ready
oCScoreboardCheckStage
oCSequencer
oCSequencerRequest
oCSerializableBasic support for object serialization
oCSerialLinkSerialLink is a simple variation of the Bridge class, with the ability to account for the latency of packet serialization
oCSeriesRequestGenerator
oCSet
oCSETranslatingPortProxy
oCShader
oCSimObjectAbstract superclass for simulation objects
oCSimObjectResolverBase class to wrap object resolving functionality
oCSimpleCPUPolicyStruct that defines the key classes to be used by the CPU
oCSimpleDisk
oCSimpleExecContext
oCSimpleExtLink
oCSimpleFreeListFree list for a single class of registers (e.g., integer or floating point)
oCSimpleIntLink
oCSimpleMemoryThe simple memory is a basic single-ported memory controller with a configurable throughput and latency
oCSimpleNetwork
oCSimplePoolManager
oCSimpleRenameMapRegister rename map for a single class of registers (e.g., integer or floating point)
oCSimpleThreadThe SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface
oCSimpleTimingPortThe simple timing port uses a queued port to implement recvFunctional and recvTimingReq through recvAtomic
oCSimpleTrace
oCSimPoint
oCSkipFuncEvent
oCSlavePortA SlavePort is a specialisation of a port
oCSNHash
oCSnoopFilterThis snoop filter keeps track of which connected port has a particular line of data
oCSnoopRespPacketQueue
oCSolarisThis class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Solaris syscall interface
oCSouthBridge
oCSp804
oCSparc32Linux
oCSparc32Process
oCSparc64Process
oCSparcLinux
oCSparcProcess
oCSparcSolaris
oCSparcSystem
oCSrcClockDomainThe source clock domains provides the notion of a clock domain that is connected to a tunable clock source
oCSRegOperand
oCStackDistCalcThe stack distance calculator is a passive object that merely observes the addresses pass to it
oCStackDistProbe
oCStaticInstBase, ISA-independent static instruction class
oCStatTest
oCStorageElement
oCStorageMap
oCStorageSpace
oCStoreSetImplements a store set predictor for determining if memory instructions are dependent upon each other
oCStoreTrace
oCStridePrefetcher
oCStringWrap
oCStubSlavePortImplement a `stub' port which just responds to requests by printing a message
oCStubSlavePortHandler
oCSubBlock
oCSubSystemThe SubSystem simobject does nothing, it is just a container for other simobjects used by the configuration system
oCSwitch
oCSwitchAllocator
oCSymbolTable
oCSyscallDescThis class provides the wrapper interface for the system call implementations which are defined in the sim/syscall_emul files and bound to the ISAs in the architecture specific code (i.e
oCSyscallFlagTransTableThis struct is used to build target-OS-dependent tables that map the target's flags to the host's flags
oCSyscallRetryFault
oCSyscallReturnThis class represents the return value from an emulated system call, including any errno setting
oCSystem
oCSystemCounterGlobal system counter
oCT1000
oCTaggedPrefetcher
oCTapEvent
oCTapListener
oCTBETable
oCTCPIface
oCTerminal
oCTestClass
oCThermalCapacitorA ThermalCapacitor is used to model a thermal capacitance between two thermal domains
oCThermalDomainA ThermalDomain is used to group objects under that operate under the same temperature
oCThermalEntityAn abstract class that represents any thermal entity which is used in the circuital thermal equivalent model
oCThermalModelA ThermalModel is the element which ties all thermal objects together and provides the thermal solver to the system
oCThermalNodeA ThermalNode is used to connect thermal entities, such as resistors, capacitors, references and domains
oCThermalReferenceA ThermalReference is a thermal domain with fixed temperature
oCThermalResistorA ThermalResistor is used to model a thermal resistance between two thermal domains
oCThreadContextThreadContext is the external interface to all thread state for anything outside of the CPU
oCThreadStateStruct for holding general thread state that is needed across CPU models
oCThrottle
oCTickedTicked attaches gem5's event queue/scheduler to evaluate calls and provides a start/stop interface to ticking
oCTickedObjectTickedObject attaches Ticked to ClockedObject and can be used as a base class where ticked operation
oCTime
oCTimeBuffer
oCTimeBufStructStruct that defines all backwards communication
oCTimerTable
oCTimingExpr
oCTimingExprBin
oCTimingExprEvalContextObject to gather the visible context for evaluation
oCTimingExprIf
oCTimingExprLet
oCTimingExprLiteral
oCTimingExprReadIntReg
oCTimingExprRef
oCTimingExprSrcReg
oCTimingExprUn
oCTimingSimpleCPU
oCTIR
oCTLBCoalescerThe TLBCoalescer is a MemObject sitting on the front side (CPUSide) of each TLB
oCTopology
oCTournamentBPImplements a tournament branch predictor, hopefully identical to the one used in the 21264
oCTraceCPUThe trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model
oCTraceGenThe trace replay generator reads a trace file and plays back the transactions
oCTraceRecordClass for recording cache contents
oCTrafficGenThe traffic generator is a master module that generates stimuli for the memory system, based on a collection of simple generator behaviours that are either probabilistic or based on traces
oCTrie
oCTsunamiTop level class for Tsunami Chipset emulation
oCTsunamiCChipTsunami CChip CSR Emulation
oCTsunamiIOTsunami I/O device is a catch all for all the south bridge stuff we care to implement
oCTsunamiPChipA very simple implementation of the Tsunami PCI interface chips
oCTypedAtomicOpFunctor
oCTypedBufferArgTypedBufferArg is a class template; instances of this template represent typed buffers in target user space that are passed by reference to an (emulated) system call
oCUart
oCUart8250
oCUFSHostDeviceUFS command flow state machine digraph CommandFlow{ node [fontsize=10]; IDLE -> transferHandler [ label=" transfer/task/command request " fontsize=6]; transferHandler -> command [ label=" It is a command " fontsize=6]; command -> IDLE [ label=" Command done, no further action " fontsize=6]; transferHandler -> taskStart [ label=" It is a task " fontsize=6]; taskStart -> finalUTP [ label=" Task handled, now acknowledge (UFS) " fontsize=6]; transferHandler -> transferStart [ label=" It is a transfer " fontsize=6]; transferStart -> SCSIResume [ label=" Transfer, obtain the specific command " fontsize=6]; SCSIResume -> DiskDataFlowPhase [ label=" Disk data transfer (see other graphs) " fontsize=6]; SCSIResume -> DeviceDataPhase [ label=" Device info transfer (handled in SCSIResume) " fontsize=6]; DiskDataFlowPhase -> transferDone [ label=" Transfer done, acknowledge SCSI command " fontsize=6]; DeviceDataPhase -> transferDone [ label=" Transfer done, acknowledge SCSI command " fontsize=6]; transferDone -> finalUTP [ label=" Transfer handled, now acknowledge (UFS) " fontsize=6]; finalUTP -> readDone [ label=" All handled, clear data structures " fontsize=6]; readDone -> IDLE [ label=" All handled, nothing outstanding " fontsize=6]; readDone -> transferHandler [ label=" All handled, handle next outstanding " fontsize=6]; }
oCUnifiedFreeListFreeList class that simply holds the list of free integer and floating point registers
oCUnifiedRenameMapUnified register rename map for all classes of registers
oCUnimpFault
oCUnknownOp
oCUnknownOp64
oCUserDesc64
oCVecRegisterState
oCVectorRegisterFile
oCVGic
oCVIPERCoalescer
oCVirtDescriptorVirtIO descriptor (chain) wrapper
oCVirtIO9PBaseThis class implements a VirtIO transport layer for the 9p network file system
oCVirtIO9PDiodVirtIO 9p proxy that communicates with the diod 9p server using pipes
oCVirtIO9PProxyVirtIO 9p proxy base class
oCVirtIO9PSocketVirtIO 9p proxy that communicates with a 9p server over tcp sockets
oCVirtIOBlockVirtIO block device
oCVirtIOConsoleVirtIO console
oCVirtIODeviceBaseBase class for all VirtIO-based devices
oCVirtIODummyDevice
oCVirtQueueBase wrapper around a virtqueue
oCVirtualChannel
oCVncInput
oCVncKeyboardA device that expects to receive input from the vnc server should derrive (through mulitple inheritence if necessary from VncKeyboard or VncMouse and call setKeyboard() or setMouse() respectively on the vnc server
oCVncMouse
oCVncServer
oCVoltageDomainA VoltageDomain is used to group clock domains that operate under the same voltage
oCVPtr
oCvring
oCvring_avail
oCvring_desc
oCvring_used
oCvring_used_elem
oCWaitClass
oCWarnUnimplementedBase class for unimplemented instructions that cause a warning to be printed (but do not terminate simulation)
oCWavefront
oCWeightedLRUPolicy
oCWholeTranslationStateThis class captures the state of an address translation
oCWireBuffer
oCWriteMask
oCWriteQueueA write queue for all eviction packets, i.e
oCWriteQueueEntryWrite queue entry
oCX86KvmCPUX86 implementation of a KVM-based hardware virtualized CPU
oCX86Linux32
oCX86Linux64
\CX86System
Generated on Fri Jun 9 2017 13:04:44 for gem5 by doxygen 1.8.6