Classes
class	M5DebugFault

class	M5VarArgsFault

class	BasicDecodeCache

class	PCStateBase

class	SimplePCState

class	UPCState

class	DelaySlotPCState

class	DelaySlotUPCState

Typedefs
typedef M5VarArgsFault < M5DebugFault::PanicFunc >	M5PanicFault

typedef M5VarArgsFault < M5DebugFault::FatalFunc >	M5FatalFault

typedef M5VarArgsFault < M5DebugFault::WarnFunc >	M5WarnFault

typedef M5VarArgsFault < M5DebugFault::WarnOnceFunc >	M5WarnOnceFault

Functions
Addr	iprAddressPseudoInst (uint8_t func, uint8_t subfunc)
	Generate a generic IPR address that emulates a pseudo inst. More...

bool	isGenericIprAccess (const Packet *pkt)
	Check if this is an platform independent IPR access. More...

Cycles	handleGenericIprRead (ThreadContext xc, Packet pkt)
	Handle generic IPR reads. More...

Cycles	handleGenericIprWrite (ThreadContext xc, Packet pkt)
	Handle generic IPR writes. More...

Cycles	handleIprRead (ThreadContext xc, Packet pkt)
	Helper function to handle IPRs when the target architecture doesn't need its own IPR handling. More...

Cycles	handleIprWrite (ThreadContext xc, Packet pkt)
	Helper function to handle IPRs when the target architecture doesn't need its own IPR handling. More...

void	m5Syscall (ThreadContext *tc)

void	m5PageFault (ThreadContext *tc)

template<class MachInst >
std::ostream &	operator<< (std::ostream &os, const SimplePCState< MachInst > &pc)

template<class MachInst >
std::ostream &	operator<< (std::ostream &os, const UPCState< MachInst > &pc)

template<class MachInst >
std::ostream &	operator<< (std::ostream &os, const DelaySlotPCState< MachInst > &pc)

template<class MachInst >
std::ostream &	operator<< (std::ostream &os, const DelaySlotUPCState< MachInst > &pc)

Variables

const int	IPR_CLASS_SHIFT = 48
	Memory requests with the MMAPPED_IPR flag are generally mapped to registers. More...

const Addr	IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF)
	Mask to extract the offset in within a generic IPR class. More...

const Addr	IPR_CLASS_PSEUDO_INST = 0x0
	gem5 pseudo-inst emulation. More...

Typedef Documentation

typedef M5VarArgsFault<M5DebugFault::FatalFunc> GenericISA::M5FatalFault

Definition at line 122 of file debugfaults.hh.

typedef M5VarArgsFault<M5DebugFault::PanicFunc> GenericISA::M5PanicFault

Definition at line 121 of file debugfaults.hh.

typedef M5VarArgsFault<M5DebugFault::WarnFunc> GenericISA::M5WarnFault

Definition at line 123 of file debugfaults.hh.

typedef M5VarArgsFault<M5DebugFault::WarnOnceFunc> GenericISA::M5WarnOnceFault

Definition at line 124 of file debugfaults.hh.

Function Documentation

Cycles GenericISA::handleGenericIprRead	(	ThreadContext *	xc,
		Packet *	pkt
	)

Handle generic IPR reads.

Parameters

xc	Thread context of the current thread.
pkt	Packet from the CPU

Returns: Latency in CPU cycles

Definition at line 54 of file mmapped_ipr.cc.

References Packet::getAddr(), handlePseudoInst(), IPR_CLASS_PSEUDO_INST, IPR_CLASS_SHIFT, panic, and ArmISA::va.

Referenced by SparcISA::handleIprRead(), X86ISA::handleIprRead(), and handleIprRead().

Cycles GenericISA::handleGenericIprWrite	(	ThreadContext *	xc,
		Packet *	pkt
	)

Handle generic IPR writes.

Parameters

xc	Thread context of the current thread.
pkt	Packet from the CPU

Returns: Latency in CPU cycles

Definition at line 71 of file mmapped_ipr.cc.

References Packet::getAddr(), handlePseudoInst(), IPR_CLASS_PSEUDO_INST, IPR_CLASS_SHIFT, panic, and ArmISA::va.

Referenced by SparcISA::handleIprWrite(), X86ISA::handleIprWrite(), and handleIprWrite().

Cycles GenericISA::handleIprRead	(	ThreadContext *	xc,
		Packet *	pkt
	)

inline

Helper function to handle IPRs when the target architecture doesn't need its own IPR handling.

This function calls handleGenericIprRead if the accessing a generic IPR and panics otherwise.

Parameters

xc	Thread context of the current thread.
pkt	Packet from the CPU

Returns: Latency in CPU cycles

Definition at line 139 of file mmapped_ipr.hh.

References handleGenericIprRead(), isGenericIprAccess(), and panic.

Referenced by BaseKvmCPU::doMMIOAccess(), TimingSimpleCPU::handleReadPacket(), LSQUnit< Impl >::read(), AtomicSimpleCPU::readMem(), and Minor::LSQ::tryToSend().

Cycles GenericISA::handleIprWrite	(	ThreadContext *	xc,
		Packet *	pkt
	)

inline

Helper function to handle IPRs when the target architecture doesn't need its own IPR handling.

This function calls handleGenericIprWrite if the accessing a generic IPR and panics otherwise.

Parameters

xc	Thread context of the current thread.
pkt	Packet from the CPU

Returns: Latency in CPU cycles

Definition at line 160 of file mmapped_ipr.hh.

References handleGenericIprWrite(), isGenericIprAccess(), and panic.

Referenced by BaseKvmCPU::doMMIOAccess(), TimingSimpleCPU::handleWritePacket(), Minor::LSQ::tryToSend(), LSQUnit< Impl >::writebackStores(), and AtomicSimpleCPU::writeMem().

Addr GenericISA::iprAddressPseudoInst	(	uint8_t	func,
		uint8_t	subfunc
	)

inline

Generate a generic IPR address that emulates a pseudo inst.

See Also: PseudoInst::pseudoInst()

Parameters

func	Function ID to call.
subfunc	Sub-function, usually 0.

Returns: Address in the IPR space corresponding to the call.

Definition at line 84 of file mmapped_ipr.hh.

References IPR_CLASS_PSEUDO_INST, and IPR_CLASS_SHIFT.

Referenced by X86ISA::TLB::finalizePhysical(), and ArmISA::TLB::finalizePhysical().

bool GenericISA::isGenericIprAccess ( const Packet * pkt )

inline

Check if this is an platform independent IPR access.

Accesses to internal platform independent gem5 registers are handled by handleGenericIprRead() and handleGenericIprWrite(). This method determines if a packet should be routed to those functions instead of the platform specific code.

See Also: handleGenericIprRead; handleGenericIprWrite

Definition at line 103 of file mmapped_ipr.hh.

References Request::GENERIC_IPR, Request::getFlags(), Request::MMAPPED_IPR, and Packet::req.

Referenced by SparcISA::handleIprRead(), X86ISA::handleIprRead(), handleIprRead(), SparcISA::handleIprWrite(), X86ISA::handleIprWrite(), and handleIprWrite().

void GenericISA::m5PageFault ( ThreadContext * tc )

Definition at line 46 of file pseudo_inst.cc.

References DPRINTF, Process::fixupStackFault(), ThreadContext::getMemProxy(), ThreadContext::getProcessPtr(), MipsISA::is, X86ISA::ISTVirtAddr, X86ISA::MISCREG_CR2, X86ISA::p, X86ISA::PageBytes, panic, SETranslatingPortProxy::readBlob(), ThreadContext::readMiscReg(), and X86ISA::size().

Referenced by PseudoInst::pseudoInst().

void GenericISA::m5Syscall ( ThreadContext * tc )

Definition at line 40 of file pseudo_inst.cc.

References DPRINTF, X86ISA::MISCREG_RFLAGS, panic, ThreadContext::readIntReg(), ThreadContext::readMiscReg(), ThreadContext::setMiscReg(), and ThreadContext::syscall().

Referenced by PseudoInst::pseudoInst().

template<class MachInst >

std::ostream& GenericISA::operator<<	(	std::ostream &	os,
		const SimplePCState< MachInst > &	pc
	)

Definition at line 177 of file types.hh.

References ccprintf(), X86ISA::os, and pc.

template<class MachInst >

std::ostream& GenericISA::operator<<	(	std::ostream &	os,
		const UPCState< MachInst > &	pc
	)

Definition at line 275 of file types.hh.

References ccprintf(), X86ISA::os, and pc.

template<class MachInst >

std::ostream& GenericISA::operator<<	(	std::ostream &	os,
		const DelaySlotPCState< MachInst > &	pc
	)

Definition at line 354 of file types.hh.

References ccprintf(), X86ISA::os, and pc.

template<class MachInst >

std::ostream& GenericISA::operator<<	(	std::ostream &	os,
		const DelaySlotUPCState< MachInst > &	pc
	)

Definition at line 453 of file types.hh.

References ccprintf(), X86ISA::os, and pc.

Variable Documentation

const Addr GenericISA::IPR_CLASS_PSEUDO_INST = 0x0

gem5 pseudo-inst emulation.

Read and writes to this class execute gem5 pseudo-instructions. A write discards the return value of the instruction, while a read returns it.

See Also: pseudoInst()

Definition at line 70 of file mmapped_ipr.hh.

Referenced by handleGenericIprRead(), handleGenericIprWrite(), and iprAddressPseudoInst().

const int GenericISA::IPR_CLASS_SHIFT = 48

Memory requests with the MMAPPED_IPR flag are generally mapped to registers.

There is a class of these registers that are internal to gem5, for example gem5 pseudo-ops in virtualized mode. Such IPRs always have the flag GENERIC_IPR set and are handled by this code.Shift amount when extracting the class of a generic IPR

Definition at line 57 of file mmapped_ipr.hh.

Referenced by handleGenericIprRead(), handleGenericIprWrite(), and iprAddressPseudoInst().

const Addr GenericISA::IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF)

Mask to extract the offset in within a generic IPR class.

Definition at line 60 of file mmapped_ipr.hh.

Referenced by handlePseudoInst().

Classes

Typedefs

Functions

Variables

Typedef Documentation

Function Documentation

Variable Documentation