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miscregs.hh
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1 /*
2  * Copyright (c) 2010-2017 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2009 The Regents of The University of Michigan
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  *
40  * Authors: Gabe Black
41  * Giacomo Gabrielli
42  */
43 #ifndef __ARCH_ARM_MISCREGS_HH__
44 #define __ARCH_ARM_MISCREGS_HH__
45 
46 #include <bitset>
47 #include <tuple>
48 
49 #include "base/bitunion.hh"
50 #include "base/compiler.hh"
51 
52 class ThreadContext;
53 
54 
55 namespace ArmISA
56 {
57  enum MiscRegIndex {
58  MISCREG_CPSR = 0, // 0
73 
74  // Helper registers
90 
91  // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
137  MISCREG_TEECR, // 75, not in ARM DDI 0487A.b+
139  MISCREG_TEEHBR, // 77, not in ARM DDI 0487A.b+
142 
143  // AArch32 CP15 registers (system control)
145  MISCREG_CTR, // 81
166  MISCREG_AIDR, // 102
179  MISCREG_SCR, // 115
180  MISCREG_SDER, // 116
184  MISCREG_HCR, // 120
185  MISCREG_HDCR, // 121
187  MISCREG_HSTR, // 123
188  MISCREG_HACR, // 124
198  MISCREG_HTCR, // 134
199  MISCREG_VTCR, // 135
200  MISCREG_DACR, // 136
203  MISCREG_DFSR, // 139
206  MISCREG_IFSR, // 142
217  MISCREG_HSR, // 153
218  MISCREG_DFAR, // 154
221  MISCREG_IFAR, // 157
229  MISCREG_PAR, // 165
286  MISCREG_PMCR, // 222
304  MISCREG_PRRR, // 240
310  MISCREG_NMRR, // 246
326  MISCREG_VBAR, // 262
330  MISCREG_RMR, // 266
331  MISCREG_ISR, // 267
371  MISCREG_CBAR, // 307
384 
385  // AArch64 registers (Op0=2)
424  MISCREG_TEECR32_EL1, // 358, not in ARM DDI 0487A.b+
425  MISCREG_TEEHBR32_EL1, // 359, not in ARM DDI 0487A.b+
426 
427  // AArch64 registers (Op0=1,3)
497  MISCREG_NZCV, // 429
498  MISCREG_DAIF, // 430
499  MISCREG_FPCR, // 431
500  MISCREG_FPSR, // 432
668 
669  // Dummy registers
670  MISCREG_NOP, // 600
671  MISCREG_RAZ, // 601
676 
678  };
679 
680  enum MiscRegInfo {
682  MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
683  // arch generic counter)
684  MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
685  // tells whether the instruction should raise a
686  // warning or fail
687  MISCREG_MUTEX, // True if the register corresponds to a pair of
688  // mutually exclusive registers
689  MISCREG_BANKED, // True if the register is banked between the two
690  // security states, and this is the parent node of the
691  // two banked registers
692  MISCREG_BANKED_CHILD, // The entry is one of the child registers that
693  // forms a banked set of regs (along with the
694  // other child regs)
695 
696  // Access permissions
697  // User mode
702  // Privileged modes other than hypervisor or monitor
707  // Hypervisor mode
710  // Monitor mode, SCR.NS == 0
713  // Monitor mode, SCR.NS == 1
716 
718  };
719 
720  extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
721 
722  // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
723  MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
724  unsigned crm, unsigned opc2);
725  MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
726  unsigned crn, unsigned crm,
727  unsigned op2);
728  // Whether a particular AArch64 system register is -always- read only.
729  bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
730 
731  // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
732  MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
733  unsigned crm, unsigned opc2);
734 
735  // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
736  MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
737 
738 
739  const char * const miscRegName[] = {
740  "cpsr",
741  "spsr",
742  "spsr_fiq",
743  "spsr_irq",
744  "spsr_svc",
745  "spsr_mon",
746  "spsr_abt",
747  "spsr_hyp",
748  "spsr_und",
749  "elr_hyp",
750  "fpsid",
751  "fpscr",
752  "mvfr1",
753  "mvfr0",
754  "fpexc",
755 
756  // Helper registers
757  "cpsr_mode",
758  "cpsr_q",
759  "fpscr_exc",
760  "fpscr_qc",
761  "lockaddr",
762  "lockflag",
763  "prrr_mair0",
764  "prrr_mair0_ns",
765  "prrr_mair0_s",
766  "nmrr_mair1",
767  "nmrr_mair1_ns",
768  "nmrr_mair1_s",
769  "pmxevtyper_pmccfiltr",
770  "sctlr_rst",
771  "sev_mailbox",
772 
773  // AArch32 CP14 registers
774  "dbgdidr",
775  "dbgdscrint",
776  "dbgdccint",
777  "dbgdtrtxint",
778  "dbgdtrrxint",
779  "dbgwfar",
780  "dbgvcr",
781  "dbgdtrrxext",
782  "dbgdscrext",
783  "dbgdtrtxext",
784  "dbgoseccr",
785  "dbgbvr0",
786  "dbgbvr1",
787  "dbgbvr2",
788  "dbgbvr3",
789  "dbgbvr4",
790  "dbgbvr5",
791  "dbgbcr0",
792  "dbgbcr1",
793  "dbgbcr2",
794  "dbgbcr3",
795  "dbgbcr4",
796  "dbgbcr5",
797  "dbgwvr0",
798  "dbgwvr1",
799  "dbgwvr2",
800  "dbgwvr3",
801  "dbgwcr0",
802  "dbgwcr1",
803  "dbgwcr2",
804  "dbgwcr3",
805  "dbgdrar",
806  "dbgbxvr4",
807  "dbgbxvr5",
808  "dbgoslar",
809  "dbgoslsr",
810  "dbgosdlr",
811  "dbgprcr",
812  "dbgdsar",
813  "dbgclaimset",
814  "dbgclaimclr",
815  "dbgauthstatus",
816  "dbgdevid2",
817  "dbgdevid1",
818  "dbgdevid0",
819  "teecr",
820  "jidr",
821  "teehbr",
822  "joscr",
823  "jmcr",
824 
825  // AArch32 CP15 registers
826  "midr",
827  "ctr",
828  "tcmtr",
829  "tlbtr",
830  "mpidr",
831  "revidr",
832  "id_pfr0",
833  "id_pfr1",
834  "id_dfr0",
835  "id_afr0",
836  "id_mmfr0",
837  "id_mmfr1",
838  "id_mmfr2",
839  "id_mmfr3",
840  "id_isar0",
841  "id_isar1",
842  "id_isar2",
843  "id_isar3",
844  "id_isar4",
845  "id_isar5",
846  "ccsidr",
847  "clidr",
848  "aidr",
849  "csselr",
850  "csselr_ns",
851  "csselr_s",
852  "vpidr",
853  "vmpidr",
854  "sctlr",
855  "sctlr_ns",
856  "sctlr_s",
857  "actlr",
858  "actlr_ns",
859  "actlr_s",
860  "cpacr",
861  "scr",
862  "sder",
863  "nsacr",
864  "hsctlr",
865  "hactlr",
866  "hcr",
867  "hdcr",
868  "hcptr",
869  "hstr",
870  "hacr",
871  "ttbr0",
872  "ttbr0_ns",
873  "ttbr0_s",
874  "ttbr1",
875  "ttbr1_ns",
876  "ttbr1_s",
877  "ttbcr",
878  "ttbcr_ns",
879  "ttbcr_s",
880  "htcr",
881  "vtcr",
882  "dacr",
883  "dacr_ns",
884  "dacr_s",
885  "dfsr",
886  "dfsr_ns",
887  "dfsr_s",
888  "ifsr",
889  "ifsr_ns",
890  "ifsr_s",
891  "adfsr",
892  "adfsr_ns",
893  "adfsr_s",
894  "aifsr",
895  "aifsr_ns",
896  "aifsr_s",
897  "hadfsr",
898  "haifsr",
899  "hsr",
900  "dfar",
901  "dfar_ns",
902  "dfar_s",
903  "ifar",
904  "ifar_ns",
905  "ifar_s",
906  "hdfar",
907  "hifar",
908  "hpfar",
909  "icialluis",
910  "bpiallis",
911  "par",
912  "par_ns",
913  "par_s",
914  "iciallu",
915  "icimvau",
916  "cp15isb",
917  "bpiall",
918  "bpimva",
919  "dcimvac",
920  "dcisw",
921  "ats1cpr",
922  "ats1cpw",
923  "ats1cur",
924  "ats1cuw",
925  "ats12nsopr",
926  "ats12nsopw",
927  "ats12nsour",
928  "ats12nsouw",
929  "dccmvac",
930  "dccsw",
931  "cp15dsb",
932  "cp15dmb",
933  "dccmvau",
934  "dccimvac",
935  "dccisw",
936  "ats1hr",
937  "ats1hw",
938  "tlbiallis",
939  "tlbimvais",
940  "tlbiasidis",
941  "tlbimvaais",
942  "tlbimvalis",
943  "tlbimvaalis",
944  "itlbiall",
945  "itlbimva",
946  "itlbiasid",
947  "dtlbiall",
948  "dtlbimva",
949  "dtlbiasid",
950  "tlbiall",
951  "tlbimva",
952  "tlbiasid",
953  "tlbimvaa",
954  "tlbimval",
955  "tlbimvaal",
956  "tlbiipas2is",
957  "tlbiipas2lis",
958  "tlbiallhis",
959  "tlbimvahis",
960  "tlbiallnsnhis",
961  "tlbimvalhis",
962  "tlbiipas2",
963  "tlbiipas2l",
964  "tlbiallh",
965  "tlbimvah",
966  "tlbiallnsnh",
967  "tlbimvalh",
968  "pmcr",
969  "pmcntenset",
970  "pmcntenclr",
971  "pmovsr",
972  "pmswinc",
973  "pmselr",
974  "pmceid0",
975  "pmceid1",
976  "pmccntr",
977  "pmxevtyper",
978  "pmccfiltr",
979  "pmxevcntr",
980  "pmuserenr",
981  "pmintenset",
982  "pmintenclr",
983  "pmovsset",
984  "l2ctlr",
985  "l2ectlr",
986  "prrr",
987  "prrr_ns",
988  "prrr_s",
989  "mair0",
990  "mair0_ns",
991  "mair0_s",
992  "nmrr",
993  "nmrr_ns",
994  "nmrr_s",
995  "mair1",
996  "mair1_ns",
997  "mair1_s",
998  "amair0",
999  "amair0_ns",
1000  "amair0_s",
1001  "amair1",
1002  "amair1_ns",
1003  "amair1_s",
1004  "hmair0",
1005  "hmair1",
1006  "hamair0",
1007  "hamair1",
1008  "vbar",
1009  "vbar_ns",
1010  "vbar_s",
1011  "mvbar",
1012  "rmr",
1013  "isr",
1014  "hvbar",
1015  "fcseidr",
1016  "contextidr",
1017  "contextidr_ns",
1018  "contextidr_s",
1019  "tpidrurw",
1020  "tpidrurw_ns",
1021  "tpidrurw_s",
1022  "tpidruro",
1023  "tpidruro_ns",
1024  "tpidruro_s",
1025  "tpidrprw",
1026  "tpidrprw_ns",
1027  "tpidrprw_s",
1028  "htpidr",
1029  "cntfrq",
1030  "cntkctl",
1031  "cntp_tval",
1032  "cntp_tval_ns",
1033  "cntp_tval_s",
1034  "cntp_ctl",
1035  "cntp_ctl_ns",
1036  "cntp_ctl_s",
1037  "cntv_tval",
1038  "cntv_ctl",
1039  "cnthctl",
1040  "cnthp_tval",
1041  "cnthp_ctl",
1042  "il1data0",
1043  "il1data1",
1044  "il1data2",
1045  "il1data3",
1046  "dl1data0",
1047  "dl1data1",
1048  "dl1data2",
1049  "dl1data3",
1050  "dl1data4",
1051  "ramindex",
1052  "l2actlr",
1053  "cbar",
1054  "httbr",
1055  "vttbr",
1056  "cntpct",
1057  "cntvct",
1058  "cntp_cval",
1059  "cntp_cval_ns",
1060  "cntp_cval_s",
1061  "cntv_cval",
1062  "cntvoff",
1063  "cnthp_cval",
1064  "cpumerrsr",
1065  "l2merrsr",
1066 
1067  // AArch64 registers (Op0=2)
1068  "mdccint_el1",
1069  "osdtrrx_el1",
1070  "mdscr_el1",
1071  "osdtrtx_el1",
1072  "oseccr_el1",
1073  "dbgbvr0_el1",
1074  "dbgbvr1_el1",
1075  "dbgbvr2_el1",
1076  "dbgbvr3_el1",
1077  "dbgbvr4_el1",
1078  "dbgbvr5_el1",
1079  "dbgbcr0_el1",
1080  "dbgbcr1_el1",
1081  "dbgbcr2_el1",
1082  "dbgbcr3_el1",
1083  "dbgbcr4_el1",
1084  "dbgbcr5_el1",
1085  "dbgwvr0_el1",
1086  "dbgwvr1_el1",
1087  "dbgwvr2_el1",
1088  "dbgwvr3_el1",
1089  "dbgwcr0_el1",
1090  "dbgwcr1_el1",
1091  "dbgwcr2_el1",
1092  "dbgwcr3_el1",
1093  "mdccsr_el0",
1094  "mddtr_el0",
1095  "mddtrtx_el0",
1096  "mddtrrx_el0",
1097  "dbgvcr32_el2",
1098  "mdrar_el1",
1099  "oslar_el1",
1100  "oslsr_el1",
1101  "osdlr_el1",
1102  "dbgprcr_el1",
1103  "dbgclaimset_el1",
1104  "dbgclaimclr_el1",
1105  "dbgauthstatus_el1",
1106  "teecr32_el1",
1107  "teehbr32_el1",
1108 
1109  // AArch64 registers (Op0=1,3)
1110  "midr_el1",
1111  "mpidr_el1",
1112  "revidr_el1",
1113  "id_pfr0_el1",
1114  "id_pfr1_el1",
1115  "id_dfr0_el1",
1116  "id_afr0_el1",
1117  "id_mmfr0_el1",
1118  "id_mmfr1_el1",
1119  "id_mmfr2_el1",
1120  "id_mmfr3_el1",
1121  "id_isar0_el1",
1122  "id_isar1_el1",
1123  "id_isar2_el1",
1124  "id_isar3_el1",
1125  "id_isar4_el1",
1126  "id_isar5_el1",
1127  "mvfr0_el1",
1128  "mvfr1_el1",
1129  "mvfr2_el1",
1130  "id_aa64pfr0_el1",
1131  "id_aa64pfr1_el1",
1132  "id_aa64dfr0_el1",
1133  "id_aa64dfr1_el1",
1134  "id_aa64afr0_el1",
1135  "id_aa64afr1_el1",
1136  "id_aa64isar0_el1",
1137  "id_aa64isar1_el1",
1138  "id_aa64mmfr0_el1",
1139  "id_aa64mmfr1_el1",
1140  "ccsidr_el1",
1141  "clidr_el1",
1142  "aidr_el1",
1143  "csselr_el1",
1144  "ctr_el0",
1145  "dczid_el0",
1146  "vpidr_el2",
1147  "vmpidr_el2",
1148  "sctlr_el1",
1149  "actlr_el1",
1150  "cpacr_el1",
1151  "sctlr_el2",
1152  "actlr_el2",
1153  "hcr_el2",
1154  "mdcr_el2",
1155  "cptr_el2",
1156  "hstr_el2",
1157  "hacr_el2",
1158  "sctlr_el3",
1159  "actlr_el3",
1160  "scr_el3",
1161  "sder32_el3",
1162  "cptr_el3",
1163  "mdcr_el3",
1164  "ttbr0_el1",
1165  "ttbr1_el1",
1166  "tcr_el1",
1167  "ttbr0_el2",
1168  "tcr_el2",
1169  "vttbr_el2",
1170  "vtcr_el2",
1171  "ttbr0_el3",
1172  "tcr_el3",
1173  "dacr32_el2",
1174  "spsr_el1",
1175  "elr_el1",
1176  "sp_el0",
1177  "spsel",
1178  "currentel",
1179  "nzcv",
1180  "daif",
1181  "fpcr",
1182  "fpsr",
1183  "dspsr_el0",
1184  "dlr_el0",
1185  "spsr_el2",
1186  "elr_el2",
1187  "sp_el1",
1188  "spsr_irq_aa64",
1189  "spsr_abt_aa64",
1190  "spsr_und_aa64",
1191  "spsr_fiq_aa64",
1192  "spsr_el3",
1193  "elr_el3",
1194  "sp_el2",
1195  "afsr0_el1",
1196  "afsr1_el1",
1197  "esr_el1",
1198  "ifsr32_el2",
1199  "afsr0_el2",
1200  "afsr1_el2",
1201  "esr_el2",
1202  "fpexc32_el2",
1203  "afsr0_el3",
1204  "afsr1_el3",
1205  "esr_el3",
1206  "far_el1",
1207  "far_el2",
1208  "hpfar_el2",
1209  "far_el3",
1210  "ic_ialluis",
1211  "par_el1",
1212  "ic_iallu",
1213  "dc_ivac_xt",
1214  "dc_isw_xt",
1215  "at_s1e1r_xt",
1216  "at_s1e1w_xt",
1217  "at_s1e0r_xt",
1218  "at_s1e0w_xt",
1219  "dc_csw_xt",
1220  "dc_cisw_xt",
1221  "dc_zva_xt",
1222  "ic_ivau_xt",
1223  "dc_cvac_xt",
1224  "dc_cvau_xt",
1225  "dc_civac_xt",
1226  "at_s1e2r_xt",
1227  "at_s1e2w_xt",
1228  "at_s12e1r_xt",
1229  "at_s12e1w_xt",
1230  "at_s12e0r_xt",
1231  "at_s12e0w_xt",
1232  "at_s1e3r_xt",
1233  "at_s1e3w_xt",
1234  "tlbi_vmalle1is",
1235  "tlbi_vae1is_xt",
1236  "tlbi_aside1is_xt",
1237  "tlbi_vaae1is_xt",
1238  "tlbi_vale1is_xt",
1239  "tlbi_vaale1is_xt",
1240  "tlbi_vmalle1",
1241  "tlbi_vae1_xt",
1242  "tlbi_aside1_xt",
1243  "tlbi_vaae1_xt",
1244  "tlbi_vale1_xt",
1245  "tlbi_vaale1_xt",
1246  "tlbi_ipas2e1is_xt",
1247  "tlbi_ipas2le1is_xt",
1248  "tlbi_alle2is",
1249  "tlbi_vae2is_xt",
1250  "tlbi_alle1is",
1251  "tlbi_vale2is_xt",
1252  "tlbi_vmalls12e1is",
1253  "tlbi_ipas2e1_xt",
1254  "tlbi_ipas2le1_xt",
1255  "tlbi_alle2",
1256  "tlbi_vae2_xt",
1257  "tlbi_alle1",
1258  "tlbi_vale2_xt",
1259  "tlbi_vmalls12e1",
1260  "tlbi_alle3is",
1261  "tlbi_vae3is_xt",
1262  "tlbi_vale3is_xt",
1263  "tlbi_alle3",
1264  "tlbi_vae3_xt",
1265  "tlbi_vale3_xt",
1266  "pmintenset_el1",
1267  "pmintenclr_el1",
1268  "pmcr_el0",
1269  "pmcntenset_el0",
1270  "pmcntenclr_el0",
1271  "pmovsclr_el0",
1272  "pmswinc_el0",
1273  "pmselr_el0",
1274  "pmceid0_el0",
1275  "pmceid1_el0",
1276  "pmccntr_el0",
1277  "pmxevtyper_el0",
1278  "pmccfiltr_el0",
1279  "pmxevcntr_el0",
1280  "pmuserenr_el0",
1281  "pmovsset_el0",
1282  "mair_el1",
1283  "amair_el1",
1284  "mair_el2",
1285  "amair_el2",
1286  "mair_el3",
1287  "amair_el3",
1288  "l2ctlr_el1",
1289  "l2ectlr_el1",
1290  "vbar_el1",
1291  "rvbar_el1",
1292  "isr_el1",
1293  "vbar_el2",
1294  "rvbar_el2",
1295  "vbar_el3",
1296  "rvbar_el3",
1297  "rmr_el3",
1298  "contextidr_el1",
1299  "tpidr_el1",
1300  "tpidr_el0",
1301  "tpidrro_el0",
1302  "tpidr_el2",
1303  "tpidr_el3",
1304  "cntkctl_el1",
1305  "cntfrq_el0",
1306  "cntpct_el0",
1307  "cntvct_el0",
1308  "cntp_tval_el0",
1309  "cntp_ctl_el0",
1310  "cntp_cval_el0",
1311  "cntv_tval_el0",
1312  "cntv_ctl_el0",
1313  "cntv_cval_el0",
1314  "pmevcntr0_el0",
1315  "pmevcntr1_el0",
1316  "pmevcntr2_el0",
1317  "pmevcntr3_el0",
1318  "pmevcntr4_el0",
1319  "pmevcntr5_el0",
1320  "pmevtyper0_el0",
1321  "pmevtyper1_el0",
1322  "pmevtyper2_el0",
1323  "pmevtyper3_el0",
1324  "pmevtyper4_el0",
1325  "pmevtyper5_el0",
1326  "cntvoff_el2",
1327  "cnthctl_el2",
1328  "cnthp_tval_el2",
1329  "cnthp_ctl_el2",
1330  "cnthp_cval_el2",
1331  "cntps_tval_el1",
1332  "cntps_ctl_el1",
1333  "cntps_cval_el1",
1334  "il1data0_el1",
1335  "il1data1_el1",
1336  "il1data2_el1",
1337  "il1data3_el1",
1338  "dl1data0_el1",
1339  "dl1data1_el1",
1340  "dl1data2_el1",
1341  "dl1data3_el1",
1342  "dl1data4_el1",
1343  "l2actlr_el1",
1344  "cpuactlr_el1",
1345  "cpuectlr_el1",
1346  "cpumerrsr_el1",
1347  "l2merrsr_el1",
1348  "cbar_el1",
1349  "contextidr_el2",
1350 
1351  // Dummy registers
1352  "nop",
1353  "raz",
1354  "cp14_unimpl",
1355  "cp15_unimpl",
1356  "a64_unimpl",
1357  "unknown"
1358  };
1359 
1360  static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1361  "The miscRegName array and NUM_MISCREGS are inconsistent.");
1362 
1363  BitUnion32(CPSR)
1364  Bitfield<31, 30> nz;
1365  Bitfield<29> c;
1366  Bitfield<28> v;
1367  Bitfield<27> q;
1368  Bitfield<26, 25> it1;
1369  Bitfield<24> j;
1370  Bitfield<23, 22> res0_23_22;
1371  Bitfield<21> ss; // AArch64
1372  Bitfield<20> il; // AArch64
1373  Bitfield<19, 16> ge;
1374  Bitfield<15, 10> it2;
1375  Bitfield<9> d; // AArch64
1376  Bitfield<9> e;
1377  Bitfield<8> a;
1378  Bitfield<7> i;
1379  Bitfield<6> f;
1380  Bitfield<8, 6> aif;
1381  Bitfield<9, 6> daif; // AArch64
1382  Bitfield<5> t;
1383  Bitfield<4> width; // AArch64
1384  Bitfield<3, 2> el; // AArch64
1385  Bitfield<4, 0> mode;
1386  Bitfield<0> sp; // AArch64
1387  EndBitUnion(CPSR)
1388 
1389  // This mask selects bits of the CPSR that actually go in the CondCodes
1390  // integer register to allow renaming.
1391  static const uint32_t CondCodesMask = 0xF00F0000;
1392  static const uint32_t CpsrMaskQ = 0x08000000;
1393 
1394  BitUnion32(HDCR)
1395  Bitfield<11> tdra;
1396  Bitfield<10> tdosa;
1397  Bitfield<9> tda;
1398  Bitfield<8> tde;
1399  Bitfield<7> hpme;
1400  Bitfield<6> tpm;
1401  Bitfield<5> tpmcr;
1402  Bitfield<4, 0> hpmn;
1403  EndBitUnion(HDCR)
1404 
1405  BitUnion32(HCPTR)
1406  Bitfield<31> tcpac;
1407  Bitfield<20> tta;
1408  Bitfield<15> tase;
1409  Bitfield<13> tcp13;
1410  Bitfield<12> tcp12;
1411  Bitfield<11> tcp11;
1412  Bitfield<10> tcp10;
1413  Bitfield<10> tfp; // AArch64
1414  Bitfield<9> tcp9;
1415  Bitfield<8> tcp8;
1416  Bitfield<7> tcp7;
1417  Bitfield<6> tcp6;
1418  Bitfield<5> tcp5;
1419  Bitfield<4> tcp4;
1420  Bitfield<3> tcp3;
1421  Bitfield<2> tcp2;
1422  Bitfield<1> tcp1;
1423  Bitfield<0> tcp0;
1424  EndBitUnion(HCPTR)
1425 
1426  BitUnion32(HSTR)
1427  Bitfield<17> tjdbx;
1428  Bitfield<16> ttee;
1429  Bitfield<15> t15;
1430  Bitfield<13> t13;
1431  Bitfield<12> t12;
1432  Bitfield<11> t11;
1433  Bitfield<10> t10;
1434  Bitfield<9> t9;
1435  Bitfield<8> t8;
1436  Bitfield<7> t7;
1437  Bitfield<6> t6;
1438  Bitfield<5> t5;
1439  Bitfield<4> t4;
1440  Bitfield<3> t3;
1441  Bitfield<2> t2;
1442  Bitfield<1> t1;
1443  Bitfield<0> t0;
1444  EndBitUnion(HSTR)
1445 
1446  BitUnion64(HCR)
1447  Bitfield<33> id; // AArch64
1448  Bitfield<32> cd; // AArch64
1449  Bitfield<31> rw; // AArch64
1450  Bitfield<30> trvm; // AArch64
1451  Bitfield<29> hcd; // AArch64
1452  Bitfield<28> tdz; // AArch64
1453 
1454  Bitfield<27> tge;
1455  Bitfield<26> tvm;
1456  Bitfield<25> ttlb;
1457  Bitfield<24> tpu;
1458  Bitfield<23> tpc;
1459  Bitfield<22> tsw;
1460  Bitfield<21> tac;
1461  Bitfield<21> tacr; // AArch64
1462  Bitfield<20> tidcp;
1463  Bitfield<19> tsc;
1464  Bitfield<18> tid3;
1465  Bitfield<17> tid2;
1466  Bitfield<16> tid1;
1467  Bitfield<15> tid0;
1468  Bitfield<14> twe;
1469  Bitfield<13> twi;
1470  Bitfield<12> dc;
1471  Bitfield<11, 10> bsu;
1472  Bitfield<9> fb;
1473  Bitfield<8> va;
1474  Bitfield<8> vse; // AArch64
1475  Bitfield<7> vi;
1476  Bitfield<6> vf;
1477  Bitfield<5> amo;
1478  Bitfield<4> imo;
1479  Bitfield<3> fmo;
1480  Bitfield<2> ptw;
1481  Bitfield<1> swio;
1482  Bitfield<0> vm;
1483  EndBitUnion(HCR)
1484 
1485  BitUnion32(NSACR)
1486  Bitfield<20> nstrcdis;
1487  Bitfield<19> rfr;
1488  Bitfield<15> nsasedis;
1489  Bitfield<14> nsd32dis;
1490  Bitfield<13> cp13;
1491  Bitfield<12> cp12;
1492  Bitfield<11> cp11;
1493  Bitfield<10> cp10;
1494  Bitfield<9> cp9;
1495  Bitfield<8> cp8;
1496  Bitfield<7> cp7;
1497  Bitfield<6> cp6;
1498  Bitfield<5> cp5;
1499  Bitfield<4> cp4;
1500  Bitfield<3> cp3;
1501  Bitfield<2> cp2;
1502  Bitfield<1> cp1;
1503  Bitfield<0> cp0;
1504  EndBitUnion(NSACR)
1505 
1506  BitUnion32(SCR)
1507  Bitfield<13> twe;
1508  Bitfield<12> twi;
1509  Bitfield<11> st; // AArch64
1510  Bitfield<10> rw; // AArch64
1511  Bitfield<9> sif;
1512  Bitfield<8> hce;
1513  Bitfield<7> scd;
1514  Bitfield<7> smd; // AArch64
1515  Bitfield<6> nEt;
1516  Bitfield<5> aw;
1517  Bitfield<4> fw;
1518  Bitfield<3> ea;
1519  Bitfield<2> fiq;
1520  Bitfield<1> irq;
1521  Bitfield<0> ns;
1522  EndBitUnion(SCR)
1523 
1524  BitUnion32(SCTLR)
1525  Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
1526  Bitfield<29> afe; // Access flag enable (AArch32 only)
1527  Bitfield<28> tre; // TEX remap enable (AArch32 only)
1528  Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
1529  Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
1530  // DC CVAC and IC IVAU instructions
1531  // (AArch64 SCTLR_EL1 only)
1532  Bitfield<25> ee; // Exception Endianness
1533  Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
1534  Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
1535  // (AArch64 SCTLR_EL1 only)
1536  Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
1537  Bitfield<22> u; // Alignment (dropped in ARMv7)
1538  Bitfield<21> fi; // Fast interrupts configuration enable
1539  // (ARMv7 only)
1540  Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
1541  // (AArch32 only)
1542  Bitfield<19> dz; // Divide by Zero fault enable
1543  // (dropped in ARMv7)
1544  Bitfield<19> wxn; // Write permission implies XN
1545  Bitfield<18> ntwe; // Not trap WFE
1546  // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1547  Bitfield<18> rao2; // Read as one
1548  Bitfield<16> ntwi; // Not trap WFI
1549  // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1550  Bitfield<16> rao3; // Read as one
1551  Bitfield<15> uct; // Enable EL0 access to CTR_EL0
1552  // (AArch64 SCTLR_EL1 only)
1553  Bitfield<14> rr; // Round Robin select (ARMv7 only)
1554  Bitfield<14> dze; // Enable EL0 access to DC ZVA
1555  // (AArch64 SCTLR_EL1 only)
1556  Bitfield<13> v; // Vectors bit (AArch32 only)
1557  Bitfield<12> i; // Instruction cache enable
1558  Bitfield<11> z; // Branch prediction enable (ARMv7 only)
1559  Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only)
1560  Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7)
1561  Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only)
1562  Bitfield<8> sed; // SETEND disable
1563  // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1564  Bitfield<7> b; // Endianness support (dropped in ARMv7)
1565  Bitfield<7> itd; // IT disable
1566  // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1567  Bitfield<6, 3> rao4; // Read as one
1568  Bitfield<6> thee; // ThumbEE enable
1569  // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1570  Bitfield<5> cp15ben; // CP15 barrier enable
1571  // (AArch32 and AArch64 SCTLR_EL1 only)
1572  Bitfield<4> sa0; // Stack Alignment Check Enable for EL0
1573  // (AArch64 SCTLR_EL1 only)
1574  Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only)
1575  Bitfield<2> c; // Cache enable
1576  Bitfield<1> a; // Alignment check enable
1577  Bitfield<0> m; // MMU enable
1578  EndBitUnion(SCTLR)
1579 
1580  BitUnion32(CPACR)
1581  Bitfield<1, 0> cp0;
1582  Bitfield<3, 2> cp1;
1583  Bitfield<5, 4> cp2;
1584  Bitfield<7, 6> cp3;
1585  Bitfield<9, 8> cp4;
1586  Bitfield<11, 10> cp5;
1587  Bitfield<13, 12> cp6;
1588  Bitfield<15, 14> cp7;
1589  Bitfield<17, 16> cp8;
1590  Bitfield<19, 18> cp9;
1591  Bitfield<21, 20> cp10;
1592  Bitfield<21, 20> fpen; // AArch64
1593  Bitfield<23, 22> cp11;
1594  Bitfield<25, 24> cp12;
1595  Bitfield<27, 26> cp13;
1596  Bitfield<29, 28> rsvd;
1597  Bitfield<28> tta; // AArch64
1598  Bitfield<30> d32dis;
1599  Bitfield<31> asedis;
1600  EndBitUnion(CPACR)
1601 
1602  BitUnion32(FSR)
1603  Bitfield<3, 0> fsLow;
1604  Bitfield<5, 0> status; // LPAE
1605  Bitfield<7, 4> domain;
1606  Bitfield<9> lpae;
1607  Bitfield<10> fsHigh;
1608  Bitfield<11> wnr;
1609  Bitfield<12> ext;
1610  Bitfield<13> cm; // LPAE
1611  EndBitUnion(FSR)
1612 
1613  BitUnion32(FPSCR)
1614  Bitfield<0> ioc;
1615  Bitfield<1> dzc;
1616  Bitfield<2> ofc;
1617  Bitfield<3> ufc;
1618  Bitfield<4> ixc;
1619  Bitfield<7> idc;
1620  Bitfield<8> ioe;
1621  Bitfield<9> dze;
1622  Bitfield<10> ofe;
1623  Bitfield<11> ufe;
1624  Bitfield<12> ixe;
1625  Bitfield<15> ide;
1626  Bitfield<18, 16> len;
1627  Bitfield<21, 20> stride;
1628  Bitfield<23, 22> rMode;
1629  Bitfield<24> fz;
1630  Bitfield<25> dn;
1631  Bitfield<26> ahp;
1632  Bitfield<27> qc;
1633  Bitfield<28> v;
1634  Bitfield<29> c;
1635  Bitfield<30> z;
1636  Bitfield<31> n;
1637  EndBitUnion(FPSCR)
1638 
1639  // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1640  // integer register to allow renaming.
1641  static const uint32_t FpCondCodesMask = 0xF0000000;
1642  // This mask selects the cumulative FP exception flags of the FPSCR.
1643  static const uint32_t FpscrExcMask = 0x0000009F;
1644  // This mask selects the cumulative saturation flag of the FPSCR.
1645  static const uint32_t FpscrQcMask = 0x08000000;
1646 
1647  BitUnion32(FPEXC)
1648  Bitfield<31> ex;
1649  Bitfield<30> en;
1650  Bitfield<29, 0> subArchDefined;
1651  EndBitUnion(FPEXC)
1652 
1653  BitUnion32(MVFR0)
1654  Bitfield<3, 0> advSimdRegisters;
1655  Bitfield<7, 4> singlePrecision;
1656  Bitfield<11, 8> doublePrecision;
1657  Bitfield<15, 12> vfpExceptionTrapping;
1658  Bitfield<19, 16> divide;
1659  Bitfield<23, 20> squareRoot;
1660  Bitfield<27, 24> shortVectors;
1661  Bitfield<31, 28> roundingModes;
1662  EndBitUnion(MVFR0)
1663 
1664  BitUnion32(MVFR1)
1665  Bitfield<3, 0> flushToZero;
1666  Bitfield<7, 4> defaultNaN;
1667  Bitfield<11, 8> advSimdLoadStore;
1668  Bitfield<15, 12> advSimdInteger;
1669  Bitfield<19, 16> advSimdSinglePrecision;
1670  Bitfield<23, 20> advSimdHalfPrecision;
1671  Bitfield<27, 24> vfpHalfPrecision;
1672  Bitfield<31, 28> raz;
1673  EndBitUnion(MVFR1)
1674 
1675  BitUnion64(TTBCR)
1676  // Short-descriptor translation table format
1677  Bitfield<2, 0> n;
1678  Bitfield<4> pd0;
1679  Bitfield<5> pd1;
1680  // Long-descriptor translation table format
1681  Bitfield<5, 0> t0sz;
1682  Bitfield<7> epd0;
1683  Bitfield<9, 8> irgn0;
1684  Bitfield<11, 10> orgn0;
1685  Bitfield<13, 12> sh0;
1686  Bitfield<14> tg0;
1687  Bitfield<21, 16> t1sz;
1688  Bitfield<22> a1;
1689  Bitfield<23> epd1;
1690  Bitfield<25, 24> irgn1;
1691  Bitfield<27, 26> orgn1;
1692  Bitfield<29, 28> sh1;
1693  Bitfield<30> tg1;
1694  Bitfield<34, 32> ips;
1695  Bitfield<36> as;
1696  Bitfield<37> tbi0;
1697  Bitfield<38> tbi1;
1698  // Common
1699  Bitfield<31> eae;
1700  // TCR_EL2/3 (AArch64)
1701  Bitfield<18, 16> ps;
1702  Bitfield<20> tbi;
1703  EndBitUnion(TTBCR)
1704 
1705  // Fields of TCR_EL{1,2,3} (mostly overlapping)
1706  // TCR_EL1 is natively 64 bits, the others are 32 bits
1707  BitUnion64(TCR)
1708  Bitfield<5, 0> t0sz;
1709  Bitfield<7> epd0; // EL1
1710  Bitfield<9, 8> irgn0;
1711  Bitfield<11, 10> orgn0;
1712  Bitfield<13, 12> sh0;
1713  Bitfield<15, 14> tg0;
1714  Bitfield<18, 16> ps;
1715  Bitfield<20> tbi; // EL2/EL3
1716  Bitfield<21, 16> t1sz; // EL1
1717  Bitfield<22> a1; // EL1
1718  Bitfield<23> epd1; // EL1
1719  Bitfield<25, 24> irgn1; // EL1
1720  Bitfield<27, 26> orgn1; // EL1
1721  Bitfield<29, 28> sh1; // EL1
1722  Bitfield<31, 30> tg1; // EL1
1723  Bitfield<34, 32> ips; // EL1
1724  Bitfield<36> as; // EL1
1725  Bitfield<37> tbi0; // EL1
1726  Bitfield<38> tbi1; // EL1
1727  EndBitUnion(TCR)
1728 
1729  BitUnion32(HTCR)
1730  Bitfield<2, 0> t0sz;
1731  Bitfield<9, 8> irgn0;
1732  Bitfield<11, 10> orgn0;
1733  Bitfield<13, 12> sh0;
1734  EndBitUnion(HTCR)
1735 
1736  BitUnion32(VTCR_t)
1737  Bitfield<3, 0> t0sz;
1738  Bitfield<4> s;
1739  Bitfield<5, 0> t0sz64;
1740  Bitfield<7, 6> sl0;
1741  Bitfield<9, 8> irgn0;
1742  Bitfield<11, 10> orgn0;
1743  Bitfield<13, 12> sh0;
1744  Bitfield<15, 14> tg0;
1745  EndBitUnion(VTCR_t)
1746 
1747  BitUnion32(PRRR)
1748  Bitfield<1,0> tr0;
1749  Bitfield<3,2> tr1;
1750  Bitfield<5,4> tr2;
1751  Bitfield<7,6> tr3;
1752  Bitfield<9,8> tr4;
1753  Bitfield<11,10> tr5;
1754  Bitfield<13,12> tr6;
1755  Bitfield<15,14> tr7;
1756  Bitfield<16> ds0;
1757  Bitfield<17> ds1;
1758  Bitfield<18> ns0;
1759  Bitfield<19> ns1;
1760  Bitfield<24> nos0;
1761  Bitfield<25> nos1;
1762  Bitfield<26> nos2;
1763  Bitfield<27> nos3;
1764  Bitfield<28> nos4;
1765  Bitfield<29> nos5;
1766  Bitfield<30> nos6;
1767  Bitfield<31> nos7;
1768  EndBitUnion(PRRR)
1769 
1770  BitUnion32(NMRR)
1771  Bitfield<1,0> ir0;
1772  Bitfield<3,2> ir1;
1773  Bitfield<5,4> ir2;
1774  Bitfield<7,6> ir3;
1775  Bitfield<9,8> ir4;
1776  Bitfield<11,10> ir5;
1777  Bitfield<13,12> ir6;
1778  Bitfield<15,14> ir7;
1779  Bitfield<17,16> or0;
1780  Bitfield<19,18> or1;
1781  Bitfield<21,20> or2;
1782  Bitfield<23,22> or3;
1783  Bitfield<25,24> or4;
1784  Bitfield<27,26> or5;
1785  Bitfield<29,28> or6;
1786  Bitfield<31,30> or7;
1787  EndBitUnion(NMRR)
1788 
1789  BitUnion32(CONTEXTIDR)
1790  Bitfield<7,0> asid;
1791  Bitfield<31,8> procid;
1792  EndBitUnion(CONTEXTIDR)
1793 
1794  BitUnion32(L2CTLR)
1795  Bitfield<2,0> sataRAMLatency;
1796  Bitfield<4,3> reserved_4_3;
1797  Bitfield<5> dataRAMSetup;
1798  Bitfield<8,6> tagRAMLatency;
1799  Bitfield<9> tagRAMSetup;
1800  Bitfield<11,10> dataRAMSlice;
1801  Bitfield<12> tagRAMSlice;
1802  Bitfield<20,13> reserved_20_13;
1803  Bitfield<21> eccandParityEnable;
1804  Bitfield<22> reserved_22;
1805  Bitfield<23> interptCtrlPresent;
1806  Bitfield<25,24> numCPUs;
1807  Bitfield<30,26> reserved_30_26;
1808  Bitfield<31> l2rstDISABLE_monitor;
1809  EndBitUnion(L2CTLR)
1810 
1811  BitUnion32(CTR)
1812  Bitfield<3,0> iCacheLineSize;
1813  Bitfield<13,4> raz_13_4;
1814  Bitfield<15,14> l1IndexPolicy;
1815  Bitfield<19,16> dCacheLineSize;
1816  Bitfield<23,20> erg;
1817  Bitfield<27,24> cwg;
1818  Bitfield<28> raz_28;
1819  Bitfield<31,29> format;
1820  EndBitUnion(CTR)
1821 
1822  BitUnion32(PMSELR)
1823  Bitfield<4, 0> sel;
1824  EndBitUnion(PMSELR)
1825 
1826  BitUnion64(PAR)
1827  // 64-bit format
1828  Bitfield<63, 56> attr;
1829  Bitfield<39, 12> pa;
1830  Bitfield<11> lpae;
1831  Bitfield<9> ns;
1832  Bitfield<8, 7> sh;
1833  Bitfield<0> f;
1834  EndBitUnion(PAR)
1835 
1836  BitUnion32(ESR)
1837  Bitfield<31, 26> ec;
1838  Bitfield<25> il;
1839  Bitfield<15, 0> imm16;
1840  EndBitUnion(ESR)
1841 
1842  BitUnion32(CPTR)
1843  Bitfield<31> tcpac;
1844  Bitfield<20> tta;
1845  Bitfield<13, 12> res1_13_12_el2;
1846  Bitfield<10> tfp;
1847  Bitfield<9, 0> res1_9_0_el2;
1848  EndBitUnion(CPTR)
1849 
1850 
1864  std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
1865  CPSR cpsr);
1866 
1880  std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
1881  CPSR cpsr);
1882 
1883  // Checks read access permissions to AArch64 system registers
1884  bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1885  ThreadContext *tc);
1886 
1887  // Checks write access permissions to AArch64 system registers
1888  bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1889  ThreadContext *tc);
1890 
1891  // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1892  // for MCR/MRC instructions
1893  int
1895 
1896  // Flattens a misc reg index using the specified security state. This is
1897  // used for opperations (eg address translations) where the security
1898  // state of the register access may differ from the current state of the
1899  // processor
1900  int
1902 
1903  // Takes a misc reg index and returns the root reg if its one of a set of
1904  // banked registers
1905  void
1907 
1908  int
1909  unflattenMiscReg(int reg);
1910 
1911 }
1912 
1913 #endif // __ARCH_ARM_MISCREGS_HH__
Bitfield< 13, 12 > ir6
Definition: miscregs.hh:1777
std::tuple< bool, bool > canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
Definition: miscregs.cc:1973
Bitfield< 31 > asedis
Definition: miscregs.hh:1599
Bitfield< 31, 8 > procid
Definition: miscregs.hh:1791
Bitfield< 23 > tpc
Definition: miscregs.hh:1458
Bitfield< 3, 2 > tr1
Definition: miscregs.hh:1749
Bitfield< 24 > fz
Definition: miscregs.hh:1629
Bitfield< 9, 8 > irgn0
Definition: miscregs.hh:1683
Bitfield< 15 > te
Definition: mt_constants.hh:62
MiscRegIndex
Definition: miscregs.hh:57
bitset< NUM_MISCREG_INFOS > miscRegInfo[NUM_MISCREGS]
Definition: miscregs.cc:131
Bitfield< 5, 3 > reg
Definition: types.hh:89
Bitfield< 26 > tvm
Definition: miscregs.hh:1455
Bitfield< 28 > v
Definition: miscregs.hh:1366
Bitfield< 8 > hce
Definition: miscregs.hh:1512
Bitfield< 11 > tcp11
Definition: miscregs.hh:1411
Bitfield< 20, 13 > reserved_20_13
Definition: miscregs.hh:1802
Bitfield< 7 > i
Definition: miscregs.hh:1378
Bitfield< 7 > hpme
Definition: miscregs.hh:1399
Bitfield< 0 > m
Definition: miscregs.hh:1577
Bitfield< 29 > hcd
Definition: miscregs.hh:1451
Bitfield< 31, 28 > roundingModes
Definition: miscregs.hh:1661
Bitfield< 2 > t2
Definition: miscregs.hh:1441
Bitfield< 10 > fsHigh
Definition: miscregs.hh:1607
Bitfield< 11 > z
Definition: miscregs.hh:1558
Bitfield< 31 > eae
Definition: miscregs.hh:1699
Bitfield< 9 > tagRAMSetup
Definition: miscregs.hh:1799
Bitfield< 30 > trvm
Definition: miscregs.hh:1450
Bitfield< 15, 14 > l1IndexPolicy
Definition: miscregs.hh:1814
Bitfield< 6 > tpm
Definition: miscregs.hh:1400
Bitfield< 21, 20 > stride
Definition: miscregs.hh:1627
Bitfield< 27, 24 > shortVectors
Definition: miscregs.hh:1660
Bitfield< 8 > a
Definition: miscregs.hh:1377
Bitfield< 17 > tid2
Definition: miscregs.hh:1465
Bitfield< 8, 7 > sh
Definition: miscregs.hh:1832
advSimdRegisters
Definition: miscregs.hh:1654
Bitfield< 21 > tacr
Definition: miscregs.hh:1461
Bitfield< 29, 28 > or6
Definition: miscregs.hh:1785
Bitfield< 8, 6 > aif
Definition: miscregs.hh:1380
Bitfield< 31 > nos7
Definition: miscregs.hh:1767
Bitfield< 5, 4 > tr2
Definition: miscregs.hh:1750
Bitfield< 13 > twi
Definition: miscregs.hh:1469
Bitfield< 0 > sp
Definition: miscregs.hh:1386
Bitfield< 31, 28 > raz
Definition: miscregs.hh:1672
Bitfield< 15, 14 > ir7
Definition: miscregs.hh:1778
Bitfield< 15, 12 > advSimdInteger
Definition: miscregs.hh:1668
Bitfield< 27 > tge
Definition: miscregs.hh:1454
Bitfield< 16 > ttee
Definition: miscregs.hh:1428
Bitfield< 7 > itd
Definition: miscregs.hh:1565
Bitfield< 14 > dze
Definition: miscregs.hh:1554
Bitfield< 26 > uci
Definition: miscregs.hh:1529
Bitfield< 15 > t15
Definition: miscregs.hh:1429
Bitfield< 7 > cp7
Definition: miscregs.hh:1496
Bitfield< 4, 0 > hpmn
Definition: miscregs.hh:1402
Bitfield< 12 > ext
Definition: miscregs.hh:1609
Bitfield< 5 > pd1
Definition: miscregs.hh:1679
Bitfield< 12 > cp12
Definition: miscregs.hh:1491
preUnflattenMiscReg()
Definition: miscregs.cc:2074
Bitfield< 13 > t13
Definition: miscregs.hh:1430
const char *const miscRegName[]
Definition: miscregs.hh:739
Bitfield< 20 > tidcp
Definition: miscregs.hh:1462
Bitfield< 23, 22 > res0_23_22
Definition: miscregs.hh:1370
Bitfield< 4, 0 > mode
Definition: miscregs.hh:1385
Bitfield< 30 > en
Definition: miscregs.hh:1649
Bitfield< 0 > t0
Definition: miscregs.hh:1443
Bitfield< 14 > twe
Definition: miscregs.hh:1468
Bitfield< 19, 16 > divide
Definition: miscregs.hh:1658
Bitfield< 9 > lpae
Definition: miscregs.hh:1606
Bitfield< 5 > dataRAMSetup
Definition: miscregs.hh:1797
Bitfield< 13, 12 > sh0
Definition: miscregs.hh:1685
Bitfield< 1 > cp1
Definition: miscregs.hh:1502
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Bitfield< 11, 8 > doublePrecision
Definition: miscregs.hh:1656
Bitfield< 30 > nos6
Definition: miscregs.hh:1766
Bitfield< 29 > afe
Definition: miscregs.hh:1526
Bitfield< 23 > interptCtrlPresent
Definition: miscregs.hh:1805
Bitfield< 4 > fw
Definition: miscregs.hh:1517
Bitfield< 9, 8 > ir4
Definition: miscregs.hh:1775
Bitfield< 14 > rr
Definition: miscregs.hh:1553
Bitfield< 16 > ds0
Definition: miscregs.hh:1756
Bitfield< 8 > tde
Definition: miscregs.hh:1398
MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1)
Definition: miscregs.cc:1926
Bitfield< 18 > ntwe
Definition: miscregs.hh:1545
Bitfield< 31 > n
Definition: miscregs.hh:1636
Bitfield< 15 > uct
Definition: miscregs.hh:1551
Bitfield< 14 > nsd32dis
Definition: miscregs.hh:1489
Bitfield< 22 > reserved_22
Definition: miscregs.hh:1804
Bitfield< 8 > ioe
Definition: miscregs.hh:1620
Bitfield< 6 > f
Definition: miscregs.hh:1379
BitUnion32(CPSR) Bitfield< 31
Bitfield< 24 > e0e
Definition: miscregs.hh:1534
Bitfield< 1 > dzc
Definition: miscregs.hh:1615
Bitfield< 4 > cp4
Definition: miscregs.hh:1499
Bitfield< 10 > sw
Definition: miscregs.hh:1559
Bitfield< 19, 18 > or1
Definition: miscregs.hh:1780
Bitfield< 16 > tid1
Definition: miscregs.hh:1466
Bitfield< 28 > raz_28
Definition: miscregs.hh:1818
Bitfield< 5, 0 > status
Definition: miscregs.hh:1604
Bitfield< 11 > ufe
Definition: miscregs.hh:1623
Bitfield< 5 > cp5
Definition: miscregs.hh:1498
Bitfield< 8 > t8
Definition: miscregs.hh:1435
Bitfield< 27 > nmfi
Definition: miscregs.hh:1528
Bitfield< 21 > eccandParityEnable
Definition: miscregs.hh:1803
Bitfield< 7 > b
Definition: miscregs.hh:1564
Bitfield< 10 > tdosa
Definition: miscregs.hh:1396
Bitfield< 2 > tcp2
Definition: miscregs.hh:1421
Bitfield< 19 > rfr
Definition: miscregs.hh:1487
Bitfield< 8 > cp8
Definition: miscregs.hh:1495
Bitfield< 0 > ns
Definition: miscregs.hh:1521
Bitfield< 21 > fi
Definition: miscregs.hh:1538
Bitfield< 26 > ahp
Definition: miscregs.hh:1631
Bitfield< 4 > tcp4
Definition: miscregs.hh:1419
Bitfield< 21 > tac
Definition: miscregs.hh:1460
Bitfield< 21, 16 > t1sz
Definition: miscregs.hh:1687
Bitfield< 30 > tg1
Definition: miscregs.hh:1693
Bitfield< 3, 2 > el
Definition: miscregs.hh:1384
Bitfield< 5 > tpmcr
Definition: miscregs.hh:1401
int unflattenMiscReg(int reg)
Definition: miscregs.cc:2090
Bitfield< 14 > tg0
Definition: miscregs.hh:1686
MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
Definition: miscregs.cc:2178
Bitfield< 2 > fiq
Definition: miscregs.hh:1519
Bitfield< 3 > cp3
Definition: miscregs.hh:1500
iCacheLineSize
Definition: miscregs.hh:1812
Bitfield< 4 > s
Definition: miscregs.hh:1738
Bitfield< 22 > u
Definition: miscregs.hh:1537
sataRAMLatency
Definition: miscregs.hh:1795
Bitfield< 5 > t5
Definition: miscregs.hh:1438
Bitfield< 11, 8 > advSimdLoadStore
Definition: miscregs.hh:1667
Bitfield< 13 > tcp13
Definition: miscregs.hh:1409
Bitfield< 2 > cp2
Definition: miscregs.hh:1501
Bitfield< 16 > rao3
Definition: miscregs.hh:1550
Bitfield< 13, 12 > res1_13_12_el2
Definition: miscregs.hh:1845
Bitfield< 11, 10 > tr5
Definition: miscregs.hh:1753
Bitfield< 5 > cp15ben
Definition: miscregs.hh:1570
Bitfield< 12 > ixe
Definition: miscregs.hh:1624
Bitfield< 27 > q
Definition: miscregs.hh:1367
Bitfield< 9 > tda
Definition: miscregs.hh:1397
Bitfield< 26, 25 > it1
Definition: miscregs.hh:1368
Bitfield< 5 > aw
Definition: miscregs.hh:1516
Bitfield< 9 > tcp9
Definition: miscregs.hh:1414
Bitfield< 2 > ptw
Definition: miscregs.hh:1480
Bitfield< 9 > d
Definition: miscregs.hh:1375
Bitfield< 7 > smd
Definition: miscregs.hh:1514
Bitfield< 0 > cp0
Definition: miscregs.hh:1503
Bitfield< 16 > ntwi
Definition: miscregs.hh:1548
Bitfield< 3 > t3
Definition: miscregs.hh:1440
Bitfield< 25 > dn
Definition: miscregs.hh:1630
Bitfield< 3 > sa
Definition: miscregs.hh:1574
Bitfield< 19 > ns1
Definition: miscregs.hh:1759
Bitfield< 39, 12 > pa
Definition: miscregs.hh:1829
Bitfield< 11, 10 > orgn0
Definition: miscregs.hh:1684
Bitfield< 24 > ve
Definition: miscregs.hh:1533
Bitfield< 3 > fmo
Definition: miscregs.hh:1479
Bitfield< 15 > tase
Definition: miscregs.hh:1408
Bitfield< 19 > wxn
Definition: miscregs.hh:1544
Bitfield< 24 > nos0
Definition: miscregs.hh:1760
Bitfield< 7, 4 > singlePrecision
Definition: miscregs.hh:1655
Bitfield< 13 > cp13
Definition: miscregs.hh:1490
static const uint32_t CpsrMaskQ
Definition: miscregs.hh:1392
Bitfield< 9, 8 > tr4
Definition: miscregs.hh:1752
Bitfield< 10 > ofe
Definition: miscregs.hh:1622
Bitfield< 9 > sif
Definition: miscregs.hh:1511
Bitfield< 28 > nos4
Definition: miscregs.hh:1764
Bitfield< 30 > d32dis
Definition: miscregs.hh:1598
Bitfield< 7 > scd
Definition: miscregs.hh:1513
Bitfield< 10 > t10
Definition: miscregs.hh:1433
Bitfield< 27 > qc
Definition: miscregs.hh:1632
bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Definition: miscregs.cc:2096
Bitfield< 23, 20 > squareRoot
Definition: miscregs.hh:1659
Bitfield< 7 > idc
Definition: miscregs.hh:1619
Bitfield< 7 > epd0
Definition: miscregs.hh:1682
Bitfield< 23 > xp
Definition: miscregs.hh:1536
Bitfield< 6, 3 > rao4
Definition: miscregs.hh:1567
Bitfield< 11 > wnr
Definition: miscregs.hh:1608
Bitfield< 21 > ss
Definition: miscregs.hh:1371
Bitfield< 28 > tdz
Definition: miscregs.hh:1452
bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
Definition: miscregs.cc:2134
Bitfield< 29, 28 > rsvd
Definition: miscregs.hh:1596
Bitfield< 27, 26 > or5
Definition: miscregs.hh:1784
Bitfield< 9 > cp9
Definition: miscregs.hh:1494
Bitfield< 15, 0 > imm16
Definition: miscregs.hh:1839
Bitfield< 9 > uma
Definition: miscregs.hh:1561
Bitfield< 13, 4 > raz_13_4
Definition: miscregs.hh:1813
Bitfield< 7, 4 > defaultNaN
Definition: miscregs.hh:1666
Bitfield< 25, 24 > numCPUs
Definition: miscregs.hh:1806
Bitfield< 5, 4 > ir2
Definition: miscregs.hh:1773
Bitfield< 29, 28 > sh1
Definition: miscregs.hh:1692
Bitfield< 8 > va
Definition: miscregs.hh:1473
Bitfield< 2 > ofc
Definition: miscregs.hh:1616
Bitfield< 6 > t6
Definition: miscregs.hh:1437
Bitfield< 20 > tta
Definition: miscregs.hh:1407
Bitfield< 19, 16 > dCacheLineSize
Definition: miscregs.hh:1815
Bitfield< 25 > ee
Definition: miscregs.hh:1532
Bitfield< 22 > tsw
Definition: miscregs.hh:1459
Bitfield< 7, 6 > ir3
Definition: miscregs.hh:1774
Bitfield< 7, 6 > tr3
Definition: miscregs.hh:1751
MiscRegInfo
Definition: miscregs.hh:680
Bitfield< 24 > j
Definition: miscregs.hh:1369
Bitfield< 7 > vi
Definition: miscregs.hh:1475
Bitfield< 4 > imo
Definition: miscregs.hh:1478
Bitfield< 11, 10 > bsu
Definition: miscregs.hh:1471
Bitfield< 4 > ixc
Definition: miscregs.hh:1618
Bitfield< 25, 24 > irgn1
Definition: miscregs.hh:1690
Bitfield< 36 > as
Definition: miscregs.hh:1695
Bitfield< 9 > e
Definition: miscregs.hh:1376
EndBitUnion(CPSR) static const uint32_t CondCodesMask=0xF00F0000
Bitfield< 3, 2 > ir1
Definition: miscregs.hh:1772
Bitfield< 25 > nos1
Definition: miscregs.hh:1761
Bitfield< 30, 26 > reserved_30_26
Definition: miscregs.hh:1807
Bitfield< 19, 16 > ge
Definition: miscregs.hh:1373
Bitfield< 10 > cp10
Definition: miscregs.hh:1493
Bitfield< 1 > irq
Definition: miscregs.hh:1520
Bitfield< 29 > c
Definition: miscregs.hh:1365
Bitfield< 5, 0 > t0sz64
Definition: miscregs.hh:1739
Bitfield< 6 > tcp6
Definition: miscregs.hh:1417
Bitfield< 4, 3 > reserved_4_3
Definition: miscregs.hh:1796
Bitfield< 9, 6 > daif
Definition: miscregs.hh:1381
Bitfield< 1 > t1
Definition: miscregs.hh:1442
Bitfield< 6 > vf
Definition: miscregs.hh:1476
Bitfield< 17 > ds1
Definition: miscregs.hh:1757
Bitfield< 37 > tbi0
Definition: miscregs.hh:1696
Bitfield< 7, 4 > domain
Definition: miscregs.hh:1605
Bitfield< 17, 16 > or0
Definition: miscregs.hh:1779
Bitfield< 31, 29 > format
Definition: miscregs.hh:1819
Bitfield< 11 > st
Definition: miscregs.hh:1509
Bitfield< 5 > amo
Definition: miscregs.hh:1477
Bitfield< 19, 16 > advSimdSinglePrecision
Definition: miscregs.hh:1669
Bitfield< 23, 20 > advSimdHalfPrecision
Definition: miscregs.hh:1670
Bitfield< 26 > nos2
Definition: miscregs.hh:1762
Bitfield< 15, 12 > vfpExceptionTrapping
Definition: miscregs.hh:1657
Bitfield< 9 > fb
Definition: miscregs.hh:1472
Bitfield< 29 > nos5
Definition: miscregs.hh:1765
std::tuple< bool, bool > canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
Check for permission to read coprocessor registers.
Definition: miscregs.cc:2009
Bitfield< 7, 6 > sl0
Definition: miscregs.hh:1740
Bitfield< 18 > rao2
Definition: miscregs.hh:1547
Bitfield< 7 > tcp7
Definition: miscregs.hh:1416
Bitfield< 10 > tfp
Definition: miscregs.hh:1413
Bitfield< 25, 24 > or4
Definition: miscregs.hh:1783
Bitfield< 28 > tre
Definition: miscregs.hh:1527
Bitfield< 15, 14 > tr7
Definition: miscregs.hh:1755
Bitfield< 8, 6 > tagRAMLatency
Definition: miscregs.hh:1798
Bitfield< 18, 16 > len
Definition: miscregs.hh:1626
Bitfield< 4 > width
Definition: miscregs.hh:1383
Bitfield< 13, 12 > tr6
Definition: miscregs.hh:1754
Bitfield< 31 > rw
Definition: miscregs.hh:1449
Bitfield< 5, 0 > t0sz
Definition: miscregs.hh:1681
Bitfield< 18 > ns0
Definition: miscregs.hh:1758
Bitfield< 10 > tcp10
Definition: miscregs.hh:1412
Bitfield< 31, 30 > or7
Definition: miscregs.hh:1786
Bitfield< 24 > tpu
Definition: miscregs.hh:1457
Bitfield< 27, 26 > orgn1
Definition: miscregs.hh:1691
Bitfield< 7, 5 > opc2
Definition: types.hh:111
Bitfield< 13 > cm
Definition: miscregs.hh:1610
bool aarch64SysRegReadOnly(MiscRegIndex miscReg)
Bitfield< 1 > swio
Definition: miscregs.hh:1481
Bitfield< 34, 32 > ips
Definition: miscregs.hh:1694
Bitfield< 7 > t7
Definition: miscregs.hh:1436
Bitfield< 4 > t4
Definition: miscregs.hh:1439
Bitfield< 27, 24 > vfpHalfPrecision
Definition: miscregs.hh:1671
static const uint32_t FpscrExcMask
Definition: miscregs.hh:1643
Bitfield< 5 > tcp5
Definition: miscregs.hh:1418
Bitfield< 23, 22 > or3
Definition: miscregs.hh:1782
Bitfield< 6 > cp6
Definition: miscregs.hh:1497
Bitfield< 32 > cd
Definition: miscregs.hh:1448
Bitfield< 12 > t12
Definition: miscregs.hh:1431
Bitfield< 19 > tsc
Definition: miscregs.hh:1463
Bitfield< 25 > ttlb
Definition: miscregs.hh:1456
Bitfield< 11, 10 > dataRAMSlice
Definition: miscregs.hh:1800
Bitfield< 8 > tcp8
Definition: miscregs.hh:1415
Bitfield< 5 > t
Definition: miscregs.hh:1382
Bitfield< 15 > ide
Definition: miscregs.hh:1625
Bitfield< 21, 20 > fpen
Definition: miscregs.hh:1592
Bitfield< 0 > vm
Definition: miscregs.hh:1482
Bitfield< 9, 0 > res1_9_0_el2
Definition: miscregs.hh:1847
int flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
Definition: miscregs.cc:2045
Bitfield< 3 > tcp3
Definition: miscregs.hh:1420
Bitfield< 9 > t9
Definition: miscregs.hh:1434
Bitfield< 18, 16 > ps
Definition: miscregs.hh:1701
#define BitUnion64(name)
Definition: bitunion.hh:327
Bitfield< 15 > nsasedis
Definition: miscregs.hh:1488
Bitfield< 15 > tid0
Definition: miscregs.hh:1467
MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: miscregs.cc:1359
Bitfield< 31 > l2rstDISABLE_monitor
Definition: miscregs.hh:1808
Bitfield< 6 > thee
Definition: miscregs.hh:1568
Bitfield< 9, 8 > rs
Definition: miscregs.hh:1560
Bitfield< 11 > cp11
Definition: miscregs.hh:1492
MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
Definition: miscregs.cc:55
Bitfield< 4 > pd0
Definition: miscregs.hh:1678
Bitfield< 27 > nos3
Definition: miscregs.hh:1763
Bitfield< 23, 22 > rMode
Definition: miscregs.hh:1628
Bitfield< 3 > ufc
Definition: miscregs.hh:1617
Bitfield< 0 > tcp0
Definition: miscregs.hh:1423
Bitfield< 12 > tcp12
Definition: miscregs.hh:1410
Bitfield< 3 > ea
Definition: miscregs.hh:1518
Bitfield< 22 > a1
Definition: miscregs.hh:1688
Bitfield< 29, 0 > subArchDefined
Definition: miscregs.hh:1650
Bitfield< 15, 10 > it2
Definition: miscregs.hh:1374
Bitfield< 21, 20 > or2
Definition: miscregs.hh:1781
Bitfield< 1 > tcp1
Definition: miscregs.hh:1422
Bitfield< 20 > uwxn
Definition: miscregs.hh:1540
Bitfield< 12 > dc
Definition: miscregs.hh:1470
Bitfield< 20 > il
Definition: miscregs.hh:1372
Bitfield< 12 > tagRAMSlice
Definition: miscregs.hh:1801
Bitfield< 19 > dz
Definition: miscregs.hh:1542
Bitfield< 8 > sed
Definition: miscregs.hh:1562
Bitfield< 20 > tbi
Definition: miscregs.hh:1702
static const uint32_t FpscrQcMask
Definition: miscregs.hh:1645
Bitfield< 18 > tid3
Definition: miscregs.hh:1464
Bitfield< 11 > t11
Definition: miscregs.hh:1432
Bitfield< 27, 24 > cwg
Definition: miscregs.hh:1817
Bitfield< 6 > nEt
Definition: miscregs.hh:1515
Bitfield< 23 > epd1
Definition: miscregs.hh:1689
Bitfield< 38 > tbi1
Definition: miscregs.hh:1697
Bitfield< 11, 10 > ir5
Definition: miscregs.hh:1776
Bitfield< 4 > sa0
Definition: miscregs.hh:1572
Bitfield< 8 > vse
Definition: miscregs.hh:1474
Bitfield< 23, 20 > erg
Definition: miscregs.hh:1816

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