This is exposed globally, independent of the ISA. More...

Namespaces
	ACPI

	ConditionTests

	IntelMP

	Kernel

	SMBios

Classes
class	E820Entry

class	E820Table

struct	CpuidResult

class	Decoder

struct	EmulEnv

class	X86FaultBase

class	X86Fault

class	X86Trap

class	X86Abort

class	X86Interrupt

class	UnimpInstFault

class	DivideError

class	DebugException

class	NonMaskableInterrupt

class	Breakpoint

class	OverflowTrap

class	BoundRange

class	InvalidOpcode

class	DeviceNotAvailable

class	DoubleFault

class	InvalidTSS

class	SegmentNotPresent

class	StackFault

class	GeneralProtection

class	PageFault

class	X87FpExceptionPending

class	AlignmentCheck

class	MachineCheck

class	SIMDFloatingPointFault

class	SecurityException

class	ExternalInterrupt

class	SystemManagementInterrupt

class	InitInterrupt

class	StartupInterrupt

class	SoftwareInterrupt

class	MacroopBase

class	FpOp
	Base classes for FpOps which provides a generateDisassembly method. More...

class	MemOp
	Base class for memory ops. More...

class	LdStOp
	Base class for load and store ops using one register. More...

class	LdStSplitOp
	Base class for load and store ops using two registers, we will call them split ops for this reason. More...

class	MediaOpBase

class	MediaOpReg

class	MediaOpImm

class	X86MicroopBase

class	RegOpBase
	Base classes for RegOps which provides a generateDisassembly method. More...

class	RegOp

class	RegOpImm

struct	InstRegIndex
	Class for register indices passed to instruction constructors. More...

class	X86StaticInst
	Base class for all X86 static instructions. More...

class	Interrupts

class	ISA

class	X86_64LinuxProcess

class	I386LinuxProcess

class	PageTableOps
	Page table operations specific to x86 ISA. More...

class	Walker

class	X86Process

class	X86_64Process

class	I386Process

union	AnyReg

class	RemoteGDB

class	ProcessInfo

class	StackTrace

class	TLB

struct	ExtMachInst

class	PCState

class	Cmos

class	PS2Device

class	PS2Mouse

class	PS2Keyboard

class	I8042

class	I82094AA

class	I8237

class	I8254

class	I8259

class	IntDevice

class	IntSinkPin

class	IntSourcePin

class	IntLine

class	Speaker

class	GpuTlbEntry

class	GpuTLB

Typedefs
typedef MultiLevelPageTable < PageTableOps >	ArchPageTable
	Declaration of architectural page table for x86. More...

typedef uint64_t	IntReg

typedef uint64_t	CCReg

typedef uint64_t	MiscReg

typedef double	FloatReg

typedef uint64_t	FloatRegBits

typedef uint16_t	RegIndex

typedef MsrMap::value_type	MsrVal

typedef std::unordered_map < Addr, MiscRegIndex >	MsrMap

typedef uint64_t	MachInst

typedef std::list< int >	ApicList

Enumerations
enum	StandardCpuidFunction { VendorAndLargestStdFunc, FamilyModelStepping, NumStandardCpuidFuncs }

enum	ExtendedCpuidFunctions { VendorAndLargestExtFunc, FamilyModelSteppingBrandFeatures, NameString1, NameString2, NameString3, L1CacheAndTLB, L2L3CacheAndL2TLB, APMInfo, LongModeAddressSize, NumExtendedCpuidFuncs }

enum	SizeType { NoImm, NI = NoImm, ByteImm, BY = ByteImm, WordImm, WO = WordImm, DWordImm, DW = DWordImm, QWordImm, QW = QWordImm, OWordImm, OW = OWordImm, VWordImm, VW = VWordImm, ZWordImm, ZW = ZWordImm, Enter, EN = Enter, Pointer, PO = Pointer }

enum	MediaFlag { MediaMultHiOp = 1, MediaSignedOp = 64, MediaScalarOp = 128 }

enum	FlagBit { CPL0FlagBit = 1, AddrSizeFlagBit = 2, StoreCheck = 4 }

enum	PTEField { PTE_NotPresent = 1, PTE_Supervisor = 2, PTE_ReadOnly = 4, PTE_Uncacheable = 8 }

enum	X86AuxiliaryVectorTypes { M5_AT_SYSINFO = 32, M5_AT_SYSINFO_EHDR = 33 }

enum	DependenceTags { FP_Reg_Base = 128, CC_Reg_Base = FP_Reg_Base + NumFloatRegs, Misc_Reg_Base = CC_Reg_Base + NumCCRegs, Max_Reg_Index = Misc_Reg_Base + NumMiscRegs }

enum	ApicRegIndex { APIC_ID, APIC_VERSION, APIC_TASK_PRIORITY, APIC_ARBITRATION_PRIORITY, APIC_PROCESSOR_PRIORITY, APIC_EOI, APIC_LOGICAL_DESTINATION, APIC_DESTINATION_FORMAT, APIC_SPURIOUS_INTERRUPT_VECTOR, APIC_IN_SERVICE_BASE, APIC_TRIGGER_MODE_BASE = APIC_IN_SERVICE_BASE + 16, APIC_INTERRUPT_REQUEST_BASE = APIC_TRIGGER_MODE_BASE + 16, APIC_ERROR_STATUS = APIC_INTERRUPT_REQUEST_BASE + 16, APIC_INTERRUPT_COMMAND_LOW, APIC_INTERRUPT_COMMAND_HIGH, APIC_LVT_TIMER, APIC_LVT_THERMAL_SENSOR, APIC_LVT_PERFORMANCE_MONITORING_COUNTERS, APIC_LVT_LINT0, APIC_LVT_LINT1, APIC_LVT_ERROR, APIC_INITIAL_COUNT, APIC_CURRENT_COUNT, APIC_DIVIDE_CONFIGURATION, APIC_INTERNAL_STATE, NUM_APIC_REGS }

enum	CCRegIndex { CCREG_ZAPS, CCREG_CFOF, CCREG_DF, CCREG_ECF, CCREG_EZF, NUM_CCREGS }

enum	FloatRegIndex { FLOATREG_MMX_BASE, FLOATREG_FPR_BASE = FLOATREG_MMX_BASE, FLOATREG_MMX0 = FLOATREG_MMX_BASE, FLOATREG_MMX1, FLOATREG_MMX2, FLOATREG_MMX3, FLOATREG_MMX4, FLOATREG_MMX5, FLOATREG_MMX6, FLOATREG_MMX7, FLOATREG_FPR0 = FLOATREG_FPR_BASE, FLOATREG_FPR1, FLOATREG_FPR2, FLOATREG_FPR3, FLOATREG_FPR4, FLOATREG_FPR5, FLOATREG_FPR6, FLOATREG_FPR7, FLOATREG_XMM_BASE = FLOATREG_MMX_BASE + NumMMXRegs, FLOATREG_XMM0_LOW = FLOATREG_XMM_BASE, FLOATREG_XMM0_HIGH, FLOATREG_XMM1_LOW, FLOATREG_XMM1_HIGH, FLOATREG_XMM2_LOW, FLOATREG_XMM2_HIGH, FLOATREG_XMM3_LOW, FLOATREG_XMM3_HIGH, FLOATREG_XMM4_LOW, FLOATREG_XMM4_HIGH, FLOATREG_XMM5_LOW, FLOATREG_XMM5_HIGH, FLOATREG_XMM6_LOW, FLOATREG_XMM6_HIGH, FLOATREG_XMM7_LOW, FLOATREG_XMM7_HIGH, FLOATREG_XMM8_LOW, FLOATREG_XMM8_HIGH, FLOATREG_XMM9_LOW, FLOATREG_XMM9_HIGH, FLOATREG_XMM10_LOW, FLOATREG_XMM10_HIGH, FLOATREG_XMM11_LOW, FLOATREG_XMM11_HIGH, FLOATREG_XMM12_LOW, FLOATREG_XMM12_HIGH, FLOATREG_XMM13_LOW, FLOATREG_XMM13_HIGH, FLOATREG_XMM14_LOW, FLOATREG_XMM14_HIGH, FLOATREG_XMM15_LOW, FLOATREG_XMM15_HIGH, FLOATREG_MICROFP_BASE = FLOATREG_XMM_BASE + 2 * NumXMMRegs, FLOATREG_MICROFP0 = FLOATREG_MICROFP_BASE, FLOATREG_MICROFP1, FLOATREG_MICROFP2, FLOATREG_MICROFP3, FLOATREG_MICROFP4, FLOATREG_MICROFP5, FLOATREG_MICROFP6, FLOATREG_MICROFP7, NUM_FLOATREGS = FLOATREG_MICROFP_BASE + NumMicroFpRegs }

enum	CondFlagBit { CFBit = 1 << 0, PFBit = 1 << 2, ECFBit = 1 << 3, AFBit = 1 << 4, EZFBit = 1 << 5, ZFBit = 1 << 6, SFBit = 1 << 7, DFBit = 1 << 10, OFBit = 1 << 11 }

enum	RFLAGBit { TFBit = 1 << 8, IFBit = 1 << 9, NTBit = 1 << 14, RFBit = 1 << 16, VMBit = 1 << 17, ACBit = 1 << 18, VIFBit = 1 << 19, VIPBit = 1 << 20, IDBit = 1 << 21 }

enum	X87StatusBit { IEBit = 1 << 0, DEBit = 1 << 1, ZEBit = 1 << 2, OEBit = 1 << 3, UEBit = 1 << 4, PEBit = 1 << 5, StackFaultBit = 1 << 6, ErrSummaryBit = 1 << 7, CC0Bit = 1 << 8, CC1Bit = 1 << 9, CC2Bit = 1 << 10, CC3Bit = 1 << 14, BusyBit = 1 << 15 }

enum	MiscRegIndex { MISCREG_CR_BASE, MISCREG_CR0 = MISCREG_CR_BASE, MISCREG_CR1, MISCREG_CR2, MISCREG_CR3, MISCREG_CR4, MISCREG_CR5, MISCREG_CR6, MISCREG_CR7, MISCREG_CR8, MISCREG_CR9, MISCREG_CR10, MISCREG_CR11, MISCREG_CR12, MISCREG_CR13, MISCREG_CR14, MISCREG_CR15, MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, MISCREG_DR0 = MISCREG_DR_BASE, MISCREG_DR1, MISCREG_DR2, MISCREG_DR3, MISCREG_DR4, MISCREG_DR5, MISCREG_DR6, MISCREG_DR7, MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, MISCREG_M5_REG, MISCREG_TSC, MISCREG_MTRRCAP, MISCREG_SYSENTER_CS, MISCREG_SYSENTER_ESP, MISCREG_SYSENTER_EIP, MISCREG_MCG_CAP, MISCREG_MCG_STATUS, MISCREG_MCG_CTL, MISCREG_DEBUG_CTL_MSR, MISCREG_LAST_BRANCH_FROM_IP, MISCREG_LAST_BRANCH_TO_IP, MISCREG_LAST_EXCEPTION_FROM_IP, MISCREG_LAST_EXCEPTION_TO_IP, MISCREG_MTRR_PHYS_BASE_BASE, MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, MISCREG_MTRR_PHYS_BASE_1, MISCREG_MTRR_PHYS_BASE_2, MISCREG_MTRR_PHYS_BASE_3, MISCREG_MTRR_PHYS_BASE_4, MISCREG_MTRR_PHYS_BASE_5, MISCREG_MTRR_PHYS_BASE_6, MISCREG_MTRR_PHYS_BASE_7, MISCREG_MTRR_PHYS_BASE_END, MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END, MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, MISCREG_MTRR_PHYS_MASK_1, MISCREG_MTRR_PHYS_MASK_2, MISCREG_MTRR_PHYS_MASK_3, MISCREG_MTRR_PHYS_MASK_4, MISCREG_MTRR_PHYS_MASK_5, MISCREG_MTRR_PHYS_MASK_6, MISCREG_MTRR_PHYS_MASK_7, MISCREG_MTRR_PHYS_MASK_END, MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END, MISCREG_MTRR_FIX_16K_80000, MISCREG_MTRR_FIX_16K_A0000, MISCREG_MTRR_FIX_4K_C0000, MISCREG_MTRR_FIX_4K_C8000, MISCREG_MTRR_FIX_4K_D0000, MISCREG_MTRR_FIX_4K_D8000, MISCREG_MTRR_FIX_4K_E0000, MISCREG_MTRR_FIX_4K_E8000, MISCREG_MTRR_FIX_4K_F0000, MISCREG_MTRR_FIX_4K_F8000, MISCREG_PAT, MISCREG_DEF_TYPE, MISCREG_MC_CTL_BASE, MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, MISCREG_MC1_CTL, MISCREG_MC2_CTL, MISCREG_MC3_CTL, MISCREG_MC4_CTL, MISCREG_MC5_CTL, MISCREG_MC6_CTL, MISCREG_MC7_CTL, MISCREG_MC_CTL_END, MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END, MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, MISCREG_MC1_STATUS, MISCREG_MC2_STATUS, MISCREG_MC3_STATUS, MISCREG_MC4_STATUS, MISCREG_MC5_STATUS, MISCREG_MC6_STATUS, MISCREG_MC7_STATUS, MISCREG_MC_STATUS_END, MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END, MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, MISCREG_MC1_ADDR, MISCREG_MC2_ADDR, MISCREG_MC3_ADDR, MISCREG_MC4_ADDR, MISCREG_MC5_ADDR, MISCREG_MC6_ADDR, MISCREG_MC7_ADDR, MISCREG_MC_ADDR_END, MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END, MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, MISCREG_MC1_MISC, MISCREG_MC2_MISC, MISCREG_MC3_MISC, MISCREG_MC4_MISC, MISCREG_MC5_MISC, MISCREG_MC6_MISC, MISCREG_MC7_MISC, MISCREG_MC_MISC_END, MISCREG_EFER = MISCREG_MC_MISC_END, MISCREG_STAR, MISCREG_LSTAR, MISCREG_CSTAR, MISCREG_SF_MASK, MISCREG_KERNEL_GS_BASE, MISCREG_TSC_AUX, MISCREG_PERF_EVT_SEL_BASE, MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, MISCREG_PERF_EVT_SEL1, MISCREG_PERF_EVT_SEL2, MISCREG_PERF_EVT_SEL3, MISCREG_PERF_EVT_SEL_END, MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END, MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, MISCREG_PERF_EVT_CTR1, MISCREG_PERF_EVT_CTR2, MISCREG_PERF_EVT_CTR3, MISCREG_PERF_EVT_CTR_END, MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END, MISCREG_IORR_BASE_BASE, MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, MISCREG_IORR_BASE1, MISCREG_IORR_BASE_END, MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END, MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, MISCREG_IORR_MASK1, MISCREG_IORR_MASK_END, MISCREG_TOP_MEM = MISCREG_IORR_MASK_END, MISCREG_TOP_MEM2, MISCREG_VM_CR, MISCREG_IGNNE, MISCREG_SMM_CTL, MISCREG_VM_HSAVE_PA, MISCREG_SEG_SEL_BASE, MISCREG_ES = MISCREG_SEG_SEL_BASE, MISCREG_CS, MISCREG_SS, MISCREG_DS, MISCREG_FS, MISCREG_GS, MISCREG_HS, MISCREG_TSL, MISCREG_TSG, MISCREG_LS, MISCREG_MS, MISCREG_TR, MISCREG_IDTR, MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, MISCREG_CS_BASE, MISCREG_SS_BASE, MISCREG_DS_BASE, MISCREG_FS_BASE, MISCREG_GS_BASE, MISCREG_HS_BASE, MISCREG_TSL_BASE, MISCREG_TSG_BASE, MISCREG_LS_BASE, MISCREG_MS_BASE, MISCREG_TR_BASE, MISCREG_IDTR_BASE, MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, MISCREG_CS_EFF_BASE, MISCREG_SS_EFF_BASE, MISCREG_DS_EFF_BASE, MISCREG_FS_EFF_BASE, MISCREG_GS_EFF_BASE, MISCREG_HS_EFF_BASE, MISCREG_TSL_EFF_BASE, MISCREG_TSG_EFF_BASE, MISCREG_LS_EFF_BASE, MISCREG_MS_EFF_BASE, MISCREG_TR_EFF_BASE, MISCREG_IDTR_EFF_BASE, MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, MISCREG_CS_LIMIT, MISCREG_SS_LIMIT, MISCREG_DS_LIMIT, MISCREG_FS_LIMIT, MISCREG_GS_LIMIT, MISCREG_HS_LIMIT, MISCREG_TSL_LIMIT, MISCREG_TSG_LIMIT, MISCREG_LS_LIMIT, MISCREG_MS_LIMIT, MISCREG_TR_LIMIT, MISCREG_IDTR_LIMIT, MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, MISCREG_CS_ATTR, MISCREG_SS_ATTR, MISCREG_DS_ATTR, MISCREG_FS_ATTR, MISCREG_GS_ATTR, MISCREG_HS_ATTR, MISCREG_TSL_ATTR, MISCREG_TSG_ATTR, MISCREG_LS_ATTR, MISCREG_MS_ATTR, MISCREG_TR_ATTR, MISCREG_IDTR_ATTR, MISCREG_X87_TOP, MISCREG_MXCSR, MISCREG_FCW, MISCREG_FSW, MISCREG_FTW, MISCREG_FTAG, MISCREG_FISEG, MISCREG_FIOFF, MISCREG_FOSEG, MISCREG_FOOFF, MISCREG_FOP, MISCREG_APIC_BASE, MISCREG_PCI_CONFIG_ADDRESS, NUM_MISCREGS }

enum	SegmentRegIndex { SEGMENT_REG_ES, SEGMENT_REG_CS, SEGMENT_REG_SS, SEGMENT_REG_DS, SEGMENT_REG_FS, SEGMENT_REG_GS, SEGMENT_REG_HS, SEGMENT_REG_TSL, SEGMENT_REG_TSG, SEGMENT_REG_LS, SEGMENT_REG_MS, SYS_SEGMENT_REG_TR, SYS_SEGMENT_REG_IDTR, NUM_SEGMENTREGS }

enum	Prefixes { NoOverride, ESOverride, CSOverride, SSOverride, DSOverride, FSOverride, GSOverride, RexPrefix, OperandSizeOverride, AddressSizeOverride, Lock, Rep, Repne, Vex2Prefix, Vex3Prefix, XopPrefix }

enum	X86SubMode { SixtyFourBitMode, CompatabilityMode, ProtectedMode, Virtual8086Mode, RealMode }

Functions
uint64_t	stringToRegister (const char *str)

bool	doCpuid (ThreadContext *tc, uint32_t function, uint32_t index, CpuidResult &result)

ApicRegIndex	decodeAddr (Addr paddr)

	BitUnion32 (TriggerIntMessage) Bitfield<7

	EndBitUnion (TriggerIntMessage) namespace DeliveryMode

static PacketPtr	prepIntRequest (const uint8_t id, Addr offset, Addr size)

template<class T >
PacketPtr	buildIntRequest (const uint8_t id, T payload, Addr offset, Addr size)

static PacketPtr	buildIntRequest (const uint8_t id, TriggerIntMessage payload)

static PacketPtr	buildIntResponse ()

template<class XC >
void	handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)

template<class XC >
void	handleLockedRead (XC xc, Request req)

template<class XC >
bool	handleLockedWrite (XC xc, Request req, Addr cacheBlockMask)

template<class XC >
void	handleLockedSnoopHit (XC *xc)

template<class XC >
Fault	initiateMemRead (XC xc, Trace::InstRecord traceData, Addr addr, unsigned dataSize, Request::Flags flags)
	Initiate a read from memory in timing mode. More...

static void	getMem (PacketPtr pkt, uint64_t &mem, unsigned dataSize, Trace::InstRecord *traceData)

template<size_t N>
void	getMem (PacketPtr pkt, std::array< uint64_t, N > &mem, unsigned dataSize, Trace::InstRecord *traceData)

template<class XC >
Fault	readMemAtomic (XC xc, Trace::InstRecord traceData, Addr addr, uint64_t &mem, unsigned dataSize, Request::Flags flags)

template<class XC , size_t N>
Fault	readMemAtomic (XC xc, Trace::InstRecord traceData, Addr addr, std::array< uint64_t, N > &mem, unsigned dataSize, unsigned flags)

template<class XC >
Fault	writeMemTiming (XC xc, Trace::InstRecord traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res)

template<class XC , size_t N>
Fault	writeMemTiming (XC xc, Trace::InstRecord traceData, std::array< uint64_t, N > &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)

template<class XC >
Fault	writeMemAtomic (XC xc, Trace::InstRecord traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res)

template<class XC , size_t N>
Fault	writeMemAtomic (XC xc, Trace::InstRecord traceData, std::array< uint64_t, N > &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)

Cycles	handleIprRead (ThreadContext xc, Packet pkt)

Cycles	handleIprWrite (ThreadContext xc, Packet pkt)

	BitUnion64 (VAddr) Bitfield< 20

	EndBitUnion (VAddr) BitUnion64(PageTableEntry) Bitfield< 63 > nx

	TlbEntry (Addr asn, Addr _vaddr, Addr _paddr, bool uncacheable, bool read_only)

	TlbEntry ()

void	updateVaddr (Addr new_vaddr)

Addr	pageStart ()

int	size ()

void	serialize (CheckpointOut &cp) const override

void	unserialize (CheckpointIn &cp) override

void	m5Syscall (ThreadContext *tc)

void	m5PageFault (ThreadContext *tc)

static ApicRegIndex	APIC_IN_SERVICE (int index)

static ApicRegIndex	APIC_TRIGGER_MODE (int index)

static ApicRegIndex	APIC_INTERRUPT_REQUEST (int index)

	BitUnion32 (InterruptCommandRegLow) Bitfield<7

	EndBitUnion (InterruptCommandRegLow) BitUnion32(InterruptCommandRegHigh) Bitfield< 31

static FloatRegIndex	FLOATREG_MMX (int index)

static FloatRegIndex	FLOATREG_FPR (int index)

static FloatRegIndex	FLOATREG_XMM_LOW (int index)

static FloatRegIndex	FLOATREG_XMM_HIGH (int index)

static FloatRegIndex	FLOATREG_MICROFP (int index)

static FloatRegIndex	FLOATREG_STACK (int index, int top)

	BitUnion64 (X86IntReg) Bitfield< 63

	EndBitUnion (X86IntReg) enum IntRegIndex

static IntRegIndex	INTREG_MICRO (int index)

static IntRegIndex	INTREG_IMPLICIT (int index)

static IntRegIndex	INTREG_FOLDED (int index, int foldBit)

static bool	isValidMiscReg (int index)

static MiscRegIndex	MISCREG_CR (int index)

static MiscRegIndex	MISCREG_DR (int index)

static MiscRegIndex	MISCREG_MTRR_PHYS_BASE (int index)

static MiscRegIndex	MISCREG_MTRR_PHYS_MASK (int index)

static MiscRegIndex	MISCREG_MC_CTL (int index)

static MiscRegIndex	MISCREG_MC_STATUS (int index)

static MiscRegIndex	MISCREG_MC_ADDR (int index)

static MiscRegIndex	MISCREG_MC_MISC (int index)

static MiscRegIndex	MISCREG_PERF_EVT_SEL (int index)

static MiscRegIndex	MISCREG_PERF_EVT_CTR (int index)

static MiscRegIndex	MISCREG_IORR_BASE (int index)

static MiscRegIndex	MISCREG_IORR_MASK (int index)

static MiscRegIndex	MISCREG_SEG_SEL (int index)

static MiscRegIndex	MISCREG_SEG_BASE (int index)

static MiscRegIndex	MISCREG_SEG_EFF_BASE (int index)

static MiscRegIndex	MISCREG_SEG_LIMIT (int index)

static MiscRegIndex	MISCREG_SEG_ATTR (int index)

	BitUnion64 (CCFlagBits) Bitfield< 11 > of
	A type to describe the condition code bits of the RFLAGS register, plus two flags, EZF and ECF, which are only visible to microcode. More...

	EndBitUnion (CCFlagBits) BitUnion64(RFLAGS) Bitfield< 21 > id
	RFLAGS. More...

	EndBitUnion (RFLAGS) BitUnion64(HandyM5Reg) Bitfield< 0 > mode

	EndBitUnion (HandyM5Reg) BitUnion64(CR0) Bitfield< 31 > pg
	Control registers. More...

	EndBitUnion (CR0) BitUnion64(CR2) Bitfield< 31

	EndBitUnion (CR2) BitUnion64(CR3) Bitfield< 51

	EndBitUnion (CR3) BitUnion64(CR4) Bitfield< 18 > osxsave

	EndBitUnion (CR4) BitUnion64(CR8) Bitfield<3

	EndBitUnion (CR8) BitUnion64(DR6) Bitfield< 0 > b0

	EndBitUnion (DR6) BitUnion64(DR7) Bitfield< 0 > l0

	EndBitUnion (DR7) BitUnion64(MTRRcap) Bitfield<7

	EndBitUnion (MTRRcap) BitUnion64(SysenterCS) Bitfield< 15
	SYSENTER configuration registers. More...

	EndBitUnion (SysenterCS) BitUnion64(SysenterESP) Bitfield< 31

	EndBitUnion (SysenterESP) BitUnion64(SysenterEIP) Bitfield< 31

	EndBitUnion (SysenterEIP) BitUnion64(McgCap) Bitfield<7
	Global machine check registers. More...

	EndBitUnion (McgCap) BitUnion64(McgStatus) Bitfield< 0 > ripv

	EndBitUnion (McgStatus) BitUnion64(DebugCtlMsr) Bitfield< 0 > lbr

	EndBitUnion (DebugCtlMsr) BitUnion64(MtrrPhysBase) Bitfield<7

	EndBitUnion (MtrrPhysBase) BitUnion64(MtrrPhysMask) Bitfield< 11 > valid

	EndBitUnion (MtrrPhysMask) BitUnion64(MtrrFixed) EndBitUnion(MtrrFixed) BitUnion64(Pat) EndBitUnion(Pat) BitUnion64(MtrrDefType) Bitfield<7

	EndBitUnion (MtrrDefType) BitUnion64(McStatus) Bitfield< 15
	Machine check. More...

	EndBitUnion (McStatus) BitUnion64(McCtl) EndBitUnion(McCtl) BitUnion64(Efer) Bitfield< 0 > sce

	EndBitUnion (Efer) BitUnion64(Star) Bitfield< 31

	EndBitUnion (Star) BitUnion64(SfMask) Bitfield< 31

	EndBitUnion (SfMask) BitUnion64(PerfEvtSel) Bitfield<7

	EndBitUnion (PerfEvtSel) BitUnion32(Syscfg) Bitfield< 18 > mfde

	EndBitUnion (Syscfg) BitUnion64(IorrBase) Bitfield< 3 > wr

	EndBitUnion (IorrBase) BitUnion64(IorrMask) Bitfield< 11 > v

	EndBitUnion (IorrMask) BitUnion64(Tom) Bitfield< 51

	EndBitUnion (Tom) BitUnion64(VmCrMsr) Bitfield< 0 > dpd

	EndBitUnion (VmCrMsr) BitUnion64(IgnneMsr) Bitfield< 0 > ignne

	EndBitUnion (IgnneMsr) BitUnion64(SmmCtlMsr) Bitfield< 0 > dismiss

	EndBitUnion (SmmCtlMsr) BitUnion64(SegSelector) Bitfield< 63
	Segment Selector. More...

	EndBitUnion (SegSelector) BitUnion64(SegDescriptor) Bitfield< 63
	Segment Descriptors. More...

	SubBitUnion (type, 43, 40) Bitfield< 43 > codeOrData

	EndSubBitUnion (type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63
	TSS Descriptor (long mode - 128 bits) the lower 64 bits. More...

	EndBitUnion (TSShigh) BitUnion64(SegAttr) Bitfield<1

	EndBitUnion (SegAttr) BitUnion64(GateDescriptor) Bitfield< 63

	EndBitUnion (GateDescriptor) BitUnion64(GateDescriptorLow) Bitfield< 63
	Long Mode Gate Descriptor. More...

	EndBitUnion (GateDescriptorLow) BitUnion64(GateDescriptorHigh) Bitfield< 31

	EndBitUnion (GateDescriptorHigh) BitUnion64(GDTR) EndBitUnion(GDTR) BitUnion64(IDTR) EndBitUnion(IDTR) BitUnion64(LDTR) EndBitUnion(LDTR) BitUnion64(TR) EndBitUnion(TR) BitUnion64(LocalApicBase) Bitfield< 51
	Descriptor-Table Registers. More...

const MsrMap	msrMap (msrMapData, msrMapData+msrMapSize)

bool	msrAddrToIndex (MiscRegIndex &regNum, Addr addr)
	Find and return the misc reg corresponding to an MSR address. More...

void	installSegDesc (ThreadContext *tc, SegmentRegIndex seg, SegDescriptor desc, bool longmode)

	BitUnion8 (LegacyPrefixVector) Bitfield<7

	EndBitUnion (LegacyPrefixVector) BitUnion8(ModRM) Bitfield<7

	EndBitUnion (ModRM) BitUnion8(Sib) Bitfield<7

	EndBitUnion (Sib) BitUnion8(Rex) Bitfield< 6 > present

	EndBitUnion (Rex) BitUnion8(Vex2Of3) Bitfield< 7 > r

	EndBitUnion (Vex2Of3) BitUnion8(Vex3Of3) Bitfield< 7 > w

	EndBitUnion (Vex3Of3) BitUnion8(Vex2Of2) Bitfield< 7 > r

	EndBitUnion (Vex2Of2) BitUnion8(VexInfo) Bitfield<6

	EndBitUnion (VexInfo) enum OpcodeType

static const char *	opcodeTypeToStr (OpcodeType type)

	BitUnion8 (Opcode) Bitfield<7

	EndBitUnion (Opcode) BitUnion8(OperatingMode) Bitfield< 3 > mode

	EndBitUnion (OperatingMode) enum X86Mode

static std::ostream &	operator<< (std::ostream &os, const ExtMachInst &emi)

static bool	operator== (const ExtMachInst &emi1, const ExtMachInst &emi2)

uint64_t	getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)

void	initCPU (ThreadContext *tc, int cpuId)

void	startupCPU (ThreadContext *tc, int cpuId)

void	copyMiscRegs (ThreadContext src, ThreadContext dest)

void	copyRegs (ThreadContext src, ThreadContext dest)

void	skipFunction (ThreadContext *tc)

uint64_t	getRFlags (ThreadContext *tc)
	Reconstruct the rflags register from the internal gem5 register state. More...

void	setRFlags (ThreadContext *tc, uint64_t val)
	Set update the rflags register and internal gem5 state. More...

uint8_t	convX87TagsToXTags (uint16_t ftw)
	Convert an x87 tag word to abridged tag format. More...

uint16_t	convX87XTagsToTags (uint8_t ftwx)
	Convert an x87 xtag word to normal tags format. More...

uint16_t	genX87Tags (uint16_t ftw, uint8_t top, int8_t spm)
	Generate and updated x87 tag register after a push/pop operation. More...

double	loadFloat80 (const void *mem)
	Load an 80-bit float from memory and convert it to double. More...

void	storeFloat80 (void *mem, double value)
	Convert and store a double as an 80-bit float. More...

PCState	buildRetPC (const PCState &curPC, const PCState &callPC)

static bool	inUserMode (ThreadContext *tc)

template<class TC >
void	zeroRegisters (TC *tc)
	Function to insure ISA semantics about 0 registers. More...

void	advancePC (PCState &pc, const StaticInstPtr &inst)

uint64_t	getExecutingAsid (ThreadContext *tc)

uint64_t	getDoubleBits (double val)
	Extract the bit string representing a double value. More...

Addr	vtophys (Addr vaddr)

Addr	vtophys (ThreadContext *tc, Addr vaddr)

static Addr	x86IOAddress (const uint32_t port)

static Addr	x86PciConfigAddress (const uint32_t addr)

static Addr	x86LocalAPICAddress (const uint8_t id, const uint16_t addr)

static Addr	x86InterruptAddress (const uint8_t id, const uint16_t addr)

Variables
static const int	vendorStringSize = 13

static const char	vendorString [vendorStringSize] = "M5 Simulator"

static const int	nameStringSize = 48

static const char	nameString [nameStringSize] = "Fake M5 x86_64 CPU"

const uint8_t	CS = CSOverride

const uint8_t	DS = DSOverride

const uint8_t	ES = ESOverride

const uint8_t	FS = FSOverride

const uint8_t	GS = GSOverride

const uint8_t	SS = SSOverride

const uint8_t	OO = OperandSizeOverride

const uint8_t	AO = AddressSizeOverride

const uint8_t	LO = Lock

const uint8_t	RE = Rep

const uint8_t	RN = Repne

const uint8_t	RX = RexPrefix

const uint8_t	V2 = Vex2Prefix

const uint8_t	V3 = Vex3Prefix

const StaticInstPtr	badMicroop

	destination

Bitfield< 15, 8 >	vector

Bitfield< 18, 16 >	deliveryMode

Bitfield< 19 >	destMode

Bitfield< 20 >	level

Bitfield< 21 >	trigger

static const Addr	TriggerIntOffset = 0

const Addr	PageShift = 12

const Addr	PageBytes = ULL(1) << PageShift

const bool	HasUnalignedMemAcc = true

const bool	CurThreadInfoImplemented = false

const int	CurThreadInfoReg = -1

const ExtMachInst NoopMachInst	M5_VAR_USED

const Request::FlagsType M5_VAR_USED	SegmentFlagMask = mask(4)

const int	FlagShift = 4

	longl1

Bitfield< 29, 21 >	longl2

Bitfield< 38, 30 >	longl3

Bitfield< 47, 39 >	longl4

Bitfield< 20, 12 >	pael1

Bitfield< 29, 21 >	pael2

Bitfield< 31, 30 >	pael3

Bitfield< 21, 12 >	norml1

Bitfield< 31, 22 >	norml2

Bitfield< 51, 12 >	base

Bitfield< 11, 9 >	avl

Bitfield< 8 >	g

Bitfield< 7 >	ps

Bitfield< 6 >	d

Bitfield< 5 >	a

Bitfield< 4 >	pcd

Bitfield< 3 >	pwt

Bitfield< 2 >	u

Bitfield< 1 >	w

Bitfield< 0 >	p

EndBitUnion(PageTableEntry) struct TlbEntry Addr	vaddr

unsigned	logBytes

bool	writable

bool	user

bool	uncacheable

bool	global

bool	patBit

bool	noExec

uint64_t	lruSeq

TlbEntryTrie::Handle	trieHandle

const std::vector< uint8_t >	PageTableLayout = {9, 9, 9, 9}
	The size of each level of the page table expressed in base 2 logarithmic values. More...

const int	NumMiscRegs = NUM_MISCREGS

const int	NumIntArchRegs = NUM_INTREGS

const int	NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs

const int	NumCCRegs = NUM_CCREGS

const int	NumFloatRegs

const int	ZeroReg = NUM_INTREGS

const int	StackPointerReg = INTREG_RSP

const int	ReturnAddressReg = 0

const int	ReturnValueReg = INTREG_RAX

const int	FramePointerReg = INTREG_RBP

const int	SyscallPseudoReturnReg = INTREG_RDX

Bitfield< 12 >	deliveryStatus

Bitfield< 19, 18 >	destShorthand

	R

SignedBitfield< 63, 0 >	SR

Bitfield< 31, 0 >	E

SignedBitfield< 31, 0 >	SE

Bitfield< 15, 0 >	X

SignedBitfield< 15, 0 >	SX

Bitfield< 15, 8 >	H

SignedBitfield< 15, 8 >	SH

Bitfield< 7, 0 >	L

SignedBitfield< 7, 0 >	SL

static const IntRegIndex	IntFoldBit = (IntRegIndex)(1 << 6)

const uint32_t	cfofMask = CFBit \| OFBit

const uint32_t	ccFlagMask = PFBit \| AFBit \| ZFBit \| SFBit

Bitfield< 7 >	sf

Bitfield< 6 >	zf

Bitfield< 5 >	ezf

Bitfield< 4 >	af

Bitfield< 3 >	ecf

Bitfield< 2 >	pf

Bitfield< 0 >	cf

Bitfield< 20 >	vip

Bitfield< 19 >	vif

Bitfield< 18 >	ac

Bitfield< 17 >	vm

Bitfield< 16 >	rf

Bitfield< 14 >	nt

Bitfield< 13, 12 >	iopl

Bitfield< 11 >	of

Bitfield< 10 >	df

Bitfield< 9 >	intf

Bitfield< 8 >	tf

Bitfield< 3, 1 >	submode

Bitfield< 5, 4 >	cpl

Bitfield< 6 >	paging

Bitfield< 7 >	prot

Bitfield< 9, 8 >	defOp

Bitfield< 11, 10 >	altOp

Bitfield< 13, 12 >	defAddr

Bitfield< 15, 14 >	altAddr

Bitfield< 17, 16 >	stack

Bitfield< 30 >	cd

Bitfield< 29 >	nw

Bitfield< 18 >	am

Bitfield< 16 >	wp

Bitfield< 5 >	ne

Bitfield< 4 >	et

Bitfield< 3 >	ts

Bitfield< 2 >	em

Bitfield< 1 >	mp

Bitfield< 0 >	pe

	legacy

	longPdtb

Bitfield< 31, 12 >	pdtb

Bitfield< 31, 5 >	paePdtb

Bitfield< 16 >	fsgsbase

Bitfield< 10 >	osxmmexcpt

Bitfield< 9 >	osfxsr

Bitfield< 8 >	pce

Bitfield< 7 >	pge

Bitfield< 6 >	mce

Bitfield< 5 >	pae

Bitfield< 4 >	pse

Bitfield< 3 >	de

Bitfield< 2 >	tsd

Bitfield< 1 >	pvi

Bitfield< 0 >	vme

	tpr

Bitfield< 1 >	b1

Bitfield< 2 >	b2

Bitfield< 3 >	b3

Bitfield< 13 >	bd

Bitfield< 14 >	bs

Bitfield< 15 >	bt

Bitfield< 1 >	g0

Bitfield< 2 >	l1

Bitfield< 3 >	g1

Bitfield< 4 >	l2

Bitfield< 5 >	g2

Bitfield< 6 >	l3

Bitfield< 7 >	g3

Bitfield< 8 >	le

Bitfield< 9 >	ge

Bitfield< 13 >	gd

Bitfield< 17, 16 >	rw0

Bitfield< 19, 18 >	len0

Bitfield< 21, 20 >	rw1

Bitfield< 23, 22 >	len1

Bitfield< 25, 24 >	rw2

Bitfield< 27, 26 >	len2

Bitfield< 29, 28 >	rw3

Bitfield< 31, 30 >	len3

	vcnt

Bitfield< 8 >	fix

Bitfield< 10 >	wc

	targetCS

	targetESP

	targetEIP

	count

Bitfield< 8 >	MCGCP

Bitfield< 1 >	eipv

Bitfield< 2 >	mcip

Bitfield< 1 >	btf

Bitfield< 2 >	pb0

Bitfield< 3 >	pb1

Bitfield< 4 >	pb2

Bitfield< 5 >	pb3

	type

Bitfield< 51, 12 >	physbase

Bitfield< 51, 12 >	physmask

Bitfield< 10 >	fe

Bitfield< 11 >	e

	mcaErrorCode

Bitfield< 31, 16 >	modelSpecificCode

Bitfield< 56, 32 >	otherInfo

Bitfield< 57 >	pcc

Bitfield< 58 >	addrv

Bitfield< 59 >	miscv

Bitfield< 60 >	en

Bitfield< 61 >	uc

Bitfield< 62 >	over

Bitfield< 63 >	val

Bitfield< 8 >	lme

Bitfield< 10 >	lma

Bitfield< 11 >	nxe

Bitfield< 12 >	svme

Bitfield< 14 >	ffxsr

	targetEip

Bitfield< 47, 32 >	syscallCsAndSs

Bitfield< 63, 48 >	sysretCsAndSs

	mask

	eventMask

Bitfield< 15, 8 >	unitMask

Bitfield< 16 >	usr

Bitfield< 17 >	os

Bitfield< 19 >	pc

Bitfield< 20 >	intEn

Bitfield< 23 >	inv

Bitfield< 31, 24 >	counterMask

Bitfield< 19 >	mfdm

Bitfield< 20 >	mvdm

Bitfield< 21 >	tom2

Bitfield< 4 >	rd

	physAddr

Bitfield< 1 >	rInit

Bitfield< 2 >	disA20M

Bitfield< 1 >	enter

Bitfield< 2 >	smiCycle

Bitfield< 3 >	exit

Bitfield< 4 >	rsmCycle

	esi

Bitfield< 15, 3 >	si

Bitfield< 2 >	ti

Bitfield< 1, 0 >	rpl

	baseHigh

Bitfield< 39, 16 >	baseLow

Bitfield< 54 >	b

Bitfield< 53 >	l

Bitfield< 51, 48 >	limitHigh

Bitfield< 15, 0 >	limitLow

Bitfield< 46, 45 >	dpl

Bitfield< 44 >	s

Bitfield< 42 >	c

Bitfield< 41 >	r

Bitfield< 2 >	unusable

Bitfield< 3 >	defaultSize

Bitfield< 4 >	longMode

Bitfield< 6 >	granularity

Bitfield< 7 >	present

Bitfield< 13 >	readable

Bitfield< 14 >	expandDown

Bitfield< 15 >	system

	offsetHigh

Bitfield< 15, 0 >	offsetLow

Bitfield< 31, 16 >	selector

Bitfield< 35, 32 >	IST

	offset

Bitfield< 11 >	enable

Bitfield< 8 >	bsp

const MsrMap::value_type	msrMapData []

static const unsigned	msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0])

const MsrMap	msrMap
	Map between MSR addresses and their corresponding misc registers. More...

const uint64_t	syscallCodeVirtAddr = 0xffff800000000000

const uint64_t	syscallCodePhysAddr = 0x60000

const uint64_t	GDTVirtAddr = 0xffff800000001000

const uint64_t	GDTPhysAddr = 0x61000

const uint64_t	IDTVirtAddr = 0xffff800000002000

const uint64_t	IDTPhysAddr = 0x62000

const uint64_t	TSSVirtAddr = 0xffff800000003000

const uint64_t	TSSPhysAddr = 0x63000

const uint64_t	ISTVirtAddr = 0xffff800000004000

const uint64_t	ISTPhysAddr = 0x64000

const uint64_t	PFHandlerVirtAddr = 0xffff800000005000

const uint64_t	PFHandlerPhysAddr = 0x65000

const uint64_t	MMIORegionVirtAddr = 0xffffc90000000000

const uint64_t	MMIORegionPhysAddr = 0xffff0000

const uint64_t	pageTablePhysAddr = 0x70000

	decodeVal

Bitfield< 7 >	repne

Bitfield< 6 >	rep

Bitfield< 5 >	lock

Bitfield< 4 >	op

Bitfield< 3 >	addr

Bitfield< 2, 0 >	seg

	mod

Bitfield< 5, 3 >	reg

Bitfield< 2, 0 >	rm

	scale

Bitfield< 5, 3 >	index

Bitfield< 1 >	x

Bitfield< 4, 0 >	m

Bitfield< 6, 3 >	v

	top5

Bitfield< 2, 0 >	bottom3

const int	NumMicroIntRegs = 16

const int	NumImplicitIntRegs = 6

const int	NumMMXRegs = 8

const int	NumXMMRegs = 16

const int	NumMicroFpRegs = 8

const int	NumCRegs = 16

const int	NumDRegs = 8

const int	NumSegments = 6

const int	NumSysSegments = 4

const Addr	IntAddrPrefixMask = ULL(0xffffffff00000000)

const Addr	IntAddrPrefixCPUID = ULL(0x100000000)

const Addr	IntAddrPrefixMSR = ULL(0x200000000)

const Addr	IntAddrPrefixIO = ULL(0x300000000)

const Addr	PhysAddrPrefixIO = ULL(0x8000000000000000)

const Addr	PhysAddrPrefixPciConfig = ULL(0xC000000000000000)

const Addr	PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000)

const Addr	PhysAddrPrefixInterrupts = ULL(0xA000000000000000)

const Addr	PhysAddrAPICRangeSize = 1 << 12

Detailed Description

This is exposed globally, independent of the ISA.

Typedef Documentation

typedef std::list<int> X86ISA::ApicList

Definition at line 61 of file intdev.hh.

typedef MultiLevelPageTable<PageTableOps> X86ISA::ArchPageTable

Declaration of architectural page table for x86.

These page tables are stored in system memory and respect x86 specification.

Definition at line 193 of file process.hh.

typedef uint64_t X86ISA::CCReg

Definition at line 93 of file registers.hh.

typedef double X86ISA::FloatReg

Definition at line 98 of file registers.hh.

typedef uint64_t X86ISA::FloatRegBits

Definition at line 99 of file registers.hh.

typedef uint64_t X86ISA::IntReg

Definition at line 92 of file registers.hh.

typedef uint64_t X86ISA::MachInst

Definition at line 54 of file types.hh.

typedef uint64_t X86ISA::MiscReg

Definition at line 94 of file registers.hh.

typedef std::unordered_map<Addr, MiscRegIndex> X86ISA::MsrMap

Definition at line 42 of file msr.hh.

typedef MsrMap::value_type X86ISA::MsrVal

Definition at line 36 of file msr.cc.

typedef uint16_t X86ISA::RegIndex

Definition at line 108 of file registers.hh.

Enumeration Type Documentation

enum X86ISA::ApicRegIndex

Enumerator
APIC_ID
APIC_VERSION
APIC_TASK_PRIORITY
APIC_ARBITRATION_PRIORITY
APIC_PROCESSOR_PRIORITY
APIC_EOI
APIC_LOGICAL_DESTINATION
APIC_DESTINATION_FORMAT
APIC_SPURIOUS_INTERRUPT_VECTOR
APIC_IN_SERVICE_BASE
APIC_TRIGGER_MODE_BASE
APIC_INTERRUPT_REQUEST_BASE
APIC_ERROR_STATUS
APIC_INTERRUPT_COMMAND_LOW
APIC_INTERRUPT_COMMAND_HIGH
APIC_LVT_TIMER
APIC_LVT_THERMAL_SENSOR
APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
APIC_LVT_LINT0
APIC_LVT_LINT1
APIC_LVT_ERROR
APIC_INITIAL_COUNT
APIC_CURRENT_COUNT
APIC_DIVIDE_CONFIGURATION
APIC_INTERNAL_STATE
NUM_APIC_REGS

Definition at line 38 of file apic.hh.

enum X86ISA::CCRegIndex

Enumerator
CCREG_ZAPS
CCREG_CFOF
CCREG_DF
CCREG_ECF
CCREG_EZF
NUM_CCREGS

Definition at line 47 of file ccr.hh.

enum X86ISA::CondFlagBit

Enumerator
CFBit
PFBit
ECFBit
AFBit
EZFBit
ZFBit
SFBit
DFBit
OFBit

Definition at line 55 of file misc.hh.

enum X86ISA::DependenceTags

Enumerator
FP_Reg_Base
CC_Reg_Base
Misc_Reg_Base
Max_Reg_Index

Definition at line 69 of file registers.hh.

enum X86ISA::ExtendedCpuidFunctions

Enumerator
VendorAndLargestExtFunc
FamilyModelSteppingBrandFeatures
NameString1
NameString2
NameString3
L1CacheAndTLB
L2L3CacheAndL2TLB
APMInfo
LongModeAddressSize
NumExtendedCpuidFuncs

Definition at line 43 of file cpuid.cc.

enum X86ISA::FlagBit

Enumerator
CPL0FlagBit
AddrSizeFlagBit
StoreCheck

Definition at line 53 of file ldstflags.hh.

enum X86ISA::FloatRegIndex

Enumerator
FLOATREG_MMX_BASE
FLOATREG_FPR_BASE
FLOATREG_MMX0
FLOATREG_MMX1
FLOATREG_MMX2
FLOATREG_MMX3
FLOATREG_MMX4
FLOATREG_MMX5
FLOATREG_MMX6
FLOATREG_MMX7
FLOATREG_FPR0
FLOATREG_FPR1
FLOATREG_FPR2
FLOATREG_FPR3
FLOATREG_FPR4
FLOATREG_FPR5
FLOATREG_FPR6
FLOATREG_FPR7
FLOATREG_XMM_BASE
FLOATREG_XMM0_LOW
FLOATREG_XMM0_HIGH
FLOATREG_XMM1_LOW
FLOATREG_XMM1_HIGH
FLOATREG_XMM2_LOW
FLOATREG_XMM2_HIGH
FLOATREG_XMM3_LOW
FLOATREG_XMM3_HIGH
FLOATREG_XMM4_LOW
FLOATREG_XMM4_HIGH
FLOATREG_XMM5_LOW
FLOATREG_XMM5_HIGH
FLOATREG_XMM6_LOW
FLOATREG_XMM6_HIGH
FLOATREG_XMM7_LOW
FLOATREG_XMM7_HIGH
FLOATREG_XMM8_LOW
FLOATREG_XMM8_HIGH
FLOATREG_XMM9_LOW
FLOATREG_XMM9_HIGH
FLOATREG_XMM10_LOW
FLOATREG_XMM10_HIGH
FLOATREG_XMM11_LOW
FLOATREG_XMM11_HIGH
FLOATREG_XMM12_LOW
FLOATREG_XMM12_HIGH
FLOATREG_XMM13_LOW
FLOATREG_XMM13_HIGH
FLOATREG_XMM14_LOW
FLOATREG_XMM14_HIGH
FLOATREG_XMM15_LOW
FLOATREG_XMM15_HIGH
FLOATREG_MICROFP_BASE
FLOATREG_MICROFP0
FLOATREG_MICROFP1
FLOATREG_MICROFP2
FLOATREG_MICROFP3
FLOATREG_MICROFP4
FLOATREG_MICROFP5
FLOATREG_MICROFP6
FLOATREG_MICROFP7
NUM_FLOATREGS

Definition at line 48 of file float.hh.

enum X86ISA::MediaFlag

Enumerator
MediaMultHiOp
MediaSignedOp
MediaScalarOp

Definition at line 38 of file micromediaop.hh.

enum X86ISA::MiscRegIndex

Enumerator
MISCREG_CR_BASE
MISCREG_CR0
MISCREG_CR1
MISCREG_CR2
MISCREG_CR3
MISCREG_CR4
MISCREG_CR5
MISCREG_CR6
MISCREG_CR7
MISCREG_CR8
MISCREG_CR9
MISCREG_CR10
MISCREG_CR11
MISCREG_CR12
MISCREG_CR13
MISCREG_CR14
MISCREG_CR15
MISCREG_DR_BASE
MISCREG_DR0
MISCREG_DR1
MISCREG_DR2
MISCREG_DR3
MISCREG_DR4
MISCREG_DR5
MISCREG_DR6
MISCREG_DR7
MISCREG_RFLAGS
MISCREG_M5_REG
MISCREG_TSC
MISCREG_MTRRCAP
MISCREG_SYSENTER_CS
MISCREG_SYSENTER_ESP
MISCREG_SYSENTER_EIP
MISCREG_MCG_CAP
MISCREG_MCG_STATUS
MISCREG_MCG_CTL
MISCREG_DEBUG_CTL_MSR
MISCREG_LAST_BRANCH_FROM_IP
MISCREG_LAST_BRANCH_TO_IP
MISCREG_LAST_EXCEPTION_FROM_IP
MISCREG_LAST_EXCEPTION_TO_IP
MISCREG_MTRR_PHYS_BASE_BASE
MISCREG_MTRR_PHYS_BASE_0
MISCREG_MTRR_PHYS_BASE_1
MISCREG_MTRR_PHYS_BASE_2
MISCREG_MTRR_PHYS_BASE_3
MISCREG_MTRR_PHYS_BASE_4
MISCREG_MTRR_PHYS_BASE_5
MISCREG_MTRR_PHYS_BASE_6
MISCREG_MTRR_PHYS_BASE_7
MISCREG_MTRR_PHYS_BASE_END
MISCREG_MTRR_PHYS_MASK_BASE
MISCREG_MTRR_PHYS_MASK_0
MISCREG_MTRR_PHYS_MASK_1
MISCREG_MTRR_PHYS_MASK_2
MISCREG_MTRR_PHYS_MASK_3
MISCREG_MTRR_PHYS_MASK_4
MISCREG_MTRR_PHYS_MASK_5
MISCREG_MTRR_PHYS_MASK_6
MISCREG_MTRR_PHYS_MASK_7
MISCREG_MTRR_PHYS_MASK_END
MISCREG_MTRR_FIX_64K_00000
MISCREG_MTRR_FIX_16K_80000
MISCREG_MTRR_FIX_16K_A0000
MISCREG_MTRR_FIX_4K_C0000
MISCREG_MTRR_FIX_4K_C8000
MISCREG_MTRR_FIX_4K_D0000
MISCREG_MTRR_FIX_4K_D8000
MISCREG_MTRR_FIX_4K_E0000
MISCREG_MTRR_FIX_4K_E8000
MISCREG_MTRR_FIX_4K_F0000
MISCREG_MTRR_FIX_4K_F8000
MISCREG_PAT
MISCREG_DEF_TYPE
MISCREG_MC_CTL_BASE
MISCREG_MC0_CTL
MISCREG_MC1_CTL
MISCREG_MC2_CTL
MISCREG_MC3_CTL
MISCREG_MC4_CTL
MISCREG_MC5_CTL
MISCREG_MC6_CTL
MISCREG_MC7_CTL
MISCREG_MC_CTL_END
MISCREG_MC_STATUS_BASE
MISCREG_MC0_STATUS
MISCREG_MC1_STATUS
MISCREG_MC2_STATUS
MISCREG_MC3_STATUS
MISCREG_MC4_STATUS
MISCREG_MC5_STATUS
MISCREG_MC6_STATUS
MISCREG_MC7_STATUS
MISCREG_MC_STATUS_END
MISCREG_MC_ADDR_BASE
MISCREG_MC0_ADDR
MISCREG_MC1_ADDR
MISCREG_MC2_ADDR
MISCREG_MC3_ADDR
MISCREG_MC4_ADDR
MISCREG_MC5_ADDR
MISCREG_MC6_ADDR
MISCREG_MC7_ADDR
MISCREG_MC_ADDR_END
MISCREG_MC_MISC_BASE
MISCREG_MC0_MISC
MISCREG_MC1_MISC
MISCREG_MC2_MISC
MISCREG_MC3_MISC
MISCREG_MC4_MISC
MISCREG_MC5_MISC
MISCREG_MC6_MISC
MISCREG_MC7_MISC
MISCREG_MC_MISC_END
MISCREG_EFER
MISCREG_STAR
MISCREG_LSTAR
MISCREG_CSTAR
MISCREG_SF_MASK
MISCREG_KERNEL_GS_BASE
MISCREG_TSC_AUX
MISCREG_PERF_EVT_SEL_BASE
MISCREG_PERF_EVT_SEL0
MISCREG_PERF_EVT_SEL1
MISCREG_PERF_EVT_SEL2
MISCREG_PERF_EVT_SEL3
MISCREG_PERF_EVT_SEL_END
MISCREG_PERF_EVT_CTR_BASE
MISCREG_PERF_EVT_CTR0
MISCREG_PERF_EVT_CTR1
MISCREG_PERF_EVT_CTR2
MISCREG_PERF_EVT_CTR3
MISCREG_PERF_EVT_CTR_END
MISCREG_SYSCFG
MISCREG_IORR_BASE_BASE
MISCREG_IORR_BASE0
MISCREG_IORR_BASE1
MISCREG_IORR_BASE_END
MISCREG_IORR_MASK_BASE
MISCREG_IORR_MASK0
MISCREG_IORR_MASK1
MISCREG_IORR_MASK_END
MISCREG_TOP_MEM
MISCREG_TOP_MEM2
MISCREG_VM_CR
MISCREG_IGNNE
MISCREG_SMM_CTL
MISCREG_VM_HSAVE_PA
MISCREG_SEG_SEL_BASE
MISCREG_ES
MISCREG_CS
MISCREG_SS
MISCREG_DS
MISCREG_FS
MISCREG_GS
MISCREG_HS
MISCREG_TSL
MISCREG_TSG
MISCREG_LS
MISCREG_MS
MISCREG_TR
MISCREG_IDTR
MISCREG_SEG_BASE_BASE
MISCREG_ES_BASE
MISCREG_CS_BASE
MISCREG_SS_BASE
MISCREG_DS_BASE
MISCREG_FS_BASE
MISCREG_GS_BASE
MISCREG_HS_BASE
MISCREG_TSL_BASE
MISCREG_TSG_BASE
MISCREG_LS_BASE
MISCREG_MS_BASE
MISCREG_TR_BASE
MISCREG_IDTR_BASE
MISCREG_SEG_EFF_BASE_BASE
MISCREG_ES_EFF_BASE
MISCREG_CS_EFF_BASE
MISCREG_SS_EFF_BASE
MISCREG_DS_EFF_BASE
MISCREG_FS_EFF_BASE
MISCREG_GS_EFF_BASE
MISCREG_HS_EFF_BASE
MISCREG_TSL_EFF_BASE
MISCREG_TSG_EFF_BASE
MISCREG_LS_EFF_BASE
MISCREG_MS_EFF_BASE
MISCREG_TR_EFF_BASE
MISCREG_IDTR_EFF_BASE
MISCREG_SEG_LIMIT_BASE
MISCREG_ES_LIMIT
MISCREG_CS_LIMIT
MISCREG_SS_LIMIT
MISCREG_DS_LIMIT
MISCREG_FS_LIMIT
MISCREG_GS_LIMIT
MISCREG_HS_LIMIT
MISCREG_TSL_LIMIT
MISCREG_TSG_LIMIT
MISCREG_LS_LIMIT
MISCREG_MS_LIMIT
MISCREG_TR_LIMIT
MISCREG_IDTR_LIMIT
MISCREG_SEG_ATTR_BASE
MISCREG_ES_ATTR
MISCREG_CS_ATTR
MISCREG_SS_ATTR
MISCREG_DS_ATTR
MISCREG_FS_ATTR
MISCREG_GS_ATTR
MISCREG_HS_ATTR
MISCREG_TSL_ATTR
MISCREG_TSG_ATTR
MISCREG_LS_ATTR
MISCREG_MS_ATTR
MISCREG_TR_ATTR
MISCREG_IDTR_ATTR
MISCREG_X87_TOP
MISCREG_MXCSR
MISCREG_FCW
MISCREG_FSW
MISCREG_FTW
MISCREG_FTAG
MISCREG_FISEG
MISCREG_FIOFF
MISCREG_FOSEG
MISCREG_FOOFF
MISCREG_FOP
MISCREG_APIC_BASE
MISCREG_PCI_CONFIG_ADDRESS
NUM_MISCREGS

Definition at line 101 of file misc.hh.

enum X86ISA::Prefixes

Enumerator
NoOverride
ESOverride
CSOverride
SSOverride
DSOverride
FSOverride
GSOverride
RexPrefix
OperandSizeOverride
AddressSizeOverride
Lock
Rep
Repne
Vex2Prefix
Vex3Prefix
XopPrefix

Definition at line 56 of file types.hh.

enum X86ISA::PTEField

Enumerator
PTE_NotPresent
PTE_Supervisor
PTE_ReadOnly
PTE_Uncacheable

Definition at line 161 of file pagetable.hh.

enum X86ISA::RFLAGBit

Enumerator
TFBit
IFBit
NTBit
RFBit
VMBit
ACBit
VIFBit
VIPBit
IDBit

Definition at line 70 of file misc.hh.

enum X86ISA::SegmentRegIndex

Enumerator
SEGMENT_REG_ES
SEGMENT_REG_CS
SEGMENT_REG_SS
SEGMENT_REG_DS
SEGMENT_REG_FS
SEGMENT_REG_GS
SEGMENT_REG_HS
SEGMENT_REG_TSL
SEGMENT_REG_TSG
SEGMENT_REG_LS
SEGMENT_REG_MS
SYS_SEGMENT_REG_TR
SYS_SEGMENT_REG_IDTR
NUM_SEGMENTREGS

Definition at line 45 of file segment.hh.

enum X86ISA::SizeType

Enumerator
NoImm
NI
ByteImm
BY
WordImm
WO
DWordImm
DW
QWordImm
QW
OWordImm
OW
VWordImm
VW
ZWordImm
ZW
Enter
EN
Pointer
PO

Definition at line 169 of file decoder_tables.cc.

enum X86ISA::StandardCpuidFunction

Enumerator
VendorAndLargestStdFunc
FamilyModelStepping
NumStandardCpuidFuncs

Definition at line 37 of file cpuid.cc.

enum X86ISA::X86AuxiliaryVectorTypes

Enumerator
M5_AT_SYSINFO
M5_AT_SYSINFO_EHDR

Definition at line 54 of file process.hh.

enum X86ISA::X86SubMode

Enumerator
SixtyFourBitMode
CompatabilityMode
ProtectedMode
Virtual8086Mode
RealMode

Definition at line 191 of file types.hh.

enum X86ISA::X87StatusBit

Enumerator
IEBit
DEBit
ZEBit
OEBit
UEBit
PEBit
StackFaultBit
ErrSummaryBit
CC0Bit
CC1Bit
CC2Bit
CC3Bit
BusyBit

Definition at line 82 of file misc.hh.

Function Documentation

void X86ISA::advancePC	(	PCState &	pc,
		const StaticInstPtr &	inst
	)

inline

Definition at line 90 of file utility.hh.

References StaticInst::advancePC().

static ApicRegIndex X86ISA::APIC_IN_SERVICE ( int index )

inlinestatic

Definition at line 75 of file apic.hh.

References APIC_IN_SERVICE_BASE, and index.

Referenced by decodeAddr(), and X86ISA::Interrupts::setReg().

static ApicRegIndex X86ISA::APIC_INTERRUPT_REQUEST ( int index )

inlinestatic

Definition at line 87 of file apic.hh.

References APIC_INTERRUPT_REQUEST_BASE, and index.

Referenced by decodeAddr(), and X86ISA::Interrupts::setReg().

static ApicRegIndex X86ISA::APIC_TRIGGER_MODE ( int index )

inlinestatic

Definition at line 81 of file apic.hh.

References APIC_TRIGGER_MODE_BASE, and index.

Referenced by decodeAddr(), X86ISA::Interrupts::readReg(), and X86ISA::Interrupts::setReg().

X86ISA::BitUnion32 ( TriggerIntMessage )

X86ISA::BitUnion32 ( InterruptCommandRegLow )

X86ISA::BitUnion64 ( X86IntReg )

X86ISA::BitUnion64 ( VAddr )

X86ISA::BitUnion64 ( CCFlagBits )

A type to describe the condition code bits of the RFLAGS register, plus two flags, EZF and ECF, which are only visible to microcode.

X86ISA::BitUnion8 ( LegacyPrefixVector )

X86ISA::BitUnion8 ( Opcode )

template<class T >

PacketPtr X86ISA::buildIntRequest	(	const uint8_t	id,
		T	payload,
		Addr	offset,
		Addr	size
	)

Definition at line 92 of file intmessage.hh.

References prepIntRequest(), and Packet::set().

Referenced by buildIntRequest(), and X86ISA::IntDevice::IntMasterPort::sendMessage().

static PacketPtr X86ISA::buildIntRequest	(	const uint8_t	id,
		TriggerIntMessage	payload
	)

inlinestatic

Definition at line 100 of file intmessage.hh.

References buildIntRequest(), and TriggerIntOffset.

static PacketPtr X86ISA::buildIntResponse ( )

inlinestatic

Definition at line 107 of file intmessage.hh.

References panic.

PCState X86ISA::buildRetPC	(	const PCState &	curPC,
		const PCState &	callPC
	)

inline

Definition at line 51 of file utility.hh.

References X86ISA::PCState::uEnd().

uint8_t X86ISA::convX87TagsToXTags ( uint16_t ftw )

Convert an x87 tag word to abridged tag format.

Convert from the x87 tag representation to the tag abridged representation used in the FXSAVE area. The classic format uses 2 bits per stack position to indicate if a position is valid, zero, special, or empty. The abridged format only stores whether a position is empty or not.

Parameters

ftw	Tag word in classic x87 format.

Returns: Tag word in the abridged format.

Definition at line 289 of file utility.cc.

References ArmISA::i.

Referenced by updateKvmStateFPUCommon().

uint16_t X86ISA::convX87XTagsToTags ( uint8_t ftwx )

Convert an x87 xtag word to normal tags format.

Convert from the abridged x87 tag representation used in the FXSAVE area to a full x87 tag. The classic format uses 2 bits per stack position to indicate if a position is valid, zero, special, or empty. The abridged format only stores whether a position is empty or not.

Todo:: Reconstruct the correct state of stack positions instead of just valid/invalid.

Parameters

ftwx	Tag word in the abridged format.

Returns: Tag word in classic x87 format.

Definition at line 314 of file utility.cc.

References ArmISA::i.

Referenced by updateThreadContextFPUCommon().

void X86ISA::copyMiscRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 214 of file utility.cc.

References ThreadContext::getDTBPtr(), ThreadContext::getITBPtr(), ArmISA::i, isValidMiscReg(), MISCREG_TSC, NUM_MISCREGS, ThreadContext::readMiscReg(), ThreadContext::readMiscRegNoEffect(), ThreadContext::setMiscReg(), and ThreadContext::setMiscRegNoEffect().

Referenced by copyRegs().

void X86ISA::copyRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 235 of file utility.cc.

References copyMiscRegs(), ArmISA::i, NumCCRegs, NumFloatRegs, NumIntRegs, ThreadContext::pcState(), ThreadContext::readCCRegFlat(), ThreadContext::readFloatRegBitsFlat(), ThreadContext::readIntRegFlat(), ThreadContext::setCCRegFlat(), ThreadContext::setFloatRegBitsFlat(), and ThreadContext::setIntRegFlat().

ApicRegIndex X86ISA::decodeAddr ( Addr paddr )

bool X86ISA::doCpuid	(	ThreadContext *	tc,
		uint32_t	function,
		uint32_t	index,
		CpuidResult &	result
	)

Definition at line 83 of file cpuid.cc.

References APMInfo, bits(), FamilyModelStepping, FamilyModelSteppingBrandFeatures, L1CacheAndTLB, L2L3CacheAndL2TLB, LongModeAddressSize, nameString, NameString1, NameString2, NameString3, nameStringSize, NumExtendedCpuidFuncs, NumStandardCpuidFuncs, offset, stringToRegister(), VendorAndLargestExtFunc, VendorAndLargestStdFunc, vendorString, vendorStringSize, and warn.

Referenced by X86KvmCPU::updateCPUID().

X86ISA::EndBitUnion ( TriggerIntMessage )

Definition at line 50 of file intmessage.hh.

References ArmISA::mode.

X86ISA::EndBitUnion ( X86IntReg )

Definition at line 61 of file int.hh.

References ArmISA::INTREG_R10, ArmISA::INTREG_R11, ArmISA::INTREG_R12, ArmISA::INTREG_R13, ArmISA::INTREG_R14, ArmISA::INTREG_R15, ArmISA::INTREG_R8, ArmISA::INTREG_R9, ArmISA::INTREG_SP, and ArmISA::NUM_INTREGS.

X86ISA::EndBitUnion ( VAddr )

X86ISA::EndBitUnion ( LegacyPrefixVector )

X86ISA::EndBitUnion ( ModRM )

X86ISA::EndBitUnion ( Sib )

X86ISA::EndBitUnion ( InterruptCommandRegLow )

X86ISA::EndBitUnion ( Rex )

X86ISA::EndBitUnion ( Vex2Of3 )

X86ISA::EndBitUnion ( Vex3Of3 )

X86ISA::EndBitUnion ( Vex2Of2 )

X86ISA::EndBitUnion ( VexInfo )

Definition at line 147 of file types.hh.

X86ISA::EndBitUnion ( Opcode )

X86ISA::EndBitUnion ( OperatingMode )

Definition at line 184 of file types.hh.

X86ISA::EndBitUnion ( CCFlagBits )

RFLAGS.

X86ISA::EndBitUnion ( RFLAGS )

X86ISA::EndBitUnion ( HandyM5Reg )

Control registers.

X86ISA::EndBitUnion ( CR0 )

X86ISA::EndBitUnion ( CR2 )

X86ISA::EndBitUnion ( CR3 )

X86ISA::EndBitUnion ( CR4 )

X86ISA::EndBitUnion ( CR8 )

X86ISA::EndBitUnion ( DR6 )

X86ISA::EndBitUnion ( DR7 )

X86ISA::EndBitUnion ( MTRRcap )

SYSENTER configuration registers.

X86ISA::EndBitUnion ( SysenterCS )

X86ISA::EndBitUnion ( SysenterESP )

X86ISA::EndBitUnion ( SysenterEIP )

Global machine check registers.

X86ISA::EndBitUnion ( McgCap )

X86ISA::EndBitUnion ( McgStatus )

X86ISA::EndBitUnion ( DebugCtlMsr )

X86ISA::EndBitUnion ( MtrrPhysBase )

X86ISA::EndBitUnion ( MtrrPhysMask )

X86ISA::EndBitUnion ( MtrrDefType )

Machine check.

X86ISA::EndBitUnion ( McStatus )

X86ISA::EndBitUnion ( Efer )

X86ISA::EndBitUnion ( Star )

X86ISA::EndBitUnion ( SfMask )

X86ISA::EndBitUnion ( PerfEvtSel )

X86ISA::EndBitUnion ( Syscfg )

X86ISA::EndBitUnion ( IorrBase )

X86ISA::EndBitUnion ( IorrMask )

X86ISA::EndBitUnion ( Tom )

X86ISA::EndBitUnion ( VmCrMsr )

X86ISA::EndBitUnion ( IgnneMsr )

X86ISA::EndBitUnion ( SmmCtlMsr )

Segment Selector.

X86ISA::EndBitUnion ( SegSelector )

Segment Descriptors.

X86ISA::EndBitUnion ( TSShigh )

X86ISA::EndBitUnion ( SegAttr )

X86ISA::EndBitUnion ( GateDescriptor )

Long Mode Gate Descriptor.

X86ISA::EndBitUnion ( GateDescriptorLow )

X86ISA::EndBitUnion ( GateDescriptorHigh )

Descriptor-Table Registers.

Task Register Local APIC Base Register

X86ISA::EndSubBitUnion ( type )

TSS Descriptor (long mode - 128 bits) the lower 64 bits.

TSS Descriptor (long mode - 128 bits) the upper 64 bits.

static FloatRegIndex X86ISA::FLOATREG_FPR ( int index )

inlinestatic

Definition at line 125 of file float.hh.

References FLOATREG_FPR_BASE, and index.

Referenced by FLOATREG_STACK(), updateKvmStateFPUCommon(), and updateThreadContextFPUCommon().

static FloatRegIndex X86ISA::FLOATREG_MICROFP ( int index )

inlinestatic

Definition at line 143 of file float.hh.

References FLOATREG_MICROFP_BASE, and index.

static FloatRegIndex X86ISA::FLOATREG_MMX ( int index )

inlinestatic

Definition at line 119 of file float.hh.

References FLOATREG_MMX_BASE, and index.

Referenced by Trace::X86NativeTrace::ThreadState::update().

static FloatRegIndex X86ISA::FLOATREG_STACK	(	int	index,
		int	top
	)

inlinestatic

Definition at line 149 of file float.hh.

References FLOATREG_FPR().

Referenced by X86ISA::ISA::flattenFloatIndex().

static FloatRegIndex X86ISA::FLOATREG_XMM_HIGH ( int index )

inlinestatic

Definition at line 137 of file float.hh.

References FLOATREG_XMM_BASE.

Referenced by updateKvmStateFPUCommon(), and updateThreadContextFPUCommon().

static FloatRegIndex X86ISA::FLOATREG_XMM_LOW ( int index )

inlinestatic

Definition at line 131 of file float.hh.

References FLOATREG_XMM_BASE, and index.

Referenced by updateKvmStateFPUCommon(), and updateThreadContextFPUCommon().

uint16_t X86ISA::genX87Tags	(	uint16_t	ftw,
		uint8_t	top,
		int8_t	spm
	)

Generate and updated x87 tag register after a push/pop operation.

Note: There is currently no support for setting other tags than valid and invalid. A real x87 will set the tag value to zero or special for some special floating point values.

Parameters

ftw	Current value of the FTW register.
top	Current x87 TOP value.
spm	Stack displacement.

Returns: New value of the FTW register.

Definition at line 335 of file utility.cc.

References ArmISA::i.

uint64_t X86ISA::getArgument	(	ThreadContext *	tc,
		int &	number,
		uint16_t	size,
		bool	fp
	)

Definition at line 53 of file utility.cc.

References ArmISA::INTREG_R8, ArmISA::INTREG_R9, panic, and ThreadContext::readIntReg().

uint64_t X86ISA::getDoubleBits ( double val )

inline

Extract the bit string representing a double value.

Definition at line 134 of file utility.hh.

uint64_t X86ISA::getExecutingAsid ( ThreadContext * tc )

inline

Definition at line 96 of file utility.hh.

static void X86ISA::getMem	(	PacketPtr	pkt,
		uint64_t &	mem,
		unsigned	dataSize,
		Trace::InstRecord *	traceData
	)

static

Definition at line 54 of file memhelpers.hh.

References Packet::get(), panic, and Trace::InstRecord::setData().

template<size_t N>

void X86ISA::getMem	(	PacketPtr	pkt,
		std::array< uint64_t, N > &	mem,
		unsigned	dataSize,
		Trace::InstRecord *	traceData
	)

Definition at line 80 of file memhelpers.hh.

References Packet::getConstPtr(), BigEndianGuest::gtoh(), ArmISA::i, and Trace::InstRecord::setData().

uint64_t X86ISA::getRFlags ( ThreadContext * tc )

Reconstruct the rflags register from the internal gem5 register state.

gem5 stores rflags in several different registers to avoid pipeline dependencies. In order to get the true rflags value, we can't simply read the value of MISCREG_RFLAGS. Instead, we need to read out various state from microcode registers and merge that with MISCREG_RFLAGS.

Parameters

tc	Thread context to read rflags from.

Returns: rflags as seen by the guest.

Definition at line 257 of file utility.cc.

References CCREG_CFOF, CCREG_DF, CCREG_ZAPS, MISCREG_RFLAGS, ThreadContext::readCCReg(), and ThreadContext::readMiscRegNoEffect().

Referenced by X86KvmCPU::updateKvmStateRegs().

Cycles X86ISA::handleIprRead	(	ThreadContext *	xc,
		Packet *	pkt
	)

inline

Definition at line 58 of file mmapped_ipr.hh.

References data, Packet::getAddr(), Packet::getSize(), GenericISA::handleGenericIprRead(), BigEndianGuest::htog(), index, GenericISA::isGenericIprAccess(), mask, offset, ThreadContext::readMiscReg(), and Packet::setData().

Cycles X86ISA::handleIprWrite	(	ThreadContext *	xc,
		Packet *	pkt
	)

inline

Definition at line 75 of file mmapped_ipr.hh.

References data, Packet::getAddr(), Packet::getSize(), BigEndianGuest::gtoh(), GenericISA::handleGenericIprWrite(), BigEndianGuest::htog(), index, GenericISA::isGenericIprAccess(), mask, offset, ThreadContext::readMiscRegNoEffect(), ThreadContext::setMiscReg(), and Packet::writeData().

template<class XC >

void X86ISA::handleLockedRead	(	XC *	xc,
		Request *	req
	)

inline

Definition at line 53 of file locked_mem.hh.

template<class XC >

void X86ISA::handleLockedSnoop	(	XC *	xc,
		PacketPtr	pkt,
		Addr	cacheBlockMask
	)

inline

Definition at line 47 of file locked_mem.hh.

template<class XC >

void X86ISA::handleLockedSnoopHit ( XC * xc )

inline

Definition at line 66 of file locked_mem.hh.

template<class XC >

bool X86ISA::handleLockedWrite	(	XC *	xc,
		Request *	req,
		Addr	cacheBlockMask
	)

inline

Definition at line 59 of file locked_mem.hh.

void X86ISA::initCPU	(	ThreadContext *	tc,
		int	cpuId
	)

Definition at line 74 of file utility.cc.

template<class XC >

Fault X86ISA::initiateMemRead	(	XC *	xc,
		Trace::InstRecord *	traceData,
		Addr	addr,
		unsigned	dataSize,
		Request::Flags	flags
	)

Initiate a read from memory in timing mode.

Definition at line 47 of file memhelpers.hh.

void X86ISA::installSegDesc	(	ThreadContext *	tc,
		SegmentRegIndex	seg,
		SegDescriptor	desc,
		bool	longmode
	)

Definition at line 61 of file system.cc.

References ArmISA::attr, base, MISCREG_SEG_ATTR(), MISCREG_SEG_BASE(), MISCREG_SEG_EFF_BASE(), MISCREG_SEG_LIMIT(), SEGMENT_REG_FS, SEGMENT_REG_GS, SEGMENT_REG_TSL, ThreadContext::setMiscReg(), and SYS_SEGMENT_REG_TR.

Referenced by X86System::initState(), and X86ISA::X86_64Process::initState().

static IntRegIndex X86ISA::INTREG_FOLDED	(	int	index,
		int	foldBit
	)

inlinestatic

Definition at line 168 of file int.hh.

References index.

static IntRegIndex X86ISA::INTREG_IMPLICIT ( int index )

inlinestatic

Definition at line 162 of file int.hh.

References index, ArmISA::NUM_INTREGS, and NumMicroIntRegs.

Referenced by initCPU().

static IntRegIndex X86ISA::INTREG_MICRO ( int index )

inlinestatic

Definition at line 156 of file int.hh.

References index, and ArmISA::NUM_INTREGS.

Referenced by initCPU(), and X86ISA::X86FaultBase::invoke().

static bool X86ISA::inUserMode ( ThreadContext * tc )

inlinestatic

Definition at line 62 of file utility.hh.

References FullSystem, MISCREG_M5_REG, and ThreadContext::readMiscRegNoEffect().

static bool X86ISA::isValidMiscReg ( int index )

inlinestatic

Definition at line 403 of file misc.hh.

References MISCREG_CR0, MISCREG_CR1, MISCREG_CR15, MISCREG_CR4, MISCREG_CR8, and NUM_MISCREGS.

Referenced by copyMiscRegs(), X86ISA::ISA::readMiscRegNoEffect(), and X86ISA::ISA::setMiscRegNoEffect().

double X86ISA::loadFloat80 ( const void * mem )

Load an 80-bit float from memory and convert it to double.

Parameters

mem	Pointer to an 80-bit float.

Returns: double representation of the 80-bit float.

Definition at line 355 of file utility.cc.

Referenced by dumpFpuCommon(), and updateThreadContextFPUCommon().

void X86ISA::m5PageFault ( ThreadContext * tc )

Definition at line 65 of file pseudo_inst.cc.

References DPRINTF, Process::fixupStackFault(), ThreadContext::getMemProxy(), ThreadContext::getProcessPtr(), MipsISA::is, ISTVirtAddr, MISCREG_CR2, p, PageBytes, panic, SETranslatingPortProxy::readBlob(), ThreadContext::readMiscReg(), and size().

Referenced by PseudoInst::pseudoInst().

void X86ISA::m5Syscall ( ThreadContext * tc )

Definition at line 48 of file pseudo_inst.cc.

References DPRINTF, MISCREG_RFLAGS, panic, ThreadContext::readIntReg(), ThreadContext::readMiscReg(), ThreadContext::setMiscReg(), and ThreadContext::syscall().

Referenced by PseudoInst::pseudoInst().

static MiscRegIndex X86ISA::MISCREG_CR ( int index )

inlinestatic

Definition at line 412 of file misc.hh.

References index, MISCREG_CR_BASE, and NumCRegs.

static MiscRegIndex X86ISA::MISCREG_DR ( int index )

inlinestatic

Definition at line 419 of file misc.hh.

References index, MISCREG_DR_BASE, and NumDRegs.

static MiscRegIndex X86ISA::MISCREG_IORR_BASE ( int index )

inlinestatic

Definition at line 490 of file misc.hh.

References index, MISCREG_IORR_BASE_BASE, and MISCREG_IORR_BASE_END.

static MiscRegIndex X86ISA::MISCREG_IORR_MASK ( int index )

inlinestatic

Definition at line 498 of file misc.hh.

References index, MISCREG_IORR_MASK_BASE, and MISCREG_IORR_MASK_END.

static MiscRegIndex X86ISA::MISCREG_MC_ADDR ( int index )

inlinestatic

Definition at line 458 of file misc.hh.

References index, MISCREG_MC_ADDR_BASE, and MISCREG_MC_ADDR_END.

Referenced by initCPU().

static MiscRegIndex X86ISA::MISCREG_MC_CTL ( int index )

inlinestatic

Definition at line 442 of file misc.hh.

References index, MISCREG_MC_CTL_BASE, and MISCREG_MC_CTL_END.

Referenced by initCPU().

static MiscRegIndex X86ISA::MISCREG_MC_MISC ( int index )

inlinestatic

Definition at line 466 of file misc.hh.

References index, MISCREG_MC_MISC_BASE, and MISCREG_MC_MISC_END.

Referenced by initCPU().

static MiscRegIndex X86ISA::MISCREG_MC_STATUS ( int index )

inlinestatic

Definition at line 450 of file misc.hh.

References index, MISCREG_MC_STATUS_BASE, and MISCREG_MC_STATUS_END.

Referenced by initCPU().

static MiscRegIndex X86ISA::MISCREG_MTRR_PHYS_BASE ( int index )

inlinestatic

Definition at line 426 of file misc.hh.

References index, MISCREG_MTRR_PHYS_BASE_BASE, and MISCREG_MTRR_PHYS_BASE_END.

Referenced by initCPU().

static MiscRegIndex X86ISA::MISCREG_MTRR_PHYS_MASK ( int index )

inlinestatic

Definition at line 434 of file misc.hh.

References index, MISCREG_MTRR_PHYS_MASK_BASE, and MISCREG_MTRR_PHYS_MASK_END.

Referenced by initCPU().

static MiscRegIndex X86ISA::MISCREG_PERF_EVT_CTR ( int index )

inlinestatic

Definition at line 482 of file misc.hh.

References index, MISCREG_PERF_EVT_CTR_BASE, and MISCREG_PERF_EVT_CTR_END.

Referenced by initCPU().

static MiscRegIndex X86ISA::MISCREG_PERF_EVT_SEL ( int index )

inlinestatic

Definition at line 474 of file misc.hh.

References index, MISCREG_PERF_EVT_SEL_BASE, and MISCREG_PERF_EVT_SEL_END.

Referenced by initCPU().

static MiscRegIndex X86ISA::MISCREG_SEG_ATTR ( int index )

inlinestatic

Definition at line 534 of file misc.hh.

References index, MISCREG_SEG_ATTR_BASE, and NUM_SEGMENTREGS.

Referenced by X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), setContextSegment(), setKvmSegmentReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

static MiscRegIndex X86ISA::MISCREG_SEG_BASE ( int index )

inlinestatic

Definition at line 513 of file misc.hh.

References index, MISCREG_SEG_BASE_BASE, and NUM_SEGMENTREGS.

Referenced by X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), setContextSegment(), setKvmDTableReg(), setKvmSegmentReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

static MiscRegIndex X86ISA::MISCREG_SEG_EFF_BASE ( int index )

inlinestatic

Definition at line 520 of file misc.hh.

References index, MISCREG_SEG_EFF_BASE_BASE, and NUM_SEGMENTREGS.

Referenced by X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), and X86ISA::ISA::setMiscReg().

static MiscRegIndex X86ISA::MISCREG_SEG_LIMIT ( int index )

inlinestatic

Definition at line 527 of file misc.hh.

References index, MISCREG_SEG_LIMIT_BASE, and NUM_SEGMENTREGS.

Referenced by X86ISA::I386Process::initState(), installSegDesc(), X86ISA::InitInterrupt::invoke(), setContextSegment(), setKvmDTableReg(), setKvmSegmentReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

static MiscRegIndex X86ISA::MISCREG_SEG_SEL ( int index )

inlinestatic

Definition at line 506 of file misc.hh.

References index, MISCREG_SEG_SEL_BASE, and NUM_SEGMENTREGS.

Referenced by X86ISA::I386Process::initState(), X86ISA::InitInterrupt::invoke(), setContextSegment(), setKvmSegmentReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

bool X86ISA::msrAddrToIndex	(	MiscRegIndex &	regNum,
		Addr	addr
	)

Find and return the misc reg corresponding to an MSR address.

Look for an MSR (addr) in msrMap and return the corresponding misc reg in regNum. The value of regNum is undefined if the MSR was not found.

Parameters

regNum	misc reg index (out).
addr	MSR address

Returns: True if the MSR was found, false otherwise.

Definition at line 149 of file msr.cc.

References msrMap.

Referenced by X86ISA::TLB::translateInt().

const MsrMap X86ISA::msrMap	(	msrMapData	,
		msrMapData+	msrMapSize
	)

static const char* X86ISA::opcodeTypeToStr ( OpcodeType type )

inlinestatic

Definition at line 158 of file types.hh.

Referenced by operator<<().

static std::ostream& X86ISA::operator<<	(	std::ostream &	os,
		const ExtMachInst &	emi
	)

inlinestatic

Definition at line 235 of file types.hh.

References ccprintf(), X86ISA::ExtMachInst::displacement, X86ISA::ExtMachInst::dispSize, X86ISA::ExtMachInst::immediate, X86ISA::ExtMachInst::legacy, X86ISA::ExtMachInst::modRM, X86ISA::ExtMachInst::op, X86ISA::ExtMachInst::opcode, opcodeTypeToStr(), os, X86ISA::ExtMachInst::rex, X86ISA::ExtMachInst::sib, X86ISA::ExtMachInst::type, and X86ISA::ExtMachInst::vex.

static bool X86ISA::operator==	(	const ExtMachInst &	emi1,
		const ExtMachInst &	emi2
	)

inlinestatic

Definition at line 252 of file types.hh.

References X86ISA::ExtMachInst::addrSize, X86ISA::ExtMachInst::displacement, X86ISA::ExtMachInst::dispSize, X86ISA::ExtMachInst::immediate, X86ISA::ExtMachInst::legacy, X86ISA::ExtMachInst::mode, X86ISA::ExtMachInst::modRM, X86ISA::ExtMachInst::op, X86ISA::ExtMachInst::opcode, X86ISA::ExtMachInst::opSize, X86ISA::ExtMachInst::rex, X86ISA::ExtMachInst::sib, X86ISA::ExtMachInst::stackSize, X86ISA::ExtMachInst::type, and X86ISA::ExtMachInst::vex.

Referenced by ArmISA::EndBitUnion().

Addr X86ISA::pageStart ( )

Definition at line 140 of file pagetable.hh.

static PacketPtr X86ISA::prepIntRequest	(	const uint8_t	id,
		Addr	offset,
		Addr	size
	)

inlinestatic

Definition at line 80 of file intmessage.hh.

References Packet::allocate(), Request::intMasterId, MemCmd::MessageReq, Request::UNCACHEABLE, and x86InterruptAddress().

Referenced by buildIntRequest().

template<class XC >

Fault X86ISA::readMemAtomic	(	XC *	xc,
		Trace::InstRecord *	traceData,
		Addr	addr,
		uint64_t &	mem,
		unsigned	dataSize,
		Request::Flags	flags
	)

Definition at line 102 of file memhelpers.hh.

References BigEndianGuest::gtoh(), NoFault, and Trace::InstRecord::setData().

template<class XC , size_t N>

Fault X86ISA::readMemAtomic	(	XC *	xc,
		Trace::InstRecord *	traceData,
		Addr	addr,
		std::array< uint64_t, N > &	mem,
		unsigned	dataSize,
		unsigned	flags
	)

Definition at line 120 of file memhelpers.hh.

References BigEndianGuest::gtoh(), ArmISA::i, NoFault, and Trace::InstRecord::setData().

void X86ISA::serialize ( CheckpointOut & cp ) const

override

Referenced by ArmISA::EndBitUnion(), MinorCPU::serialize(), and Serializable::serializeSection().

void X86ISA::setRFlags	(	ThreadContext *	tc,
		uint64_t	val
	)

Set update the rflags register and internal gem5 state.

Note: This function does not update MISCREG_M5_REG. You might need to update this register by writing anything to MISCREG_M5_REG with side-effects.

See Also: X86ISA::getRFlags()

Parameters

tc	Thread context to update
val	New rflags value to store in TC

Definition at line 273 of file utility.cc.

References ccFlagMask, CCREG_CFOF, CCREG_DF, CCREG_ECF, CCREG_EZF, CCREG_ZAPS, cfofMask, DFBit, MISCREG_RFLAGS, ThreadContext::setCCReg(), and ThreadContext::setMiscReg().

Referenced by X86KvmCPU::updateThreadContextRegs().

int X86ISA::size ( )

Definition at line 146 of file pagetable.hh.

Referenced by MemChecker::abortWrite(), FlashDevice::accessDevice(), FUPool::FUIdxQueue::addFU(), StorageSpace::addSymbol(), CacheRecorder::aggregateRecords(), Arguments::Data::alloc(), KvmVM::allocMemSlot(), CopyEngine::CopyEngineChannel::anQ(), RiscvProcess::argsInit(), X86ISA::X86Process::argsInit(), arrayParamIn(), arrayParamOut(), BlockBloomFilter::BlockBloomFilter(), brigNext(), BrigObject::BrigObject(), DefaultFetch< Impl >::buildInst(), BulkBloomFilter::BulkBloomFilter(), RubyTester::checkForDeadlock(), Packet::checkFunctional(), MuxingKvmGic::clearBankedDistRange(), MuxingKvmGic::clearDistRange(), TsunamiCChip::clearDRIR(), MaltaCChip::clearIntr(), KvmVM::coalesceMMIO(), MemChecker::completeRead(), MemChecker::completeWrite(), FunctionProfile::consume(), MuxingKvmGic::copyBankedDistRange(), MuxingKvmGic::copyDistRange(), MuxingKvmGic::copyGicState(), PacketFifo::copyout(), Linux::ThreadInfo::curTaskName(), X86ISA::Decoder::decode(), Shader::doFunctionalAccess(), MemDepUnit< MemDepPred, Impl >::dumpLists(), InstructionQueue< Impl >::dumpLists(), IdeController::EndBitUnion(), ArmISA::EndBitUnion(), LSQUnit< Impl >::executeStore(), Topology::extend_shortest_path(), LTAGE::F(), DefaultFetch< Impl >::fetch(), IGbE::DescCache< T >::fetchComplete(), ArmISA::TableWalker::fetchDescriptor(), IGbE::DescCache< T >::fetchDescriptors(), DefaultFetch< Impl >::finishTranslation(), flit::flit(), getcwdFunc(), FUPool::FUIdxQueue::getFU(), System::getMasterId(), BaseArmKvmCPU::getRegList(), BrigObject::getSectionOffset(), X86ISA::SMBios::SMBiosStructure::getStringLength(), H3BloomFilter::H3BloomFilter(), AbstractController::init(), FetchUnit::initiateFetch(), BaseDynInst< Impl >::initiateMemRead(), LinuxArmSystem::initState(), SubBlock::internalMergeFrom(), SubBlock::internalMergeTo(), VIPERCoalescer::invL1(), VIPERCoalescer::invwbL1(), ClDriver::ioctl(), m5PageFault(), main(), UFSHostDevice::manageWriteTransfer(), PortProxy::memsetBlob(), SimplePoolManager::minAllocatedElements(), Minor::LSQ::StoreBuffer::minorTrace(), mmapImpl(), network_message_to_size(), VirtIOConsole::TermTransQueue::onNotifyDescriptor(), PerfectSwitch::operateVnet(), Stats::DistPrint::operator()(), Terminal::out(), IGbE::TxDescCache::pktComplete(), TsunamiCChip::postDRIR(), MaltaCChip::postIntr(), TsunamiCChip::postRTC(), BPredUnit::predict(), Stats::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy >::prepare(), Sinic::Device::prepareIO(), DataBlock::print(), print_backtrace(), Net::IpPtr::pstart(), Net::Ip6Ptr::pstart(), Net::TcpPtr::pstart(), Net::UdpPtr::pstart(), Minor::LSQ::pushRequest(), AbstractController::queueMemoryWritePartial(), RangeAddrMapper::RangeAddrMapper(), PciVirtIO::read(), NoMaliGpu::read(), VirtIOBlock::read(), ProtoInputStream::read(), CopyEngine::read(), GenericPciHost::read(), GenericTimerMem::read(), PerfKvmCounter::read(), TraceCPU::ElasticDataGen::InputStream::read(), VirtIODeviceBase::readConfigBlob(), AtomicSimpleCPU::readMem(), CheckerCPU::readMem(), StubSlavePort::recvAtomic(), MemCheckerMonitor::recvFunctional(), MemCheckerMonitor::recvFunctionalSnoop(), MemCheckerMonitor::recvTimingReq(), MemCheckerMonitor::recvTimingResp(), Sinic::regValid(), LdsState::releaseSpace(), DefaultRename< Impl >::removeFromHistory(), DefaultRename< Impl >::renameDestRegs(), UFSHostDevice::requestHandler(), LdsState::reserveSpace(), Sinic::Device::reset(), Stats::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy >::reset(), MemChecker::reset(), AbstractController::resetStats(), Sinic::Device::rxKick(), UFSHostDevice::SCSIResume(), ComputeUnit::sendRequest(), AlphaISA::TLB::serialize(), Network::setFromNetQueue(), Request::setPhys(), Set::setSize(), Network::setToNetQueue(), ArmISA::Stage2MMU::Stage2Translation::setVirt(), Request::setVirt(), DefaultDecode< Impl >::skidInsert(), DefaultIEW< Impl >::skidInsert(), DefaultRename< Impl >::skidInsert(), NetDest::smallestElement(), BPredUnit::squash(), IdeDisk::startCommand(), MemChecker::startRead(), MemChecker::startWrite(), SubBlock::SubBlock(), FullO3CPU< Impl >::totalInsts(), FullO3CPU< Impl >::totalOps(), AlphaISA::StackTrace::trace(), UFSHostDevice::transferDone(), TrafficGen::transition(), IGbE::txStateMachine(), SymbolTable::unserialize(), AlphaISA::TLB::unserialize(), X86ISA::Decoder::updateNPC(), TLBCoalescer::updatePhysAddresses(), Stats::Text::visit(), ArmISA::VldMultOp::VldMultOp(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VstMultOp::VstMultOp(), ArmISA::VstSingleOp::VstSingleOp(), VIPERCoalescer::wbL1(), PciVirtIO::write(), NoMaliGpu::write(), VirtIOBlock::write(), CopyEngine::write(), GenericTimerMem::write(), LSQUnit< Impl >::write(), LSQUnit< Impl >::writebackStores(), VirtIODeviceBase::writeConfigBlob(), UFSHostDevice::writeDevice(), TraceCPU::ElasticDataGen::GraphNode::writeElementAsTrace(), AtomicSimpleCPU::writeMem(), TimingSimpleCPU::writeMem(), BaseDynInst< Impl >::writeMem(), CheckerCPU::writeMem(), X86ISA::SMBios::BiosInformation::writeOut(), X86ISA::SMBios::SMBiosTable::writeOut(), X86ISA::E820Table::writeTo(), and CheckTable::~CheckTable().

void X86ISA::skipFunction ( ThreadContext * tc )

Definition at line 251 of file utility.cc.

References panic.

void X86ISA::startupCPU	(	ThreadContext *	tc,
		int	cpuId
	)

Definition at line 201 of file utility.cc.

References ThreadContext::activate(), FullSystem, and ThreadContext::suspend().

void X86ISA::storeFloat80	(	void *	mem,
		double	value
	)

Convert and store a double as an 80-bit float.

Parameters

mem	Pointer to destination for the 80-bit float.
value	Double precision float to store.

Definition at line 364 of file utility.cc.

Referenced by updateKvmStateFPUCommon().

uint64_t X86ISA::stringToRegister ( const char * str )

Definition at line 72 of file cpuid.cc.

References reg.

Referenced by doCpuid().

X86ISA::SubBitUnion	(	type	,
		43	,
		40
	)

X86ISA::TlbEntry	(	Addr	asn,
		Addr	_vaddr,
		Addr	_paddr,
		bool	uncacheable,
		bool	read_only
	)

Referenced by X86ISA::RemoteGDB::acc(), X86ISA::TLB::demapPage(), AlphaISA::TLB::flushAll(), X86ISA::TLB::insert(), X86ISA::TLB::lookup(), MultiLevelPageTable< ISAOps >::lookup(), MultiLevelPageTable< ISAOps >::map(), FuncPageTable::map(), X86ISA::GpuTLB::CpuSidePort::recvFunctional(), MultiLevelPageTable< ISAOps >::remap(), X86ISA::TLB::translate(), PageTableBase::translate(), X86ISA::GpuTLB::translationReturn(), X86ISA::TLB::unserialize(), and FuncPageTable::unserialize().

X86ISA::TlbEntry ( )

void X86ISA::unserialize ( CheckpointIn & cp )

override

Referenced by ArmISA::EndBitUnion(), MinorCPU::unserialize(), and Serializable::unserializeSection().

void X86ISA::updateVaddr ( Addr new_vaddr )

Definition at line 135 of file pagetable.hh.

Addr X86ISA::vtophys ( Addr vaddr )

inline

Definition at line 55 of file vtophys.cc.

References fatal, and panic.

Addr X86ISA::vtophys	(	ThreadContext *	tc,
		Addr	vaddr
	)

inline

Definition at line 61 of file vtophys.cc.

References addr, DPRINTF, fatal, ThreadContext::getDTBPtr(), logBytes, ArmISA::mask, NoFault, panic, BaseTLB::Read, X86ISA::Walker::startFunctional(), try_translate(), and MipsISA::vaddr.

template<class XC >

Fault X86ISA::writeMemAtomic	(	XC *	xc,
		Trace::InstRecord *	traceData,
		uint64_t	mem,
		unsigned	dataSize,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 179 of file memhelpers.hh.

References BigEndianGuest::gtoh(), BigEndianGuest::htog(), NoFault, and Trace::InstRecord::setData().

template<class XC , size_t N>

Fault X86ISA::writeMemAtomic	(	XC *	xc,
		Trace::InstRecord *	traceData,
		std::array< uint64_t, N > &	mem,
		unsigned	dataSize,
		Addr	addr,
		unsigned	flags,
		uint64_t *	res
	)

Definition at line 197 of file memhelpers.hh.

References BigEndianGuest::gtoh(), BigEndianGuest::htog(), ArmISA::i, NoFault, and Trace::InstRecord::setData().

template<class XC >

Fault X86ISA::writeMemTiming	(	XC *	xc,
		Trace::InstRecord *	traceData,
		uint64_t	mem,
		unsigned	dataSize,
		Addr	addr,
		Request::Flags	flags,
		uint64_t *	res
	)

Definition at line 144 of file memhelpers.hh.

References BigEndianGuest::htog(), and Trace::InstRecord::setData().

template<class XC , size_t N>

Fault X86ISA::writeMemTiming	(	XC *	xc,
		Trace::InstRecord *	traceData,
		std::array< uint64_t, N > &	mem,
		unsigned	dataSize,
		Addr	addr,
		unsigned	flags,
		uint64_t *	res
	)

Definition at line 157 of file memhelpers.hh.

References BigEndianGuest::htog(), ArmISA::i, and Trace::InstRecord::setData().

static Addr X86ISA::x86InterruptAddress	(	const uint8_t	id,
		const uint16_t	addr
	)

inlinestatic

Definition at line 100 of file x86_traits.hh.

References PhysAddrAPICRangeSize, and PhysAddrPrefixInterrupts.

Referenced by X86ISA::I82094AA::getIntAddrRange(), X86ISA::Interrupts::getIntAddrRange(), prepIntRequest(), and X86ISA::Interrupts::recvMessage().

static Addr X86ISA::x86IOAddress ( const uint32_t port )

inlinestatic

Definition at line 81 of file x86_traits.hh.

References PhysAddrPrefixIO.

Referenced by X86KvmCPU::handleKvmExitIO().

static Addr X86ISA::x86LocalAPICAddress	(	const uint8_t	id,
		const uint16_t	addr
	)

inlinestatic

Definition at line 93 of file x86_traits.hh.

References addr, and PhysAddrPrefixLocalAPIC.

Referenced by X86ISA::TLB::finalizePhysical(), X86ISA::Interrupts::setCPU(), and X86ISA::GpuTLB::translate().

static Addr X86ISA::x86PciConfigAddress ( const uint32_t addr )

inlinestatic

Definition at line 87 of file x86_traits.hh.

References addr, and PhysAddrPrefixPciConfig.

Referenced by X86KvmCPU::handleKvmExitIO().

template<class TC >

void X86ISA::zeroRegisters ( TC * tc )

Function to insure ISA semantics about 0 registers.

Parameters

tc	The thread context.

Variable Documentation

Bitfield< 40 > X86ISA::a

Definition at line 90 of file pagetable.hh.

Referenced by AlphaISA::VAddr::operator=(), and PowerISA::VAddr::operator=().

Bitfield<18> X86ISA::ac

Definition at line 562 of file misc.hh.

Referenced by LinuxArmSystem::initState().

Bitfield<3> X86ISA::addr

Definition at line 81 of file types.hh.

Referenced by X86ISA::PageFault::describe(), X86ISA::PageTableOps::getOffsets(), X86ISA::PageFault::invoke(), X86ISA::ProcessInfo::ProcessInfo(), X86ISA::I8042::read(), X86ISA::TLB::setConfigAddress(), X86ISA::GpuTLB::setConfigAddress(), X86ISA::IntelMP::FloatingPointer::setTableAddr(), X86ISA::SMBios::SMBiosTable::setTableAddr(), X86ISA::Walker::WalkerState::setupWalk(), X86ISA::I8042::write(), x86LocalAPICAddress(), and x86PciConfigAddress().

Bitfield<58> X86ISA::addrv

Definition at line 765 of file misc.hh.

Bitfield< 4 > X86ISA::af

Definition at line 549 of file misc.hh.

Bitfield<15, 14> X86ISA::altAddr

Definition at line 587 of file misc.hh.

Bitfield<11, 10> X86ISA::altOp

Definition at line 585 of file misc.hh.

Bitfield<18> X86ISA::am

Definition at line 598 of file misc.hh.

const uint8_t X86ISA::AO = AddressSizeOverride

Definition at line 53 of file decoder_tables.cc.

Bitfield< 5 > X86ISA::avl

Definition at line 86 of file pagetable.hh.

Bitfield< 5 > X86ISA::b

Definition at line 875 of file misc.hh.

Bitfield<1> X86ISA::b1

Definition at line 648 of file misc.hh.

Referenced by ArmISA::mul62x62().

Bitfield<2> X86ISA::b2

Definition at line 649 of file misc.hh.

Bitfield<3> X86ISA::b3

Definition at line 650 of file misc.hh.

const StaticInstPtr X86ISA::badMicroop

Initial value:

=
    new X86ISAInst::MicroPanic(NoopMachInst, "BAD",
        StaticInst::IsMicroop | StaticInst::IsLastMicroop,
        "Invalid microop!", 0)

Definition at line 51 of file badmicroop.cc.

Referenced by X86ISAInst::MicrocodeRom::fetchMicroop(), and X86ISA::MacroopBase::fetchMicroop().

Bitfield< 2, 0 > X86ISA::base

Definition at line 85 of file pagetable.hh.

Referenced by dumpDmesgEntry(), IdeController::EndBitUnion(), ArmISA::SysDC64::generateDisassembly(), ArmISA::Swap::generateDisassembly(), ArmISA::RfeOp::generateDisassembly(), ArmISA::MemoryDImm64::generateDisassembly(), ArmISA::MemoryDImmEx64::generateDisassembly(), ArmISA::MemoryEx64::generateDisassembly(), ArmISA::ArmFault::getVector(), X86System::initState(), installSegDesc(), Stats::VectorPrint::operator()(), Stats::DistPrint::operator()(), Stats::SparseHistPrint::operator()(), ArmISA::Memory::printInst(), ArmISA::ArmStaticInst::shift_rm_rs(), ArmISA::ArmStaticInst::shiftReg64(), ArmISA::Memory64::startDisassembly(), MipsISA::ProcessInfo::task(), X86ISA::ProcessInfo::task(), AlphaISA::ProcessInfo::task(), ArmISA::ProcessInfo::task(), MemTest::tick(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), and X86ISA::SMBios::SMBiosTable::writeOut().

X86ISA::baseHigh

Definition at line 871 of file misc.hh.

Bitfield< 39, 16 > X86ISA::baseLow

Definition at line 872 of file misc.hh.

Bitfield<13> X86ISA::bd

Definition at line 651 of file misc.hh.

Bitfield<2,0> X86ISA::bottom3

Definition at line 178 of file types.hh.

Bitfield<14> X86ISA::bs

Definition at line 652 of file misc.hh.

Bitfield<8> X86ISA::bsp

Definition at line 1005 of file misc.hh.

Bitfield<15> X86ISA::bt

Definition at line 653 of file misc.hh.

Bitfield<1> X86ISA::btf

Definition at line 716 of file misc.hh.

Bitfield< 42 > X86ISA::c

Definition at line 888 of file misc.hh.

Referenced by X86ISA::PS2Device::unserialize().

const uint32_t X86ISA::ccFlagMask = PFBit | AFBit | ZFBit | SFBit

Definition at line 68 of file misc.hh.

Referenced by setRFlags().

Bitfield<30> X86ISA::cd

Definition at line 596 of file misc.hh.

Bitfield< 0 > X86ISA::cf

Definition at line 552 of file misc.hh.

const uint32_t X86ISA::cfofMask = CFBit | OFBit

Definition at line 67 of file misc.hh.

Referenced by setRFlags().

Bitfield< 36, 32 > X86ISA::count

Definition at line 704 of file misc.hh.

Referenced by FlashDevice::accessDevice(), DefaultCommit< Impl >::commitInsts(), InstructionQueue< Impl >::completeMemInst(), countBoolVec(), InstructionQueue< Impl >::doSquash(), IGbE::drain(), FunctionProfile::dump(), UFSHostDevice::finalUTP(), BlockBloomFilter::getTotalCount(), BulkBloomFilter::getTotalCount(), LSB_CountingBloomFilter::getTotalCount(), MultiGrainBloomFilter::getTotalCount(), H3BloomFilter::getTotalCount(), NonCountingBloomFilter::getTotalCount(), MultiBitSelBloomFilter::getTotalCount(), X86KvmCPU::handleKvmExitIO(), FlashDevice::initializeFlash(), InstructionQueue< Impl >::insert(), InstructionQueue< Impl >::insertNonSpec(), ElfObject::loadSomeSymbols(), UFSHostDevice::manageReadTransfer(), UFSHostDevice::manageWriteTransfer(), System::markWorkItem(), InstructionQueue< Impl >::numFreeEntries(), MipsISA::Interrupts::onCpuTimerInterrupt(), StackDistCalc::printStack(), SimpleDisk::read(), Intel8254Timer::Counter::read(), UFSHostDevice::UFSSCSIDevice::readFlash(), FlashDevice::remap(), UFSHostDevice::requestHandler(), InstructionQueue< Impl >::resetState(), InstructionQueue< Impl >::scheduleReadyInsts(), UFSHostDevice::UFSSCSIDevice::SCSICMDHandle(), UFSHostDevice::SCSIResume(), FlashDevice::serialize(), FuncPageTable::serialize(), Sinic::Device::serialize(), ActivityRecorder::setActivityCount(), UFSHostDevice::UFSSCSIDevice::statusCheck(), UFSHostDevice::UFSHostDevice(), FlashDevice::unserialize(), FuncPageTable::unserialize(), ActivityRecorder::validate(), Checker< Impl >::verify(), FutexMap::wakeup(), UFSHostDevice::UFSSCSIDevice::writeFlash(), and writevFunc().

Bitfield<31,24> X86ISA::counterMask

Definition at line 810 of file misc.hh.

Bitfield<5, 4> X86ISA::cpl

Definition at line 581 of file misc.hh.

const uint8_t X86ISA::CS = CSOverride

Definition at line 45 of file decoder_tables.cc.

const bool X86ISA::CurThreadInfoImplemented = false

Definition at line 69 of file isa_traits.hh.

const int X86ISA::CurThreadInfoReg = -1

Definition at line 70 of file isa_traits.hh.

Bitfield< 54 > X86ISA::d

Definition at line 89 of file pagetable.hh.

Bitfield<3> X86ISA::de

Definition at line 636 of file misc.hh.

Referenced by dumpDmesgEntry(), and OutputDirectory::remove().

X86ISA::decodeVal

Definition at line 76 of file types.hh.

Bitfield<13, 12> X86ISA::defAddr

Definition at line 586 of file misc.hh.

Bitfield<3> X86ISA::defaultSize

Definition at line 941 of file misc.hh.

Bitfield<9, 8> X86ISA::defOp

Definition at line 584 of file misc.hh.

Bitfield< 10, 8 > X86ISA::deliveryMode

Definition at line 46 of file intmessage.hh.

Bitfield<12> X86ISA::deliveryStatus

Definition at line 96 of file apic.hh.

X86ISA::destination

Definition at line 44 of file intmessage.hh.

Referenced by GarnetSyntheticTraffic::generatePkt(), UFSHostDevice::readDevice(), and UFSHostDevice::transferDone().

Bitfield< 11 > X86ISA::destMode

Definition at line 47 of file intmessage.hh.

Bitfield<19, 18> X86ISA::destShorthand

Definition at line 99 of file apic.hh.

Bitfield<10> X86ISA::df

Definition at line 568 of file misc.hh.

Bitfield<2> X86ISA::disA20M

Definition at line 838 of file misc.hh.

Bitfield< 46, 45 > X86ISA::dpl

Definition at line 881 of file misc.hh.

const uint8_t X86ISA::DS = DSOverride

Definition at line 46 of file decoder_tables.cc.

Bitfield<31,0> X86ISA::E

Definition at line 53 of file int.hh.

Referenced by ArmISA::ArmStaticInst::cSwap().

Bitfield< 42 > X86ISA::e

Definition at line 754 of file misc.hh.

Referenced by dumpKvm().

Bitfield<3> X86ISA::ecf

Definition at line 550 of file misc.hh.

Bitfield<1> X86ISA::eipv

Definition at line 710 of file misc.hh.

Bitfield<2> X86ISA::em

Definition at line 603 of file misc.hh.

Referenced by Consumer::scheduleEvent(), and Consumer::scheduleEventAbsolute().

Bitfield< 22 > X86ISA::en

Definition at line 767 of file misc.hh.

Bitfield<11> X86ISA::enable

Definition at line 1004 of file misc.hh.

Referenced by ArmISA::PMU::updateAllCounters().

Bitfield<1> X86ISA::enter

Definition at line 847 of file misc.hh.

const uint8_t X86ISA::ES = ESOverride

Definition at line 47 of file decoder_tables.cc.

X86ISA::esi

Definition at line 860 of file misc.hh.

Bitfield<4> X86ISA::et

Definition at line 601 of file misc.hh.

X86ISA::eventMask

Definition at line 801 of file misc.hh.

Bitfield<3> X86ISA::exit

Definition at line 849 of file misc.hh.

Referenced by RoutingUnit::lookupRoutingTable(), main(), Sinic::Device::rxKick(), NSGigE::rxKick(), ArmISA::ArmStaticInst::shift_carry_imm(), ArmISA::ArmStaticInst::shift_carry_rs(), ArmISA::ArmStaticInst::shift_rm_imm(), ArmISA::ArmStaticInst::shift_rm_rs(), ArmISA::ArmStaticInst::shiftReg64(), Sinic::Device::txKick(), NSGigE::txKick(), and usage().

Bitfield<14> X86ISA::expandDown

Definition at line 949 of file misc.hh.

Referenced by X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

Bitfield<5> X86ISA::ezf

Definition at line 548 of file misc.hh.

Bitfield<10> X86ISA::fe

Definition at line 753 of file misc.hh.

Bitfield<14> X86ISA::ffxsr

Definition at line 787 of file misc.hh.

Bitfield<8> X86ISA::fix

Definition at line 681 of file misc.hh.

const int X86ISA::FlagShift = 4

Definition at line 52 of file ldstflags.hh.

Referenced by Sequencer::makeRequest(), GPUCoalescer::makeRequest(), X86ISA::GpuTLB::pagingProtectionChecks(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

const int X86ISA::FramePointerReg = INTREG_RBP

Definition at line 86 of file registers.hh.

const uint8_t X86ISA::FS = FSOverride

Definition at line 48 of file decoder_tables.cc.

Bitfield<16> X86ISA::fsgsbase

Definition at line 626 of file misc.hh.

Bitfield< 55 > X86ISA::g

Definition at line 87 of file pagetable.hh.

Bitfield<1> X86ISA::g0

Definition at line 658 of file misc.hh.

Bitfield<3> X86ISA::g1

Definition at line 660 of file misc.hh.

Bitfield<5> X86ISA::g2

Definition at line 662 of file misc.hh.

Bitfield<7> X86ISA::g3

Definition at line 664 of file misc.hh.

Bitfield<13> X86ISA::gd

Definition at line 667 of file misc.hh.

const uint64_t X86ISA::GDTPhysAddr = 0x61000

Definition at line 69 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

const uint64_t X86ISA::GDTVirtAddr = 0xffff800000001000

Definition at line 68 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

Bitfield<9> X86ISA::ge

Definition at line 666 of file misc.hh.

bool X86ISA::global

Definition at line 120 of file pagetable.hh.

Referenced by X86ISA::TLB::flushNonGlobal(), Stats::initSimStats(), and ArmISA::TLB::insert().

Bitfield<6> X86ISA::granularity

Definition at line 944 of file misc.hh.

const uint8_t X86ISA::GS = GSOverride

Definition at line 49 of file decoder_tables.cc.

Bitfield<15,8> X86ISA::H

Definition at line 57 of file int.hh.

Referenced by SparcISA::SparcFault< T >::vals().

const bool X86ISA::HasUnalignedMemAcc = true

Definition at line 67 of file isa_traits.hh.

const uint64_t X86ISA::IDTPhysAddr = 0x62000

Definition at line 71 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

const uint64_t X86ISA::IDTVirtAddr = 0xffff800000002000

Definition at line 70 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

const Addr X86ISA::IntAddrPrefixCPUID = ULL(0x100000000)

Definition at line 68 of file x86_traits.hh.

Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().

const Addr X86ISA::IntAddrPrefixIO = ULL(0x300000000)

Definition at line 70 of file x86_traits.hh.

Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().

const Addr X86ISA::IntAddrPrefixMask = ULL(0xffffffff00000000)

Definition at line 67 of file x86_traits.hh.

Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().

const Addr X86ISA::IntAddrPrefixMSR = ULL(0x200000000)

Definition at line 69 of file x86_traits.hh.

Referenced by X86ISA::TLB::translateInt(), and X86ISA::GpuTLB::translateInt().

Bitfield<20> X86ISA::intEn

Definition at line 807 of file misc.hh.

Bitfield<9> X86ISA::intf

Definition at line 569 of file misc.hh.

const IntRegIndex X86ISA::IntFoldBit = (IntRegIndex)(1 << 6)

static

Definition at line 153 of file int.hh.

Referenced by X86ISA::ISA::flattenIntIndex(), X86ISA::X86StaticInst::merge(), X86ISA::X86StaticInst::pick(), X86ISA::X86StaticInst::printReg(), and X86ISA::X86StaticInst::signedPick().

Bitfield<23> X86ISA::inv

Definition at line 809 of file misc.hh.

Referenced by BasePrefetcher::observeAccess().

Bitfield<13, 12> X86ISA::iopl

Definition at line 566 of file misc.hh.

Bitfield<35, 32> X86ISA::IST

Definition at line 971 of file misc.hh.

const uint64_t X86ISA::ISTPhysAddr = 0x64000

Definition at line 75 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

const uint64_t X86ISA::ISTVirtAddr = 0xffff800000004000

Definition at line 74 of file system.hh.

Referenced by X86ISA::X86_64Process::initState(), and m5PageFault().

Bitfield<7, 0> X86ISA::L

Definition at line 59 of file int.hh.

Referenced by ArmProcess32::ArmProcess32(), ArmProcess64::ArmProcess64(), ArmISA::TableWalker::doLongDescriptor(), KvmDevice::ioctl(), Kvm::ioctl(), PerfKvmCounter::ioctl(), KvmVM::ioctl(), BaseKvmCPU::ioctl(), MipsProcess::MipsProcess(), PowerProcess::PowerProcess(), and RiscvProcess::RiscvProcess().

Bitfield< 2 > X86ISA::l

Definition at line 876 of file misc.hh.

Bitfield<2> X86ISA::l1

Definition at line 659 of file misc.hh.

Bitfield<4> X86ISA::l2

Definition at line 661 of file misc.hh.

Bitfield<6> X86ISA::l3

Definition at line 663 of file misc.hh.

Bitfield<8> X86ISA::le

Definition at line 665 of file misc.hh.

X86ISA::legacy

Definition at line 610 of file misc.hh.

Bitfield<19, 18> X86ISA::len0

Definition at line 669 of file misc.hh.

Bitfield<23, 22> X86ISA::len1

Definition at line 671 of file misc.hh.

Bitfield<27, 26> X86ISA::len2

Definition at line 673 of file misc.hh.

Bitfield<31, 30> X86ISA::len3

Definition at line 675 of file misc.hh.

Bitfield< 14 > X86ISA::level

Definition at line 48 of file intmessage.hh.

Referenced by Trie< Key, Value >::Node::dump(), SparcISA::Interrupts::getInterrupt(), StackDistCalc::getSum(), SparcISA::Interrupts::InterruptLevel(), SparcISA::SparcFaultBase::invoke(), StackDistCalc::sanityCheckTree(), StackDistCalc::updateSum(), and StackDistCalc::updateSumsLeavesToRoot().

Bitfield< 51, 48 > X86ISA::limitHigh

Definition at line 878 of file misc.hh.

Bitfield< 15, 0 > X86ISA::limitLow

Definition at line 879 of file misc.hh.

Bitfield<10> X86ISA::lma

Definition at line 784 of file misc.hh.

Bitfield<8> X86ISA::lme

Definition at line 783 of file misc.hh.

const uint8_t X86ISA::LO = Lock

Definition at line 54 of file decoder_tables.cc.

Bitfield<5> X86ISA::lock

Definition at line 79 of file types.hh.

Referenced by DistIface::Sync::abort(), doSimLoop(), DrainManager::drainableCount(), DistIface::SyncNode::progress(), DistIface::SyncSwitch::progress(), DrainManager::registerDrainable(), DistIface::SyncNode::requestCkpt(), DistIface::SyncNode::requestExit(), DistIface::SyncNode::run(), DistIface::SyncSwitch::run(), EventQueue::serviceOne(), DrainManager::unregisterDrainable(), and Barrier::wait().

unsigned X86ISA::logBytes

Definition at line 107 of file pagetable.hh.

Referenced by X86ISA::RemoteGDB::acc(), and vtophys().

X86ISA::longl1

Definition at line 67 of file pagetable.hh.

Bitfield<29, 21> X86ISA::longl2

Definition at line 68 of file pagetable.hh.

Bitfield<38, 30> X86ISA::longl3

Definition at line 69 of file pagetable.hh.

Bitfield<47, 39> X86ISA::longl4

Definition at line 70 of file pagetable.hh.

Bitfield<4> X86ISA::longMode

Definition at line 942 of file misc.hh.

X86ISA::longPdtb

Definition at line 614 of file misc.hh.

uint64_t X86ISA::lruSeq

Definition at line 126 of file pagetable.hh.

Bitfield<4, 0> X86ISA::m

Definition at line 115 of file types.hh.

static const int NumArgumentRegs32 M5_VAR_USED

Initial value:

= {
        0x0,                            
        0x0,                            
        0x0,                            
        { OneByteOpcode, 0x90 },        
        0x0, 0x0,                       
        0, 0,                           
        8, 8, 8,                        
        0,                              
        SixtyFourBitMode                
                                        
    }

Definition at line 72 of file isa_traits.hh.

X86ISA::mask

Definition at line 797 of file misc.hh.

Referenced by X86ISA::RemoteGDB::acc(), X86ISA::ISA::clear(), X86ISA::Decoder::decode(), decodeAddr(), X86ISA::Decoder::getImmediate(), X86ISA::I386Process::getSyscallArg(), handleIprRead(), handleIprWrite(), X86ISA::Interrupts::read(), X86ISA::Walker::WalkerState::stepWalk(), X86ISA::TLB::translate(), X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), X86ISA::I8259::write(), and X86ISA::Interrupts::write().

X86ISA::mcaErrorCode

Definition at line 761 of file misc.hh.

Bitfield<6> X86ISA::mce

Definition at line 633 of file misc.hh.

Bitfield<8> X86ISA::MCGCP

Definition at line 705 of file misc.hh.

Bitfield<2> X86ISA::mcip

Definition at line 711 of file misc.hh.

Bitfield<19> X86ISA::mfdm

Definition at line 815 of file misc.hh.

Bitfield<59> X86ISA::miscv

Definition at line 766 of file misc.hh.

const uint64_t X86ISA::MMIORegionPhysAddr = 0xffff0000

Definition at line 79 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

const uint64_t X86ISA::MMIORegionVirtAddr = 0xffffc90000000000

Definition at line 78 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

X86ISA::mod

Definition at line 88 of file types.hh.

Referenced by X86ISA::IntelMP::CompatAddrSpaceMod::writeOut().

Bitfield<31,16> X86ISA::modelSpecificCode

Definition at line 762 of file misc.hh.

Bitfield<1> X86ISA::mp

Definition at line 604 of file misc.hh.

Referenced by GlobalMemPipeline::exec().

const MsrMap X86ISA::msrMap

Map between MSR addresses and their corresponding misc registers.

Note: This map is usually only used when enumeration of supported MSRs is needed (e.g., in virtualized CPUs). Code that needs to look-up specific MSRs should use msrAddrToIndex().

Referenced by X86KvmCPU::getMsrIntersection(), msrAddrToIndex(), X86KvmCPU::updateKvmStateMSRs(), and X86KvmCPU::updateThreadContextMSRs().

const MsrMap::value_type X86ISA::msrMapData[]

Definition at line 38 of file msr.cc.

const unsigned X86ISA::msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0])

static

Definition at line 144 of file msr.cc.

Bitfield<20> X86ISA::mvdm

Definition at line 816 of file misc.hh.

const char X86ISA::nameString[nameStringSize] = "Fake M5 x86_64 CPU"

static

Definition at line 69 of file cpuid.cc.

Referenced by doCpuid().

const int X86ISA::nameStringSize = 48

static

Definition at line 68 of file cpuid.cc.

Referenced by doCpuid().

Bitfield<5> X86ISA::ne

Definition at line 600 of file misc.hh.

bool X86ISA::noExec

Definition at line 124 of file pagetable.hh.

Bitfield<21, 12> X86ISA::norml1

Definition at line 76 of file pagetable.hh.

Bitfield<31, 22> X86ISA::norml2

Definition at line 77 of file pagetable.hh.

Bitfield<14> X86ISA::nt

Definition at line 565 of file misc.hh.

const int X86ISA::NumCCRegs = NUM_CCREGS

Definition at line 59 of file registers.hh.

Referenced by copyRegs().

const int X86ISA::NumCRegs = 16

Definition at line 61 of file x86_traits.hh.

Referenced by MISCREG_CR().

const int X86ISA::NumDRegs = 8

Definition at line 62 of file x86_traits.hh.

Referenced by MISCREG_DR().

const int X86ISA::NumFloatRegs

Initial value:

=

NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8

X86ISA::NumMicroFpRegs

const int NumMicroFpRegs

Definition: x86_traits.hh:59

X86ISA::NumMMXRegs

const int NumMMXRegs

Definition: x86_traits.hh:57

X86ISA::NumXMMRegs

const int NumXMMRegs

Definition: x86_traits.hh:58

Definition at line 65 of file registers.hh.

Referenced by copyRegs().

const int X86ISA::NumImplicitIntRegs = 6

Definition at line 49 of file x86_traits.hh.

Referenced by initCPU().

const int X86ISA::NumIntArchRegs = NUM_INTREGS

Definition at line 57 of file registers.hh.

const int X86ISA::NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs

Definition at line 58 of file registers.hh.

Referenced by copyRegs().

const int X86ISA::NumMicroFpRegs = 8

Definition at line 59 of file x86_traits.hh.

Referenced by X86ISA::X86StaticInst::printReg().

const int X86ISA::NumMicroIntRegs = 16

Definition at line 47 of file x86_traits.hh.

Referenced by initCPU(), and INTREG_IMPLICIT().

const int X86ISA::NumMiscRegs = NUM_MISCREGS

Definition at line 55 of file registers.hh.

Referenced by X86ISA::ISA::clear(), X86ISA::ISA::serialize(), and X86ISA::ISA::unserialize().

const int X86ISA::NumMMXRegs = 8

Definition at line 57 of file x86_traits.hh.

Referenced by X86ISA::X86StaticInst::printReg().

const int X86ISA::NumSegments = 6

Definition at line 64 of file x86_traits.hh.

const int X86ISA::NumSysSegments = 4

Definition at line 65 of file x86_traits.hh.

const int X86ISA::NumXMMRegs = 16

Definition at line 58 of file x86_traits.hh.

Referenced by X86ISA::X86StaticInst::printReg().

Bitfield<29> X86ISA::nw

Definition at line 597 of file misc.hh.

Bitfield<11> X86ISA::nxe

Definition at line 785 of file misc.hh.

Bitfield<11> X86ISA::of

Definition at line 567 of file misc.hh.

X86ISA::offsetHigh

Definition at line 954 of file misc.hh.

Bitfield< 15, 0 > X86ISA::offsetLow

Definition at line 955 of file misc.hh.

const uint8_t X86ISA::OO = OperandSizeOverride

Definition at line 52 of file decoder_tables.cc.

Bitfield<17> X86ISA::os

Definition at line 804 of file misc.hh.

Referenced by O3ThreadState< Impl >::dumpFuncProfile(), SimpleThread::dumpFuncProfile(), IdeController::EndBitUnion(), OutputDirectory::findOrCreate(), Minor::LSQ::StoreBuffer::minorTrace(), OutputDirectory::open(), operator<<(), Minor::operator<<(), GenericISA::operator<<(), operator<<(), Linux::DmesgDumpEvent::process(), Linux::KernelPanicEvent::process(), and PseudoInst::writefile().

Bitfield<9> X86ISA::osfxsr

Definition at line 630 of file misc.hh.

Bitfield<10> X86ISA::osxmmexcpt

Definition at line 628 of file misc.hh.

Bitfield<56,32> X86ISA::otherInfo

Definition at line 763 of file misc.hh.

Bitfield<62> X86ISA::over

Definition at line 769 of file misc.hh.

Bitfield< 1, 0 > X86ISA::p

Definition at line 95 of file pagetable.hh.

Referenced by m5PageFault(), X86ISA::GpuTLB::CpuSidePort::recvFunctional(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), and X86ISA::GpuTLB::translationReturn().

Bitfield<5> X86ISA::pae

Definition at line 634 of file misc.hh.

Bitfield<20, 12> X86ISA::pael1

Definition at line 72 of file pagetable.hh.

Bitfield<29, 21> X86ISA::pael2

Definition at line 73 of file pagetable.hh.

Bitfield<31, 30> X86ISA::pael3

Definition at line 74 of file pagetable.hh.

Bitfield<31, 5> X86ISA::paePdtb

Definition at line 618 of file misc.hh.

const Addr X86ISA::PageBytes = ULL(1) << PageShift

Definition at line 64 of file isa_traits.hh.

Referenced by X86ISA::X86Process::argsInit(), X86ISA::TLB::finalizePhysical(), X86ISA::I386Process::I386Process(), X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), m5PageFault(), X86ISA::GpuTLB::translate(), and X86ISA::X86_64Process::X86_64Process().

const Addr X86ISA::PageShift = 12

Definition at line 63 of file isa_traits.hh.

const std::vector<uint8_t> X86ISA::PageTableLayout = {9, 9, 9, 9}

The size of each level of the page table expressed in base 2 logarithmic values.

Definition at line 158 of file pagetable.hh.

const uint64_t X86ISA::pageTablePhysAddr = 0x70000

Definition at line 81 of file system.hh.

Referenced by X86ISA::PageTableOps::getBasePtr(), and X86ISA::X86_64Process::initState().

Bitfield<6> X86ISA::paging

Definition at line 582 of file misc.hh.

bool X86ISA::patBit

Definition at line 122 of file pagetable.hh.

Bitfield<2> X86ISA::pb0

Definition at line 717 of file misc.hh.

Bitfield<3> X86ISA::pb1

Definition at line 718 of file misc.hh.

Bitfield<4> X86ISA::pb2

Definition at line 719 of file misc.hh.

Bitfield<5> X86ISA::pb3

Definition at line 720 of file misc.hh.

Bitfield<19> X86ISA::pc

Definition at line 806 of file misc.hh.

Referenced by X86ISA::StackTrace::decodePrologue(), initCPU(), X86ISA::X86FaultBase::invoke(), X86ISA::X86Trap::invoke(), X86ISA::InitInterrupt::invoke(), and X86ISA::I386Process::syscall().

Bitfield<57> X86ISA::pcc

Definition at line 764 of file misc.hh.

Bitfield< 4 > X86ISA::pcd

Definition at line 91 of file pagetable.hh.

Bitfield<8> X86ISA::pce

Definition at line 631 of file misc.hh.

Bitfield<31, 12> X86ISA::pdtb

Definition at line 616 of file misc.hh.

Bitfield<0> X86ISA::pe

Definition at line 605 of file misc.hh.

Referenced by EtherLink::Link::serialize().

Bitfield< 2 > X86ISA::pf

Definition at line 551 of file misc.hh.

Referenced by Cache::recvTimingReq(), and ComputeUnit::DTLBPort::recvTimingResp().

const uint64_t X86ISA::PFHandlerPhysAddr = 0x65000

Definition at line 77 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

const uint64_t X86ISA::PFHandlerVirtAddr = 0xffff800000005000

Definition at line 76 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

Bitfield<7> X86ISA::pge

Definition at line 632 of file misc.hh.

X86ISA::physAddr

Definition at line 832 of file misc.hh.

Referenced by TraceCPU::ElasticDataGen::GraphNode::writeElementAsTrace().

const Addr X86ISA::PhysAddrAPICRangeSize = 1 << 12

Definition at line 78 of file x86_traits.hh.

Referenced by X86ISA::I82094AA::getIntAddrRange(), X86ISA::Interrupts::getIntAddrRange(), and x86InterruptAddress().

const Addr X86ISA::PhysAddrPrefixInterrupts = ULL(0xA000000000000000)

Definition at line 75 of file x86_traits.hh.

Referenced by x86InterruptAddress().

const Addr X86ISA::PhysAddrPrefixIO = ULL(0x8000000000000000)

Definition at line 72 of file x86_traits.hh.

Referenced by X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), and x86IOAddress().

const Addr X86ISA::PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000)

Definition at line 74 of file x86_traits.hh.

Referenced by x86LocalAPICAddress().

const Addr X86ISA::PhysAddrPrefixPciConfig = ULL(0xC000000000000000)

Definition at line 73 of file x86_traits.hh.

Referenced by X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), and x86PciConfigAddress().

Bitfield< 51, 12 > X86ISA::physbase

Definition at line 729 of file misc.hh.

Bitfield< 51, 12 > X86ISA::physmask

Definition at line 734 of file misc.hh.

Bitfield< 0 > X86ISA::present

Definition at line 945 of file misc.hh.

Referenced by X86ISA::Walker::WalkerState::pageFault(), X86ISA::PageFault::PageFault(), and PersistentTable::persistentRequestLock().

Bitfield<7> X86ISA::prot

Definition at line 583 of file misc.hh.

Referenced by mmapImpl().

Bitfield<7> X86ISA::ps

Definition at line 88 of file pagetable.hh.

Bitfield<4> X86ISA::pse

Definition at line 635 of file misc.hh.

Bitfield<1> X86ISA::pvi

Definition at line 638 of file misc.hh.

Bitfield< 3 > X86ISA::pwt

Definition at line 92 of file pagetable.hh.

X86ISA::R

Definition at line 51 of file int.hh.

Bitfield< 2 > X86ISA::r

Definition at line 889 of file misc.hh.

Referenced by X86ISA::RemoteGDB::X86GdbRegCache::getRegs(), X86ISA::RemoteGDB::X86GdbRegCache::setRegs(), and X86ISA::RemoteGDB::AMD64GdbRegCache::setRegs().

Bitfield<4> X86ISA::rd

Definition at line 822 of file misc.hh.

const uint8_t X86ISA::RE = Rep

Definition at line 55 of file decoder_tables.cc.

Bitfield<13> X86ISA::readable

Definition at line 948 of file misc.hh.

Bitfield<5,3> X86ISA::reg

Definition at line 89 of file types.hh.

Referenced by RegAddrOperand< RegOperandType >::calcLane(), RegAddrOperand< RegOperandType >::calcVector(), Minor::Scoreboard::canInstIssue(), ArmISA::canReadAArch64SysReg(), ArmISA::canReadCoprocReg(), ArmISA::canWriteAArch64SysReg(), ArmISA::canWriteCoprocReg(), Minor::Scoreboard::clearInstDests(), HsailISA::decodeBr(), HsailISA::decodeBrn(), HsailISA::decodeCbr(), X86ISA::StackTrace::decodePrologue(), MipsISA::StackTrace::decodePrologue(), AlphaISA::StackTrace::decodePrologue(), RegAddrOperand< RegOperandType >::disassemble(), ArmV8KvmCPU::dump(), Minor::Scoreboard::execSeqNumToWaitFor(), Minor::Scoreboard::findIndex(), findRegDataType(), X86ISA::ISA::flattenCCIndex(), RiscvISA::ISA::flattenCCIndex(), PowerISA::ISA::flattenCCIndex(), AlphaISA::ISA::flattenCCIndex(), MipsISA::ISA::flattenCCIndex(), SparcISA::ISA::flattenCCIndex(), ArmISA::ISA::flattenCCIndex(), X86ISA::ISA::flattenFloatIndex(), RiscvISA::ISA::flattenFloatIndex(), PowerISA::ISA::flattenFloatIndex(), AlphaISA::ISA::flattenFloatIndex(), MipsISA::ISA::flattenFloatIndex(), SparcISA::ISA::flattenFloatIndex(), ArmISA::ISA::flattenFloatIndex(), RiscvISA::ISA::flattenIntIndex(), PowerISA::ISA::flattenIntIndex(), AlphaISA::ISA::flattenIntIndex(), MipsISA::ISA::flattenIntIndex(), ArmISA::ISA::flattenIntIndex(), SparcISA::ISA::flattenIntIndex(), X86ISA::ISA::flattenMiscIndex(), RiscvISA::ISA::flattenMiscIndex(), PowerISA::ISA::flattenMiscIndex(), AlphaISA::ISA::flattenMiscIndex(), MipsISA::ISA::flattenMiscIndex(), SparcISA::ISA::flattenMiscIndex(), ArmISA::ISA::flattenMiscIndex(), ArmISA::flattenMiscRegNsBanked(), Minor::flattenRegIndex(), KvmKernelGicV2::getGicReg(), ArmV8KvmCPU::getSysRegMap(), RegAddrOperand< RegOperandType >::init(), ArmISA::intRegInMode(), ArmISA::MacroMemOp::MacroMemOp(), ArmISA::makeSP(), ArmISA::makeZero(), Minor::Scoreboard::markupInstDests(), ArmISA::TableWalker::memAttrsLPAE(), X86ISA::X86StaticInst::merge(), CustomNoMaliGpu::onReset(), Net::EthAddr::operator uint64_t(), X86ISA::X86StaticInst::pick(), ArmISA::preUnflattenMiscReg(), Minor::printRegName(), EnergyCtrl::read(), X86ISA::Interrupts::read(), Sinic::Device::read(), NSGigE::read(), X86ISA::Interrupts::readReg(), X86ISA::Cmos::readRegister(), Sinic::Device::serialize(), KvmKernelGicV2::setGicReg(), X86ISA::Interrupts::setReg(), X86ISA::Interrupts::setRegNoEffect(), X86ISA::X86StaticInst::signedPick(), stringToRegister(), ArmISA::unflattenMiscReg(), Sinic::Device::unserialize(), ArmV8KvmCPU::updateKvmState(), ArmKvmCPU::updateKvmStateCoProc(), ArmKvmCPU::updateTCStateCoProc(), ArmV8KvmCPU::updateThreadContext(), EnergyCtrl::write(), X86ISA::Interrupts::write(), NSGigE::write(), and X86ISA::Cmos::writeRegister().

Bitfield<6> X86ISA::rep

Definition at line 78 of file types.hh.

Bitfield<7> X86ISA::repne

Definition at line 77 of file types.hh.

const int X86ISA::ReturnAddressReg = 0

Definition at line 84 of file registers.hh.

Referenced by X86ISA::StackTrace::decodePrologue().

const int X86ISA::ReturnValueReg = INTREG_RAX

Definition at line 85 of file registers.hh.

Bitfield<16> X86ISA::rf

Definition at line 564 of file misc.hh.

Bitfield<1> X86ISA::rInit

Definition at line 837 of file misc.hh.

Bitfield<2,0> X86ISA::rm

Definition at line 90 of file types.hh.

Referenced by X86ISA::EmulEnv::doModRM().

const uint8_t X86ISA::RN = Repne

Definition at line 56 of file decoder_tables.cc.

Bitfield<1, 0> X86ISA::rpl

Definition at line 863 of file misc.hh.

Bitfield<4> X86ISA::rsmCycle

Definition at line 850 of file misc.hh.

Bitfield<17, 16> X86ISA::rw0

Definition at line 668 of file misc.hh.

Bitfield<21, 20> X86ISA::rw1

Definition at line 670 of file misc.hh.

Bitfield<25, 24> X86ISA::rw2

Definition at line 672 of file misc.hh.

Bitfield<29, 28> X86ISA::rw3

Definition at line 674 of file misc.hh.

const uint8_t X86ISA::RX = RexPrefix

Definition at line 57 of file decoder_tables.cc.

Bitfield<44> X86ISA::s

Definition at line 882 of file misc.hh.

Referenced by Float16::Float16(), and Float16::operator float().

X86ISA::scale

Definition at line 94 of file types.hh.

Referenced by ArmISA::vfpSFixedToFpD(), ArmISA::vfpSFixedToFpS(), ArmISA::vfpUFixedToFpD(), and ArmISA::vfpUFixedToFpS().

SignedBitfield<31,0> X86ISA::SE

Definition at line 54 of file int.hh.

Bitfield<2,0> X86ISA::seg

Definition at line 84 of file types.hh.

Referenced by X86ISA::X86_64Process::initState(), X86ISA::I386Process::initState(), X86ISA::InitInterrupt::invoke(), ElfObject::loadSections(), X86ISA::GpuTLB::tlbLookup(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

const Request::FlagsType M5_VAR_USED X86ISA::SegmentFlagMask = mask(4)

Definition at line 51 of file ldstflags.hh.

Referenced by X86ISA::GpuTLB::tlbLookup(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

Bitfield< 31, 16 > X86ISA::selector

Definition at line 956 of file misc.hh.

Bitfield< 7 > X86ISA::sf

Definition at line 546 of file misc.hh.

SignedBitfield<15,8> X86ISA::SH

Definition at line 58 of file int.hh.

Referenced by SparcISA::SparcFault< T >::vals().

Bitfield<15, 3> X86ISA::si

Definition at line 861 of file misc.hh.

Referenced by X86ISA::Decoder::decode().

SignedBitfield<7, 0> X86ISA::SL

Definition at line 60 of file int.hh.

Bitfield<2> X86ISA::smiCycle

Definition at line 848 of file misc.hh.

SignedBitfield<63,0> X86ISA::SR

Definition at line 52 of file int.hh.

const uint8_t X86ISA::SS = SSOverride

Definition at line 50 of file decoder_tables.cc.

Bitfield<17, 16> X86ISA::stack

Definition at line 588 of file misc.hh.

Referenced by setupAltStack().

const int X86ISA::StackPointerReg = INTREG_RSP

Definition at line 82 of file registers.hh.

Referenced by X86ISA::X86Process::argsInit().

Bitfield< 2, 0 > X86ISA::submode

Definition at line 580 of file misc.hh.

Bitfield<12> X86ISA::svme

Definition at line 786 of file misc.hh.

SignedBitfield<15,0> X86ISA::SX

Definition at line 56 of file int.hh.

const uint64_t X86ISA::syscallCodePhysAddr = 0x60000

Definition at line 67 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

const uint64_t X86ISA::syscallCodeVirtAddr = 0xffff800000000000

Definition at line 66 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

Bitfield<47,32> X86ISA::syscallCsAndSs

Definition at line 792 of file misc.hh.

const int X86ISA::SyscallPseudoReturnReg = INTREG_RDX

Definition at line 90 of file registers.hh.

Bitfield<63,48> X86ISA::sysretCsAndSs

Definition at line 793 of file misc.hh.

Bitfield<15> X86ISA::system

Definition at line 950 of file misc.hh.

X86ISA::targetCS

Definition at line 689 of file misc.hh.

X86ISA::targetEIP

Definition at line 697 of file misc.hh.

X86ISA::targetEip

Definition at line 791 of file misc.hh.

X86ISA::targetESP

Definition at line 693 of file misc.hh.

Bitfield<8> X86ISA::tf

Definition at line 570 of file misc.hh.

Bitfield<2> X86ISA::ti

Definition at line 862 of file misc.hh.

Bitfield<21> X86ISA::tom2

Definition at line 817 of file misc.hh.

X86ISA::top5

Definition at line 177 of file types.hh.

X86ISA::tpr

Definition at line 643 of file misc.hh.

TlbEntryTrie::Handle X86ISA::trieHandle

Definition at line 128 of file pagetable.hh.

Referenced by X86ISA::TLB::evictLRU(), X86ISA::TLB::flushAll(), X86ISA::TLB::flushNonGlobal(), and X86ISA::TLB::serialize().

Bitfield< 15 > X86ISA::trigger

Definition at line 49 of file intmessage.hh.

const Addr X86ISA::TriggerIntOffset = 0

static

Definition at line 77 of file intmessage.hh.

Referenced by buildIntRequest().

Bitfield<3> X86ISA::ts

Definition at line 602 of file misc.hh.

Bitfield<2> X86ISA::tsd

Definition at line 637 of file misc.hh.

const uint64_t X86ISA::TSSPhysAddr = 0x63000

Definition at line 73 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

const uint64_t X86ISA::TSSVirtAddr = 0xffff800000003000

Definition at line 72 of file system.hh.

Referenced by X86ISA::X86_64Process::initState().

Bitfield< 43, 40 > X86ISA::type

Definition at line 728 of file misc.hh.

Referenced by CacheRecorder::addRecord(), broadcast(), GarnetNetwork::collateStats(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::completeAcc(), KvmVM::createDevice(), createMachineID(), ArmV8KvmCPU::dump(), findRegDataType(), ArmISA::MemoryReg64::generateDisassembly(), ArmISA::PMU::getCounterTypeRegister(), Throttle::getMsgCount(), Switch::getMsgCount(), ArmV8KvmCPU::getSysRegMap(), Sequencer::hitCallback(), GPUCoalescer::hitCallback(), Prefetcher::initializeStream(), iGbReg::TxdOp::isType(), MachineTypeAndNodeIDToMachineID(), mapAddressToRange(), PerfKvmCounterConfig::PerfKvmCounterConfig(), Sequencer::recordMissLatency(), GPUCoalescer::recordMissLatency(), SimpleNetwork::regStats(), Switch::regStats(), Throttle::regStats(), Sinic::Device::rxFilter(), NSGigE::rxFilter(), PipeFDEntry::setEndType(), NetworkLink::setType(), BaseRemoteGDB::trap(), ElasticTrace::TraceInfo::typeToStr(), TraceCPU::ElasticDataGen::GraphNode::typeToStr(), Iob::writeIob(), X86ISA::SMBios::SMBiosStructure::writeOut(), X86ISA::IntelMP::BaseConfigEntry::writeOut(), X86ISA::IntelMP::ExtConfigEntry::writeOut(), and X86ISA::E820Table::writeTo().

Bitfield<2> X86ISA::u

Definition at line 93 of file pagetable.hh.

Bitfield<61> X86ISA::uc

Definition at line 768 of file misc.hh.

bool X86ISA::uncacheable

Definition at line 118 of file pagetable.hh.

Referenced by X86ISA::Walker::WalkerState::stepWalk(), MemTest::tick(), and TLBCoalescer::updatePhysAddresses().

Bitfield<15,8> X86ISA::unitMask

Definition at line 802 of file misc.hh.

Bitfield<2> X86ISA::unusable

Definition at line 940 of file misc.hh.

bool X86ISA::user

Definition at line 113 of file pagetable.hh.

Bitfield<16> X86ISA::usr

Definition at line 803 of file misc.hh.

Bitfield< 6, 3 > X86ISA::v

Definition at line 122 of file types.hh.

const uint8_t X86ISA::V2 = Vex2Prefix

Definition at line 58 of file decoder_tables.cc.

const uint8_t X86ISA::V3 = Vex3Prefix

Definition at line 59 of file decoder_tables.cc.

EndBitUnion (PageTableEntry) struct TlbEntry Addr X86ISA::vaddr

Definition at line 96 of file pagetable.hh.

Referenced by X86ISA::GpuTLB::handleFuncTranslationReturn(), X86ISA::GpuTLB::handleTranslationReturn(), X86ISA::GpuTLB::CpuSidePort::recvFunctional(), X86ISA::Walker::WalkerState::setupWalk(), X86ISA::Walker::WalkerState::stepWalk(), AlphaISA::TlbEntry::TlbEntry(), SparcISA::TlbEntry::TlbEntry(), X86ISA::GpuTLB::tlbLookup(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), X86ISA::GpuTLB::translationReturn(), and AlphaISA::TlbEntry::updateVaddr().

Bitfield<63> X86ISA::val

Definition at line 770 of file misc.hh.

X86ISA::vcnt

Definition at line 680 of file misc.hh.

X86ISA::vector

Definition at line 45 of file intmessage.hh.

Referenced by Iob::receiveDeviceInterrupt(), X86ISA::Interrupts::requestInterrupt(), Iob::serialize(), Iob::unserialize(), and Iob::writeIob().

const char X86ISA::vendorString[vendorStringSize] = "M5 Simulator"

static

Definition at line 67 of file cpuid.cc.

Referenced by doCpuid().

const int X86ISA::vendorStringSize = 13

static

Definition at line 66 of file cpuid.cc.

Referenced by doCpuid().

Bitfield<19> X86ISA::vif

Definition at line 561 of file misc.hh.

Bitfield<20> X86ISA::vip

Definition at line 560 of file misc.hh.

Bitfield<17> X86ISA::vm

Definition at line 563 of file misc.hh.

Bitfield<0> X86ISA::vme

Definition at line 639 of file misc.hh.

Bitfield< 3 > X86ISA::w

Definition at line 94 of file pagetable.hh.

Bitfield<10> X86ISA::wc

Definition at line 682 of file misc.hh.

Bitfield<16> X86ISA::wp

Definition at line 599 of file misc.hh.

Bitfield< 12 > X86ISA::writable

Definition at line 111 of file pagetable.hh.

Bitfield<15,0> X86ISA::X

Definition at line 55 of file int.hh.

Referenced by LTAGE::update().

Bitfield< 6 > X86ISA::x

Definition at line 105 of file types.hh.

Referenced by AlphaProcess::argsInit(), MipsProcess::argsInit(), PowerProcess::argsInit(), SparcProcess::argsInit(), ArmProcess::argsInit(), X86ISA::X86Process::argsInit(), ArmISA::TLB::checkPermissions64(), LSQUnit< Impl >::checkSnoop(), CopyEngine::CopyEngine(), SparcISA::copyRegs(), SparcISA::TLB::demapAll(), SparcISA::TLB::demapContext(), SparcISA::TLB::dumpAll(), IGbE::DescCache< T >::fetchComplete(), SparcISA::TLB::flushAll(), ArmISA::TLB::flushAllNs(), ArmISA::TLB::flushAllSecurity(), ArmISA::TLB::flushAsid(), ArmISA::fp32_add(), ArmISA::fp32_div(), ArmISA::fp32_mul(), ArmISA::fp32_muladd(), ArmISA::fp32_sqrt(), ArmISA::fp64_add(), ArmISA::fp64_div(), ArmISA::fp64_mul(), ArmISA::fp64_muladd(), ArmISA::fp64_sqrt(), ArmISA::fplibCompareEQ(), ArmISA::fplibCompareGE(), ArmISA::fplibCompareGT(), ArmISA::fplibMax(), ArmISA::fplibMin(), ArmISA::fplibRoundInt(), ArmISA::FPToFixed_32(), ArmISA::FPToFixed_64(), H3BloomFilter::get_index(), MultiBitSelBloomFilter::get_index(), PciDevice::getAddrRanges(), Gicv2m::Gicv2m(), X86ISA::GpuTLB::GpuTLB(), IGbE::IGbE(), AlphaISA::initializeIprTable(), SparcISA::TLB::insert(), Iob::Iob(), ArmISA::TLB::lookup(), m5_fegetround(), m5_twin32_t::m5_twin32_t(), m5_twin64_t::operator=(), m5_twin32_t::operator=(), FrameBuffer::pixel(), power(), ArmISA::TLB::printTlb(), RangeAddrMapper::RangeAddrMapper(), Pl390::readCpu(), SparcISA::ISA::readFSReg(), IGbE::DescCache< T >::reset(), VncServer::sendFrameBufferUpdate(), Process::serialize(), Iob::serialize(), X86ISA::TLB::serialize(), SparcISA::TLB::serialize(), CopyEngine::serialize(), IGbE::DescCache< T >::serialize(), Pl111::serialize(), VncServer::setEncodings(), ArmISA::ISA::setMiscReg(), Pl390::softInt(), swap_byte(), swap_byte16(), swap_byte32(), swap_byte64(), swap_byte< Twin32_t >(), swap_byte< Twin64_t >(), System::System(), X86ISA::TLB::TLB(), SparcISA::TLB::TLB(), ArmISA::ISA::tlbiALL(), ArmISA::ISA::tlbiALLN(), ArmISA::ISA::tlbiMVA(), ArmISA::ISA::tlbiVA(), TsunamiCChip::TsunamiCChip(), Process::unserialize(), Iob::unserialize(), X86ISA::TLB::unserialize(), SparcISA::TLB::unserialize(), CopyEngine::unserialize(), IGbE::DescCache< T >::unserialize(), Pl111::unserialize(), PhysicalMemory::unserializeStore(), Pl390::updateIntState(), VGic::VGic(), SparcISA::vtophys(), IGbE::DescCache< T >::wbComplete(), Bitmap::write(), TsunamiCChip::write(), IGbE::DescCache< T >::writeback1(), and CopyEngine::~CopyEngine().

const int X86ISA::ZeroReg = NUM_INTREGS

Definition at line 81 of file registers.hh.

Referenced by X86ISA::X86StaticInst::printMem().

Bitfield< 6 > X86ISA::zf

Definition at line 547 of file misc.hh.

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