mmapped_ipr.hh

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/*
 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
 * All rights reserved.
 *
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 * modification, are permitted provided that the following conditions are
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 * this software without specific prior written permission.
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 * Authors: Gabe Black
 */

#ifndef __ARCH_X86_MMAPPEDIPR_HH__
#define __ARCH_X86_MMAPPEDIPR_HH__

#include "arch/generic/mmapped_ipr.hh"
#include "arch/x86/regs/misc.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"

namespace X86ISA
{
    inline Cycles
    handleIprRead(ThreadContext *xc, Packet *pkt)
    {
        if (GenericISA::isGenericIprAccess(pkt)) {
            return GenericISA::handleGenericIprRead(xc, pkt);
        } else {
            Addr offset = pkt->getAddr() & mask(3);
            MiscRegIndex index = (MiscRegIndex)(
                pkt->getAddr() / sizeof(MiscReg));
            MiscReg data = htog(xc->readMiscReg(index));
            // Make sure we don't trot off the end of data.
            assert(offset + pkt->getSize() <= sizeof(MiscReg));
            pkt->setData(((uint8_t *)&data) + offset);
            return Cycles(1);
        }
    }

    inline Cycles
    handleIprWrite(ThreadContext *xc, Packet *pkt)
    {
        if (GenericISA::isGenericIprAccess(pkt)) {
            return GenericISA::handleGenericIprWrite(xc, pkt);
        } else {
            Addr offset = pkt->getAddr() & mask(3);
            MiscRegIndex index = (MiscRegIndex)(
                pkt->getAddr() / sizeof(MiscReg));
            MiscReg data;
            data = htog(xc->readMiscRegNoEffect(index));
            // Make sure we don't trot off the end of data.
            assert(offset + pkt->getSize() <= sizeof(MiscReg));
            pkt->writeData(((uint8_t *)&data) + offset);
            xc->setMiscReg(index, gtoh(data));
            return Cycles(1);
        }
    }
}

#endif // __ARCH_X86_MMAPPEDIPR_HH__