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misc.hh
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1 /*
2  * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3  * All rights reserved.
4  *
5  * The license below extends only to copyright in the software and shall
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8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
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23  * this software without specific prior written permission.
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25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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36  *
37  * Authors: Gabe Black
38  */
39 
40 #ifndef __ARCH_X86_MISCREGS_HH__
41 #define __ARCH_X86_MISCREGS_HH__
42 
43 #include "arch/x86/regs/segment.hh"
44 #include "arch/x86/x86_traits.hh"
45 #include "base/bitunion.hh"
46 
47 //These get defined in some system headers (at least termbits.h). That confuses
48 //things here significantly.
49 #undef CR0
50 #undef CR2
51 #undef CR3
52 
53 namespace X86ISA
54 {
55  enum CondFlagBit {
56  CFBit = 1 << 0,
57  PFBit = 1 << 2,
58  ECFBit = 1 << 3,
59  AFBit = 1 << 4,
60  EZFBit = 1 << 5,
61  ZFBit = 1 << 6,
62  SFBit = 1 << 7,
63  DFBit = 1 << 10,
64  OFBit = 1 << 11
65  };
66 
67  const uint32_t cfofMask = CFBit | OFBit;
68  const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit;
69 
70  enum RFLAGBit {
71  TFBit = 1 << 8,
72  IFBit = 1 << 9,
73  NTBit = 1 << 14,
74  RFBit = 1 << 16,
75  VMBit = 1 << 17,
76  ACBit = 1 << 18,
77  VIFBit = 1 << 19,
78  VIPBit = 1 << 20,
79  IDBit = 1 << 21
80  };
81 
82  enum X87StatusBit {
83  // Exception Flags
84  IEBit = 1 << 0,
85  DEBit = 1 << 1,
86  ZEBit = 1 << 2,
87  OEBit = 1 << 3,
88  UEBit = 1 << 4,
89  PEBit = 1 << 5,
90 
91  // !Exception Flags
92  StackFaultBit = 1 << 6,
93  ErrSummaryBit = 1 << 7,
94  CC0Bit = 1 << 8,
95  CC1Bit = 1 << 9,
96  CC2Bit = 1 << 10,
97  CC3Bit = 1 << 14,
98  BusyBit = 1 << 15,
99  };
100 
102  {
103  // Control registers
104  // Most of these are invalid. See isValidMiscReg() below.
122 
123  // Debug registers
133 
134  // Flags register
136 
137  //Register to keep handy values like the CPU mode in.
139 
140  /*
141  * Model Specific Registers
142  */
143  // Time stamp counter
145 
147 
151 
155 
157 
162 
173 
184 
196 
198 
200 
211 
222 
233 
244 
245  // Extended feature enable register
247 
251 
253 
255 
257 
264 
271 
273 
278 
283 
286 
291 
292  /*
293  * Segment registers
294  */
295  // Segment selectors
310 
311  // Hidden segment base field
326 
327  // The effective segment base, ie what is actually added to an
328  // address. In 64 bit mode this can be different from the above,
329  // namely 0.
344 
345  // Hidden segment limit field
360 
361  // Hidden segment limit attributes
376 
377  // Floating point control registers
380 
391 
392  //XXX Add "Model-Specific Registers"
393 
395 
396  // "Fake" MSRs for internally implemented devices
398 
400  };
401 
402  static inline bool
404  {
405  return (index >= MISCREG_CR0 && index < NUM_MISCREGS &&
406  index != MISCREG_CR1 &&
407  !(index > MISCREG_CR4 && index < MISCREG_CR8) &&
408  !(index > MISCREG_CR8 && index <= MISCREG_CR15));
409  }
410 
411  static inline MiscRegIndex
413  {
414  assert(index >= 0 && index < NumCRegs);
415  return (MiscRegIndex)(MISCREG_CR_BASE + index);
416  }
417 
418  static inline MiscRegIndex
420  {
421  assert(index >= 0 && index < NumDRegs);
422  return (MiscRegIndex)(MISCREG_DR_BASE + index);
423  }
424 
425  static inline MiscRegIndex
427  {
428  assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END -
431  }
432 
433  static inline MiscRegIndex
435  {
436  assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END -
439  }
440 
441  static inline MiscRegIndex
443  {
444  assert(index >= 0 && index < (MISCREG_MC_CTL_END -
447  }
448 
449  static inline MiscRegIndex
451  {
452  assert(index >= 0 && index < (MISCREG_MC_STATUS_END -
455  }
456 
457  static inline MiscRegIndex
459  {
460  assert(index >= 0 && index < (MISCREG_MC_ADDR_END -
463  }
464 
465  static inline MiscRegIndex
467  {
468  assert(index >= 0 && index < (MISCREG_MC_MISC_END -
471  }
472 
473  static inline MiscRegIndex
475  {
476  assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END -
479  }
480 
481  static inline MiscRegIndex
483  {
484  assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END -
487  }
488 
489  static inline MiscRegIndex
491  {
492  assert(index >= 0 && index < (MISCREG_IORR_BASE_END -
495  }
496 
497  static inline MiscRegIndex
499  {
500  assert(index >= 0 && index < (MISCREG_IORR_MASK_END -
503  }
504 
505  static inline MiscRegIndex
507  {
508  assert(index >= 0 && index < NUM_SEGMENTREGS);
510  }
511 
512  static inline MiscRegIndex
514  {
515  assert(index >= 0 && index < NUM_SEGMENTREGS);
517  }
518 
519  static inline MiscRegIndex
521  {
522  assert(index >= 0 && index < NUM_SEGMENTREGS);
524  }
525 
526  static inline MiscRegIndex
528  {
529  assert(index >= 0 && index < NUM_SEGMENTREGS);
531  }
532 
533  static inline MiscRegIndex
535  {
536  assert(index >= 0 && index < NUM_SEGMENTREGS);
538  }
539 
544  BitUnion64(CCFlagBits)
545  Bitfield<11> of;
546  Bitfield<7> sf;
547  Bitfield<6> zf;
548  Bitfield<5> ezf;
549  Bitfield<4> af;
550  Bitfield<3> ecf;
551  Bitfield<2> pf;
552  Bitfield<0> cf;
553  EndBitUnion(CCFlagBits)
554 
558  BitUnion64(RFLAGS)
559  Bitfield<21> id; // ID Flag
560  Bitfield<20> vip; // Virtual Interrupt Pending
561  Bitfield<19> vif; // Virtual Interrupt Flag
562  Bitfield<18> ac; // Alignment Check
563  Bitfield<17> vm; // Virtual-8086 Mode
564  Bitfield<16> rf; // Resume Flag
565  Bitfield<14> nt; // Nested Task
566  Bitfield<13, 12> iopl; // I/O Privilege Level
567  Bitfield<11> of; // Overflow Flag
568  Bitfield<10> df; // Direction Flag
569  Bitfield<9> intf; // Interrupt Flag
570  Bitfield<8> tf; // Trap Flag
571  Bitfield<7> sf; // Sign Flag
572  Bitfield<6> zf; // Zero Flag
573  Bitfield<4> af; // Auxiliary Flag
574  Bitfield<2> pf; // Parity Flag
575  Bitfield<0> cf; // Carry Flag
576  EndBitUnion(RFLAGS)
577 
578  BitUnion64(HandyM5Reg)
579  Bitfield<0> mode;
580  Bitfield<3, 1> submode;
581  Bitfield<5, 4> cpl;
582  Bitfield<6> paging;
583  Bitfield<7> prot;
584  Bitfield<9, 8> defOp;
585  Bitfield<11, 10> altOp;
586  Bitfield<13, 12> defAddr;
587  Bitfield<15, 14> altAddr;
588  Bitfield<17, 16> stack;
589  EndBitUnion(HandyM5Reg)
590 
594  BitUnion64(CR0)
595  Bitfield<31> pg; // Paging
596  Bitfield<30> cd; // Cache Disable
597  Bitfield<29> nw; // Not Writethrough
598  Bitfield<18> am; // Alignment Mask
599  Bitfield<16> wp; // Write Protect
600  Bitfield<5> ne; // Numeric Error
601  Bitfield<4> et; // Extension Type
602  Bitfield<3> ts; // Task Switched
603  Bitfield<2> em; // Emulation
604  Bitfield<1> mp; // Monitor Coprocessor
605  Bitfield<0> pe; // Protection Enabled
606  EndBitUnion(CR0)
607 
608  // Page Fault Virtual Address
609  BitUnion64(CR2)
610  Bitfield<31, 0> legacy;
611  EndBitUnion(CR2)
612 
613  BitUnion64(CR3)
614  Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
615  // Base Address
616  Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
617  // Base Address
618  Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
619  // Base Address
620  Bitfield<4> pcd; // Page-Level Cache Disable
621  Bitfield<3> pwt; // Page-Level Writethrough
622  EndBitUnion(CR3)
623 
624  BitUnion64(CR4)
625  Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States
626  Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE,
627  // WRGSBASE instructions
628  Bitfield<10> osxmmexcpt; // Operating System Unmasked
629  // Exception Support
630  Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
631  Bitfield<8> pce; // Performance-Monitoring Counter Enable
632  Bitfield<7> pge; // Page-Global Enable
633  Bitfield<6> mce; // Machine Check Enable
634  Bitfield<5> pae; // Physical-Address Extension
635  Bitfield<4> pse; // Page Size Extensions
636  Bitfield<3> de; // Debugging Extensions
637  Bitfield<2> tsd; // Time Stamp Disable
638  Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
639  Bitfield<0> vme; // Virtual-8086 Mode Extensions
640  EndBitUnion(CR4)
641 
642  BitUnion64(CR8)
643  Bitfield<3, 0> tpr; // Task Priority Register
644  EndBitUnion(CR8)
645 
646  BitUnion64(DR6)
647  Bitfield<0> b0;
648  Bitfield<1> b1;
649  Bitfield<2> b2;
650  Bitfield<3> b3;
651  Bitfield<13> bd;
652  Bitfield<14> bs;
653  Bitfield<15> bt;
654  EndBitUnion(DR6)
655 
656  BitUnion64(DR7)
657  Bitfield<0> l0;
658  Bitfield<1> g0;
659  Bitfield<2> l1;
660  Bitfield<3> g1;
661  Bitfield<4> l2;
662  Bitfield<5> g2;
663  Bitfield<6> l3;
664  Bitfield<7> g3;
665  Bitfield<8> le;
666  Bitfield<9> ge;
667  Bitfield<13> gd;
668  Bitfield<17, 16> rw0;
669  Bitfield<19, 18> len0;
670  Bitfield<21, 20> rw1;
671  Bitfield<23, 22> len1;
672  Bitfield<25, 24> rw2;
673  Bitfield<27, 26> len2;
674  Bitfield<29, 28> rw3;
675  Bitfield<31, 30> len3;
676  EndBitUnion(DR7)
677 
678  // MTRR capabilities
679  BitUnion64(MTRRcap)
680  Bitfield<7, 0> vcnt; // Variable-Range Register Count
681  Bitfield<8> fix; // Fixed-Range Registers
682  Bitfield<10> wc; // Write-Combining
683  EndBitUnion(MTRRcap)
684 
688  BitUnion64(SysenterCS)
689  Bitfield<15, 0> targetCS;
690  EndBitUnion(SysenterCS)
691 
692  BitUnion64(SysenterESP)
693  Bitfield<31, 0> targetESP;
694  EndBitUnion(SysenterESP)
695 
696  BitUnion64(SysenterEIP)
697  Bitfield<31, 0> targetEIP;
698  EndBitUnion(SysenterEIP)
699 
703  BitUnion64(McgCap)
704  Bitfield<7, 0> count; // Number of error reporting register banks
705  Bitfield<8> MCGCP; // MCG_CTL register present.
706  EndBitUnion(McgCap)
707 
708  BitUnion64(McgStatus)
709  Bitfield<0> ripv; // Restart-IP valid
710  Bitfield<1> eipv; // Error-IP valid
711  Bitfield<2> mcip; // Machine check in-progress
712  EndBitUnion(McgStatus)
713 
714  BitUnion64(DebugCtlMsr)
715  Bitfield<0> lbr; // Last-branch record
716  Bitfield<1> btf; // Branch single step
717  Bitfield<2> pb0; // Performance monitoring pin control 0
718  Bitfield<3> pb1; // Performance monitoring pin control 1
719  Bitfield<4> pb2; // Performance monitoring pin control 2
720  Bitfield<5> pb3; // Performance monitoring pin control 3
721  /*uint64_t pb(int index)
722  {
723  return bits(__data, index + 2);
724  }*/
725  EndBitUnion(DebugCtlMsr)
726 
727  BitUnion64(MtrrPhysBase)
728  Bitfield<7, 0> type; // Default memory type
729  Bitfield<51, 12> physbase; // Range physical base address
730  EndBitUnion(MtrrPhysBase)
731 
732  BitUnion64(MtrrPhysMask)
733  Bitfield<11> valid; // MTRR pair enable
734  Bitfield<51, 12> physmask; // Range physical mask
735  EndBitUnion(MtrrPhysMask)
736 
737  BitUnion64(MtrrFixed)
738  /*uint64_t type(int index)
739  {
740  return bits(__data, index * 8 + 7, index * 8);
741  }*/
742  EndBitUnion(MtrrFixed)
743 
744  BitUnion64(Pat)
745  /*uint64_t pa(int index)
746  {
747  return bits(__data, index * 8 + 2, index * 8);
748  }*/
749  EndBitUnion(Pat)
750 
751  BitUnion64(MtrrDefType)
752  Bitfield<7, 0> type; // Default type
753  Bitfield<10> fe; // Fixed range enable
754  Bitfield<11> e; // MTRR enable
755  EndBitUnion(MtrrDefType)
756 
760  BitUnion64(McStatus)
761  Bitfield<15,0> mcaErrorCode;
762  Bitfield<31,16> modelSpecificCode;
763  Bitfield<56,32> otherInfo;
764  Bitfield<57> pcc; // Processor-context corrupt
765  Bitfield<58> addrv; // Error-address register valid
766  Bitfield<59> miscv; // Miscellaneous-error register valid
767  Bitfield<60> en; // Error condition enabled
768  Bitfield<61> uc; // Uncorrected error
769  Bitfield<62> over; // Status register overflow
770  Bitfield<63> val; // Valid
771  EndBitUnion(McStatus)
772 
773  BitUnion64(McCtl)
774  /*uint64_t en(int index)
775  {
776  return bits(__data, index);
777  }*/
778  EndBitUnion(McCtl)
779 
780  // Extended feature enable register
781  BitUnion64(Efer)
782  Bitfield<0> sce; // System call extensions
783  Bitfield<8> lme; // Long mode enable
784  Bitfield<10> lma; // Long mode active
785  Bitfield<11> nxe; // No-execute enable
786  Bitfield<12> svme; // Secure virtual machine enable
787  Bitfield<14> ffxsr; // Fast fxsave/fxrstor
788  EndBitUnion(Efer)
789 
790  BitUnion64(Star)
791  Bitfield<31,0> targetEip;
792  Bitfield<47,32> syscallCsAndSs;
793  Bitfield<63,48> sysretCsAndSs;
794  EndBitUnion(Star)
795 
796  BitUnion64(SfMask)
797  Bitfield<31,0> mask;
798  EndBitUnion(SfMask)
799 
800  BitUnion64(PerfEvtSel)
801  Bitfield<7,0> eventMask;
802  Bitfield<15,8> unitMask;
803  Bitfield<16> usr; // User mode
804  Bitfield<17> os; // Operating-system mode
805  Bitfield<18> e; // Edge detect
806  Bitfield<19> pc; // Pin control
807  Bitfield<20> intEn; // Interrupt enable
808  Bitfield<22> en; // Counter enable
809  Bitfield<23> inv; // Invert mask
810  Bitfield<31,24> counterMask;
811  EndBitUnion(PerfEvtSel)
812 
813  BitUnion32(Syscfg)
814  Bitfield<18> mfde; // MtrrFixDramEn
815  Bitfield<19> mfdm; // MtrrFixDramModEn
816  Bitfield<20> mvdm; // MtrrVarDramEn
817  Bitfield<21> tom2; // MtrrTom2En
818  EndBitUnion(Syscfg)
819 
820  BitUnion64(IorrBase)
821  Bitfield<3> wr; // WrMem Enable
822  Bitfield<4> rd; // RdMem Enable
823  Bitfield<51,12> physbase; // Range physical base address
824  EndBitUnion(IorrBase)
825 
826  BitUnion64(IorrMask)
827  Bitfield<11> v; // I/O register pair enable (valid)
828  Bitfield<51,12> physmask; // Range physical mask
829  EndBitUnion(IorrMask)
830 
831  BitUnion64(Tom)
832  Bitfield<51,23> physAddr; // Top of memory physical address
833  EndBitUnion(Tom)
834 
835  BitUnion64(VmCrMsr)
836  Bitfield<0> dpd;
837  Bitfield<1> rInit;
838  Bitfield<2> disA20M;
839  EndBitUnion(VmCrMsr)
840 
841  BitUnion64(IgnneMsr)
842  Bitfield<0> ignne;
843  EndBitUnion(IgnneMsr)
844 
845  BitUnion64(SmmCtlMsr)
846  Bitfield<0> dismiss;
847  Bitfield<1> enter;
848  Bitfield<2> smiCycle;
849  Bitfield<3> exit;
850  Bitfield<4> rsmCycle;
851  EndBitUnion(SmmCtlMsr)
852 
856  BitUnion64(SegSelector)
857  // The following bitfield is not defined in the ISA, but it's useful
858  // when checking selectors in larger data types to make sure they
859  // aren't too large.
860  Bitfield<63, 3> esi; // Extended selector
861  Bitfield<15, 3> si; // Selector Index
862  Bitfield<2> ti; // Table Indicator
863  Bitfield<1, 0> rpl; // Requestor Privilege Level
864  EndBitUnion(SegSelector)
865 
870  BitUnion64(SegDescriptor)
871  Bitfield<63, 56> baseHigh;
872  Bitfield<39, 16> baseLow;
873  Bitfield<55> g; // Granularity
874  Bitfield<54> d; // Default Operand Size
875  Bitfield<54> b; // Default Operand Size
876  Bitfield<53> l; // Long Attribute Bit
877  Bitfield<52> avl; // Available To Software
878  Bitfield<51, 48> limitHigh;
879  Bitfield<15, 0> limitLow;
880  Bitfield<47> p; // Present
881  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
882  Bitfield<44> s; // System
883  SubBitUnion(type, 43, 40)
884  // Specifies whether this descriptor is for code or data.
885  Bitfield<43> codeOrData;
886 
887  // These bit fields are for code segments
888  Bitfield<42> c; // Conforming
889  Bitfield<41> r; // Readable
890 
891  // These bit fields are for data segments
892  Bitfield<42> e; // Expand-Down
893  Bitfield<41> w; // Writable
894 
895  // This is used for both code and data segments.
896  Bitfield<40> a; // Accessed
897  EndSubBitUnion(type)
898  EndBitUnion(SegDescriptor)
899 
904  BitUnion64(TSSlow)
905  Bitfield<63, 56> baseHigh;
906  Bitfield<39, 16> baseLow;
907  Bitfield<55> g; // Granularity
908  Bitfield<52> avl; // Available To Software
909  Bitfield<51, 48> limitHigh;
910  Bitfield<15, 0> limitLow;
911  Bitfield<47> p; // Present
912  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
913  SubBitUnion(type, 43, 40)
914  // Specifies whether this descriptor is for code or data.
915  Bitfield<43> codeOrData;
916 
917  // These bit fields are for code segments
918  Bitfield<42> c; // Conforming
919  Bitfield<41> r; // Readable
920 
921  // These bit fields are for data segments
922  Bitfield<42> e; // Expand-Down
923  Bitfield<41> w; // Writable
924 
925  // This is used for both code and data segments.
926  Bitfield<40> a; // Accessed
927  EndSubBitUnion(type)
928  EndBitUnion(TSSlow)
929 
934  BitUnion64(TSShigh)
935  Bitfield<31, 0> base;
936  EndBitUnion(TSShigh)
937 
938  BitUnion64(SegAttr)
939  Bitfield<1, 0> dpl;
940  Bitfield<2> unusable;
941  Bitfield<3> defaultSize;
942  Bitfield<4> longMode;
943  Bitfield<5> avl;
944  Bitfield<6> granularity;
945  Bitfield<7> present;
946  Bitfield<11, 8> type;
947  Bitfield<12> writable;
948  Bitfield<13> readable;
949  Bitfield<14> expandDown;
950  Bitfield<15> system;
951  EndBitUnion(SegAttr)
952 
953  BitUnion64(GateDescriptor)
954  Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
955  Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
956  Bitfield<31, 16> selector; // Target Code-Segment Selector
957  Bitfield<47> p; // Present
958  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
959  Bitfield<43, 40> type;
960  Bitfield<36, 32> count; // Parameter Count
961  EndBitUnion(GateDescriptor)
962 
966  BitUnion64(GateDescriptorLow)
967  Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
968  Bitfield<47> p; // Present
969  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
970  Bitfield<43, 40> type;
971  Bitfield<35, 32> IST; // IST pointer to TSS -- new stack for exception handling
972  Bitfield<31, 16> selector; // Target Code-Segment Selector
973  Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
974  EndBitUnion(GateDescriptorLow)
975 
976  BitUnion64(GateDescriptorHigh)
977  Bitfield<31, 0> offset; // Target Code-Segment Offset
978  EndBitUnion(GateDescriptorHigh)
979 
983  BitUnion64(GDTR)
984  EndBitUnion(GDTR)
985 
986  BitUnion64(IDTR)
987  EndBitUnion(IDTR)
988 
989  BitUnion64(LDTR)
990  EndBitUnion(LDTR)
991 
995  BitUnion64(TR)
996  EndBitUnion(TR)
997 
998 
1002  BitUnion64(LocalApicBase)
1003  Bitfield<51, 12> base;
1004  Bitfield<11> enable;
1005  Bitfield<8> bsp;
1006  EndBitUnion(LocalApicBase)
1007 }
1008 
1009 #endif // __ARCH_X86_INTREGS_HH__
count
Definition: misc.hh:704
Bitfield< 14 > bs
Definition: misc.hh:652
targetCS
Definition: misc.hh:689
targetEip
Definition: misc.hh:791
Bitfield< 51, 48 > limitHigh
Definition: misc.hh:878
Bitfield< 19 > mfdm
Definition: misc.hh:815
Bitfield< 27, 26 > len2
Definition: misc.hh:673
Bitfield< 61 > uc
Definition: misc.hh:768
offset
Definition: misc.hh:977
Bitfield< 51, 12 > physmask
Definition: misc.hh:734
Bitfield< 19 > vif
Definition: misc.hh:561
Bitfield< 29, 28 > rw3
Definition: misc.hh:674
static MiscRegIndex MISCREG_PERF_EVT_CTR(int index)
Definition: misc.hh:482
Bitfield< 35, 32 > IST
Definition: misc.hh:971
vcnt
Definition: misc.hh:680
Bitfield< 5, 3 > index
Definition: types.hh:95
Bitfield< 57 > pcc
Definition: misc.hh:764
Bitfield< 17 > vm
Definition: misc.hh:563
Bitfield< 5 > ne
Definition: misc.hh:600
Bitfield< 5 > g2
Definition: misc.hh:662
Bitfield< 9 > ge
Definition: misc.hh:666
RFLAGBit
Definition: misc.hh:70
Bitfield< 13, 12 > defAddr
Definition: misc.hh:586
Bitfield< 8 > le
Definition: misc.hh:665
Bitfield< 20 > mvdm
Definition: misc.hh:816
Bitfield< 1 > rInit
Definition: misc.hh:837
Bitfield< 15, 8 > unitMask
Definition: misc.hh:802
Bitfield< 4 > pb2
Definition: misc.hh:719
Bitfield< 63, 48 > sysretCsAndSs
Definition: misc.hh:793
Bitfield< 14 > nt
Definition: misc.hh:565
X87StatusBit
Definition: misc.hh:82
Bitfield< 6 > d
Definition: pagetable.hh:89
EndBitUnion(TriggerIntMessage) namespace DeliveryMode
Definition: intmessage.hh:50
Bitfield< 3 > exit
Definition: misc.hh:849
Bitfield< 31, 12 > pdtb
Definition: misc.hh:616
Bitfield< 11 > nxe
Definition: misc.hh:785
Bitfield< 3 > ecf
Definition: misc.hh:550
Bitfield< 15, 14 > altAddr
Definition: misc.hh:587
Bitfield< 13 > gd
Definition: misc.hh:667
Bitfield< 47, 32 > syscallCsAndSs
Definition: misc.hh:792
physAddr
Definition: misc.hh:832
Bitfield< 46, 45 > dpl
Definition: misc.hh:881
Bitfield< 13 > bd
Definition: misc.hh:651
Bitfield< 11 > e
Definition: misc.hh:754
Bitfield< 9 > osfxsr
Definition: misc.hh:630
Bitfield< 3, 1 > submode
Definition: misc.hh:580
Bitfield< 2 > em
Definition: misc.hh:603
Bitfield< 6 > granularity
Definition: misc.hh:944
Bitfield< 1 > enter
Definition: misc.hh:847
Bitfield< 7 > present
Definition: misc.hh:945
Bitfield< 4 > l2
Definition: misc.hh:661
Bitfield< 3 > defaultSize
Definition: misc.hh:941
Bitfield< 23 > inv
Definition: misc.hh:809
Bitfield< 14 > expandDown
Definition: misc.hh:949
Bitfield< 39, 16 > baseLow
Definition: misc.hh:872
Bitfield< 19 > pc
Definition: misc.hh:806
Bitfield< 53 > l
Definition: misc.hh:876
Bitfield< 4, 0 > mode
Definition: miscregs.hh:1385
Bitfield< 7 > prot
Definition: misc.hh:583
Bitfield< 1 > b1
Definition: misc.hh:648
static bool isValidMiscReg(int index)
Definition: misc.hh:403
Bitfield< 10 > wc
Definition: misc.hh:682
Bitfield< 5 > pb3
Definition: misc.hh:720
Bitfield< 42 > c
Definition: misc.hh:888
Bitfield< 15, 0 > offsetLow
Definition: misc.hh:955
Bitfield< 17 > os
Definition: misc.hh:804
Bitfield< 15 > bt
Definition: misc.hh:653
Bitfield< 8 > MCGCP
Definition: misc.hh:705
Bitfield< 4 > longMode
Definition: misc.hh:942
Bitfield< 58 > addrv
Definition: misc.hh:765
MiscRegIndex
Definition: misc.hh:101
Bitfield< 18 > am
Definition: misc.hh:598
Bitfield< 1 > btf
Definition: misc.hh:716
Bitfield< 63 > val
Definition: misc.hh:770
Bitfield< 6, 3 > v
Definition: types.hh:122
Bitfield< 7 > sf
Definition: misc.hh:546
Bitfield< 20 > vip
Definition: misc.hh:560
Bitfield< 10 > osxmmexcpt
Definition: misc.hh:628
Bitfield< 0 > cf
Definition: misc.hh:552
Bitfield< 6 > paging
Definition: misc.hh:582
targetEIP
Definition: misc.hh:697
Bitfield< 20 > intEn
Definition: misc.hh:807
Bitfield< 7 > g3
Definition: misc.hh:664
Bitfield< 41 > r
Definition: misc.hh:889
Bitfield< 6 > mce
Definition: misc.hh:633
Bitfield< 11 > enable
Definition: misc.hh:1004
Bitfield< 13, 12 > iopl
Definition: misc.hh:566
const int NumDRegs
Definition: x86_traits.hh:62
Bitfield< 51, 12 > physbase
Definition: misc.hh:729
Bitfield< 16 > rf
Definition: misc.hh:564
Bitfield< 29 > nw
Definition: misc.hh:597
static MiscRegIndex MISCREG_SEG_ATTR(int index)
Definition: misc.hh:534
const int NumCRegs
Definition: x86_traits.hh:61
static MiscRegIndex MISCREG_CR(int index)
Definition: misc.hh:412
Bitfield< 18 > ac
Definition: misc.hh:562
Bitfield< 4 > rd
Definition: misc.hh:822
Bitfield< 25, 24 > rw2
Definition: misc.hh:672
Bitfield< 3 > pwt
Definition: pagetable.hh:92
static MiscRegIndex MISCREG_SEG_LIMIT(int index)
Definition: misc.hh:527
Bitfield< 31, 30 > len3
Definition: misc.hh:675
Bitfield< 3 > ts
Definition: misc.hh:602
Bitfield< 14 > ffxsr
Definition: misc.hh:787
Bitfield< 6 > zf
Definition: misc.hh:547
Bitfield< 10 > lma
Definition: misc.hh:784
mask
Definition: misc.hh:797
Bitfield< 1 > w
Definition: pagetable.hh:94
baseHigh
Definition: misc.hh:871
Bitfield< 51, 12 > base
Definition: pagetable.hh:85
Bitfield< 0 > pe
Definition: misc.hh:605
Bitfield< 1 > mp
Definition: misc.hh:604
Bitfield< 8 > pce
Definition: misc.hh:631
Bitfield< 31, 5 > paePdtb
Definition: misc.hh:618
BitUnion64(VAddr) Bitfield< 20
Bitfield< 62 > over
Definition: misc.hh:769
Bitfield< 9 > intf
Definition: misc.hh:569
Bitfield< 0 > vme
Definition: misc.hh:639
Bitfield< 3 > b3
Definition: misc.hh:650
Bitfield< 12 > svme
Definition: misc.hh:786
Bitfield< 31, 16 > selector
Definition: misc.hh:956
Bitfield< 59 > miscv
Definition: misc.hh:766
static MiscRegIndex MISCREG_MTRR_PHYS_BASE(int index)
Definition: misc.hh:426
BitUnion32(TriggerIntMessage) Bitfield<7
Bitfield< 16 > usr
Definition: misc.hh:803
Bitfield< 11 > of
Definition: misc.hh:567
EndSubBitUnion(type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63
TSS Descriptor (long mode - 128 bits) the lower 64 bits.
static MiscRegIndex MISCREG_SEG_SEL(int index)
Definition: misc.hh:506
Bitfield< 31, 24 > counterMask
Definition: misc.hh:810
Bitfield< 8 > bsp
Definition: misc.hh:1005
Bitfield< 2 > disA20M
Definition: misc.hh:838
Bitfield< 60 > en
Definition: misc.hh:767
Bitfield< 5 > a
Definition: pagetable.hh:90
Bitfield< 2 > pb0
Definition: misc.hh:717
Bitfield< 1, 0 > rpl
Definition: misc.hh:863
Bitfield< 15 > system
Definition: misc.hh:950
Bitfield< 5, 4 > cpl
Definition: misc.hh:581
Bitfield< 54 > b
Definition: misc.hh:875
offsetHigh
Definition: misc.hh:954
longPdtb
Definition: misc.hh:614
Bitfield< 16 > fsgsbase
Definition: misc.hh:626
Bitfield< 17, 16 > stack
Definition: misc.hh:588
Bitfield< 11, 9 > avl
Definition: pagetable.hh:86
Bitfield< 1 > pvi
Definition: misc.hh:638
Bitfield< 15, 0 > limitLow
Definition: misc.hh:879
Bitfield< 4 > af
Definition: misc.hh:549
Bitfield< 2 > ti
Definition: misc.hh:862
CondFlagBit
Definition: misc.hh:55
type
Definition: misc.hh:728
Bitfield< 3 > pb1
Definition: misc.hh:718
Bitfield< 4 > et
Definition: misc.hh:601
Bitfield< 21, 20 > rw1
Definition: misc.hh:670
Bitfield< 2 > l1
Definition: misc.hh:659
Bitfield< 6 > l3
Definition: misc.hh:663
static MiscRegIndex MISCREG_SEG_BASE(int index)
Definition: misc.hh:513
Bitfield< 1 > g0
Definition: misc.hh:658
Bitfield< 17, 16 > rw0
Definition: misc.hh:668
Bitfield< 3 > de
Definition: misc.hh:636
Bitfield< 4 > pse
Definition: misc.hh:635
Bitfield< 15, 3 > si
Definition: misc.hh:861
Bitfield< 44 > s
Definition: misc.hh:882
Bitfield< 9, 8 > defOp
Definition: misc.hh:584
Bitfield< 31, 16 > modelSpecificCode
Definition: misc.hh:762
static MiscRegIndex MISCREG_MTRR_PHYS_MASK(int index)
Definition: misc.hh:434
static MiscRegIndex MISCREG_PERF_EVT_SEL(int index)
Definition: misc.hh:474
SubBitUnion(type, 43, 40) Bitfield< 43 > codeOrData
static MiscRegIndex MISCREG_MC_ADDR(int index)
Definition: misc.hh:458
static MiscRegIndex MISCREG_MC_CTL(int index)
Definition: misc.hh:442
Bitfield< 2 > b2
Definition: misc.hh:649
Bitfield< 2 > tsd
Definition: misc.hh:637
Bitfield< 4 > pcd
Definition: pagetable.hh:91
Bitfield< 5 > pae
Definition: misc.hh:634
mcaErrorCode
Definition: misc.hh:761
Bitfield< 19, 18 > len0
Definition: misc.hh:669
Bitfield< 13 > readable
Definition: misc.hh:948
static MiscRegIndex MISCREG_SEG_EFF_BASE(int index)
Definition: misc.hh:520
Bitfield< 56, 32 > otherInfo
Definition: misc.hh:763
static MiscRegIndex MISCREG_IORR_BASE(int index)
Definition: misc.hh:490
static MiscRegIndex MISCREG_IORR_MASK(int index)
Definition: misc.hh:498
Bitfield< 3 > wr
Bitfield< 0 > p
Definition: pagetable.hh:95
Bitfield< 8 > fix
Definition: misc.hh:681
Bitfield< 2 > mcip
Definition: misc.hh:711
const uint32_t ccFlagMask
Definition: misc.hh:68
Bitfield< 8 > tf
Definition: misc.hh:570
bool writable
Definition: pagetable.hh:111
static MiscRegIndex MISCREG_MC_MISC(int index)
Definition: misc.hh:466
Bitfield< 2 > pf
Definition: misc.hh:551
static MiscRegIndex MISCREG_MC_STATUS(int index)
Definition: misc.hh:450
Bitfield< 8 > lme
Definition: misc.hh:783
esi
Definition: misc.hh:860
Bitfield< 23, 22 > len1
Definition: misc.hh:671
Bitfield< 8 > g
Definition: pagetable.hh:87
static MiscRegIndex MISCREG_DR(int index)
Definition: misc.hh:419
const uint32_t cfofMask
Definition: misc.hh:67
Bitfield< 11, 10 > altOp
Definition: misc.hh:585
legacy
Definition: misc.hh:610
Bitfield< 2 > unusable
Definition: misc.hh:940
Bitfield< 3 > g1
Definition: misc.hh:660
Bitfield< 2 > smiCycle
Definition: misc.hh:848
Bitfield< 5 > ezf
Definition: misc.hh:548
Bitfield< 7 > pge
Definition: misc.hh:632
targetESP
Definition: misc.hh:693
tpr
Definition: misc.hh:643
Bitfield< 16 > wp
Definition: misc.hh:599
Bitfield< 4 > rsmCycle
Definition: misc.hh:850
Bitfield< 10 > df
Definition: misc.hh:568
Bitfield< 30 > cd
Definition: misc.hh:596
Bitfield< 10 > fe
Definition: misc.hh:753
Bitfield< 21 > tom2
Definition: misc.hh:817
eventMask
Definition: misc.hh:801
Bitfield< 1 > eipv
Definition: misc.hh:710

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