ArmISA Namespace Reference

Namespaces
	Kernel

Classes
class	Decoder
class	ArmFault
class	ArmFaultVals
class	Reset
class	UndefinedInstruction
class	SupervisorCall
class	SecureMonitorCall
class	SupervisorTrap
class	SecureMonitorTrap
class	HypervisorCall
class	HypervisorTrap
class	AbortFault
class	PrefetchAbort
class	DataAbort
class	VirtualDataAbort
class	Interrupt
class	VirtualInterrupt
class	FastInterrupt
class	VirtualFastInterrupt
class	PCAlignmentFault
	PC alignment fault (AArch64 only) More...
class	SPAlignmentFault
	Stack pointer alignment fault (AArch64 only) More...
class	SystemError
	System error (AArch64 only) More...
class	FlushPipe
class	ArmSev
class	IllegalInstSetStateFault
	Illegal Instruction Set State fault (AArch64 only) More...
class	BranchImm
class	BranchImmCond
class	BranchReg
class	BranchRegCond
class	BranchRegReg
class	BranchImmReg
class	BranchImm64
class	BranchImmCond64
class	BranchReg64
class	BranchRet64
class	BranchEret64
class	BranchImmReg64
class	BranchImmImmReg64
class	DataXImmOp
class	DataXImmOnlyOp
class	DataXSRegOp
class	DataXERegOp
class	DataX1RegOp
class	DataX1RegImmOp
class	DataX1Reg2ImmOp
class	DataX2RegOp
class	DataX2RegImmOp
class	DataX3RegOp
class	DataXCondCompImmOp
class	DataXCondCompRegOp
class	DataXCondSelOp
class	MicroOp
	Base class for Memory microops. More...
class	MicroOpX
class	MicroNeonMemOp
	Microops for Neon loads/stores. More...
class	MicroNeonMixOp
	Microops for Neon load/store (de)interleaving. More...
class	MicroNeonMixLaneOp
class	MicroNeonMixOp64
	Microops for AArch64 NEON load/store (de)interleaving. More...
class	MicroNeonMixLaneOp64
class	VldMultOp64
	Base classes for microcoded AArch64 NEON memory instructions. More...
class	VstMultOp64
class	VldSingleOp64
class	VstSingleOp64
class	MicroSetPCCPSR
	Microops of the form PC = IntRegA CPSR = IntRegB. More...
class	MicroIntMov
	Microops of the form IntRegA = IntRegB. More...
class	MicroIntImmOp
	Microops of the form IntRegA = IntRegB op Imm. More...
class	MicroIntImmXOp
class	MicroIntOp
	Microops of the form IntRegA = IntRegB op IntRegC. More...
class	MicroIntRegXOp
class	MicroIntRegOp
	Microops of the form IntRegA = IntRegB op shifted IntRegC. More...
class	MicroMemOp
	Memory microops which use IntReg + Imm addressing. More...
class	MicroMemPairOp
class	MacroMemOp
	Base class for microcoded integer memory instructions. More...
class	PairMemOp
	Base class for pair load/store instructions. More...
class	BigFpMemImmOp
class	BigFpMemPostOp
class	BigFpMemPreOp
class	BigFpMemRegOp
class	BigFpMemLitOp
class	VldMultOp
	Base classes for microcoded integer memory instructions. More...
class	VldSingleOp
class	VstMultOp
	Base class for microcoded integer memory instructions. More...
class	VstSingleOp
class	MacroVFPMemOp
	Base class for microcoded floating point memory instructions. More...
class	Swap
class	MightBeMicro
class	RfeOp
class	SrsOp
class	Memory
class	MemoryImm
class	MemoryExImm
class	MemoryDImm
class	MemoryExDImm
class	MemoryReg
class	MemoryDReg
class	MemoryOffset
class	MemoryPreIndex
class	MemoryPostIndex
class	SysDC64
class	MightBeMicro64
class	Memory64
class	MemoryImm64
class	MemoryDImm64
class	MemoryDImmEx64
class	MemoryPreIndex64
class	MemoryPostIndex64
class	MemoryReg64
class	MemoryRaw64
class	MemoryEx64
class	MemoryLiteral64
class	Mult3
	Base class for multipy instructions using three registers. More...
class	Mult4
	Base class for multipy instructions using four registers. More...
struct	VReg
	128-bit NEON vector register. More...
class	PredOp
	Base class for predicated integer operations. More...
class	PredImmOp
	Base class for predicated immediate operations. More...
class	PredIntOp
	Base class for predicated integer operations. More...
class	DataImmOp
class	DataRegOp
class	DataRegRegOp
class	PredMacroOp
	Base class for predicated macro-operations. More...
class	PredMicroop
	Base class for predicated micro-operations. More...
class	ArmStaticInst
class	VfpMacroOp
class	FpOp
class	FpCondCompRegOp
class	FpCondSelOp
class	FpRegRegOp
class	FpRegImmOp
class	FpRegRegImmOp
class	FpRegRegRegOp
class	FpRegRegRegCondOp
class	FpRegRegRegRegOp
class	FpRegRegRegImmOp
class	Interrupts
class	ISA
	Some registers alias with others, and therefore need to be translated. More...
class	BaseISADevice
	Base class for devices that use the MiscReg interfaces. More...
class	DummyISADevice
	Dummy device that prints a warning when it is accessed. More...
struct	VAddr
struct	PTE
struct	TlbEntry
class	PMU
	Model of an ARM PMU version 3. More...
union	AnyReg
class	RemoteGDB
class	ProcessInfo
class	StackTrace
class	Stage2LookUp
class	Stage2MMU
class	TableWalker
class	TlbTestInterface
class	TLB

Typedefs
typedef Addr	FaultOffset
typedef uint64_t	XReg
typedef int	VfpSavedState
typedef IntRegIndex	IntRegMap [NUM_ARCH_INTREGS]
typedef uint16_t	RegIndex
typedef uint64_t	IntReg
typedef uint32_t	FloatRegBits
typedef float	FloatReg
typedef uint64_t	MiscReg
typedef uint64_t	CCReg
typedef uint32_t	MachInst
typedef int	RegContextParam
typedef int	RegContextVal

Enumerations
enum	ccRegIndex {   CCREG_NZ, CCREG_C, CCREG_V, CCREG_GE,   CCREG_FP, CCREG_ZERO, NUM_CCREGS }
enum	ConditionCode {   COND_EQ = 0, COND_NE, COND_CS, COND_CC,   COND_MI, COND_PL, COND_VS, COND_VC,   COND_HI, COND_LS, COND_GE, COND_LT,   COND_GT, COND_LE, COND_AL, COND_UC }
enum	FPRounding {   FPRounding_TIEEVEN = 0, FPRounding_POSINF = 1, FPRounding_NEGINF = 2, FPRounding_ZERO = 3,   FPRounding_TIEAWAY = 4, FPRounding_ODD = 5 }
enum	VfpMicroMode { VfpNotAMicroop, VfpMicroop, VfpFirstMicroop, VfpLastMicroop }
enum	FeExceptionBit {   FeDivByZero = FE_DIVBYZERO, FeInexact = FE_INEXACT, FeInvalid = FE_INVALID, FeOverflow = FE_OVERFLOW,   FeUnderflow = FE_UNDERFLOW, FeAllExceptions = FE_ALL_EXCEPT }
enum	FeRoundingMode { FeRoundDown = FE_DOWNWARD, FeRoundNearest = FE_TONEAREST, FeRoundZero = FE_TOWARDZERO, FeRoundUpward = FE_UPWARD }
enum	VfpRoundingMode {   VfpRoundNearest = 0, VfpRoundUpward = 1, VfpRoundDown = 2, VfpRoundZero = 3,   VfpRoundAway = 4 }
enum	IntRegIndex {   INTREG_R0, INTREG_R1, INTREG_R2, INTREG_R3,   INTREG_R4, INTREG_R5, INTREG_R6, INTREG_R7,   INTREG_R8, INTREG_R9, INTREG_R10, INTREG_R11,   INTREG_R12, INTREG_R13, INTREG_SP = INTREG_R13, INTREG_R14,   INTREG_LR = INTREG_R14, INTREG_R15, INTREG_PC = INTREG_R15, INTREG_R13_SVC,   INTREG_SP_SVC = INTREG_R13_SVC, INTREG_R14_SVC, INTREG_LR_SVC = INTREG_R14_SVC, INTREG_R13_MON,   INTREG_SP_MON = INTREG_R13_MON, INTREG_R14_MON, INTREG_LR_MON = INTREG_R14_MON, INTREG_R13_HYP,   INTREG_SP_HYP = INTREG_R13_HYP, INTREG_R13_ABT, INTREG_SP_ABT = INTREG_R13_ABT, INTREG_R14_ABT,   INTREG_LR_ABT = INTREG_R14_ABT, INTREG_R13_UND, INTREG_SP_UND = INTREG_R13_UND, INTREG_R14_UND,   INTREG_LR_UND = INTREG_R14_UND, INTREG_R13_IRQ, INTREG_SP_IRQ = INTREG_R13_IRQ, INTREG_R14_IRQ,   INTREG_LR_IRQ = INTREG_R14_IRQ, INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ,   INTREG_R11_FIQ, INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_SP_FIQ = INTREG_R13_FIQ,   INTREG_R14_FIQ, INTREG_LR_FIQ = INTREG_R14_FIQ, INTREG_ZERO, INTREG_UREG0,   INTREG_UREG1, INTREG_UREG2, INTREG_DUMMY, INTREG_SP0,   INTREG_SP1, INTREG_SP2, INTREG_SP3, NUM_INTREGS,   NUM_ARCH_INTREGS = 32, INTREG_X0 = 0, INTREG_X1, INTREG_X2,   INTREG_X3, INTREG_X4, INTREG_X5, INTREG_X6,   INTREG_X7, INTREG_X8, INTREG_X9, INTREG_X10,   INTREG_X11, INTREG_X12, INTREG_X13, INTREG_X14,   INTREG_X15, INTREG_X16, INTREG_X17, INTREG_X18,   INTREG_X19, INTREG_X20, INTREG_X21, INTREG_X22,   INTREG_X23, INTREG_X24, INTREG_X25, INTREG_X26,   INTREG_X27, INTREG_X28, INTREG_X29, INTREG_X30,   INTREG_X31, INTREG_SPX = NUM_INTREGS, INTREG_R0_USR = INTREG_R0, INTREG_R1_USR = INTREG_R1,   INTREG_R2_USR = INTREG_R2, INTREG_R3_USR = INTREG_R3, INTREG_R4_USR = INTREG_R4, INTREG_R5_USR = INTREG_R5,   INTREG_R6_USR = INTREG_R6, INTREG_R7_USR = INTREG_R7, INTREG_R8_USR = INTREG_R8, INTREG_R9_USR = INTREG_R9,   INTREG_R10_USR = INTREG_R10, INTREG_R11_USR = INTREG_R11, INTREG_R12_USR = INTREG_R12, INTREG_R13_USR = INTREG_R13,   INTREG_SP_USR = INTREG_SP, INTREG_R14_USR = INTREG_R14, INTREG_LR_USR = INTREG_LR, INTREG_R15_USR = INTREG_R15,   INTREG_PC_USR = INTREG_PC, INTREG_R0_SVC = INTREG_R0, INTREG_R1_SVC = INTREG_R1, INTREG_R2_SVC = INTREG_R2,   INTREG_R3_SVC = INTREG_R3, INTREG_R4_SVC = INTREG_R4, INTREG_R5_SVC = INTREG_R5, INTREG_R6_SVC = INTREG_R6,   INTREG_R7_SVC = INTREG_R7, INTREG_R8_SVC = INTREG_R8, INTREG_R9_SVC = INTREG_R9, INTREG_R10_SVC = INTREG_R10,   INTREG_R11_SVC = INTREG_R11, INTREG_R12_SVC = INTREG_R12, INTREG_PC_SVC = INTREG_PC, INTREG_R15_SVC = INTREG_R15,   INTREG_R0_MON = INTREG_R0, INTREG_R1_MON = INTREG_R1, INTREG_R2_MON = INTREG_R2, INTREG_R3_MON = INTREG_R3,   INTREG_R4_MON = INTREG_R4, INTREG_R5_MON = INTREG_R5, INTREG_R6_MON = INTREG_R6, INTREG_R7_MON = INTREG_R7,   INTREG_R8_MON = INTREG_R8, INTREG_R9_MON = INTREG_R9, INTREG_R10_MON = INTREG_R10, INTREG_R11_MON = INTREG_R11,   INTREG_R12_MON = INTREG_R12, INTREG_PC_MON = INTREG_PC, INTREG_R15_MON = INTREG_R15, INTREG_R0_ABT = INTREG_R0,   INTREG_R1_ABT = INTREG_R1, INTREG_R2_ABT = INTREG_R2, INTREG_R3_ABT = INTREG_R3, INTREG_R4_ABT = INTREG_R4,   INTREG_R5_ABT = INTREG_R5, INTREG_R6_ABT = INTREG_R6, INTREG_R7_ABT = INTREG_R7, INTREG_R8_ABT = INTREG_R8,   INTREG_R9_ABT = INTREG_R9, INTREG_R10_ABT = INTREG_R10, INTREG_R11_ABT = INTREG_R11, INTREG_R12_ABT = INTREG_R12,   INTREG_PC_ABT = INTREG_PC, INTREG_R15_ABT = INTREG_R15, INTREG_R0_HYP = INTREG_R0, INTREG_R1_HYP = INTREG_R1,   INTREG_R2_HYP = INTREG_R2, INTREG_R3_HYP = INTREG_R3, INTREG_R4_HYP = INTREG_R4, INTREG_R5_HYP = INTREG_R5,   INTREG_R6_HYP = INTREG_R6, INTREG_R7_HYP = INTREG_R7, INTREG_R8_HYP = INTREG_R8, INTREG_R9_HYP = INTREG_R9,   INTREG_R10_HYP = INTREG_R10, INTREG_R11_HYP = INTREG_R11, INTREG_R12_HYP = INTREG_R12, INTREG_LR_HYP = INTREG_LR,   INTREG_R14_HYP = INTREG_R14, INTREG_PC_HYP = INTREG_PC, INTREG_R15_HYP = INTREG_R15, INTREG_R0_UND = INTREG_R0,   INTREG_R1_UND = INTREG_R1, INTREG_R2_UND = INTREG_R2, INTREG_R3_UND = INTREG_R3, INTREG_R4_UND = INTREG_R4,   INTREG_R5_UND = INTREG_R5, INTREG_R6_UND = INTREG_R6, INTREG_R7_UND = INTREG_R7, INTREG_R8_UND = INTREG_R8,   INTREG_R9_UND = INTREG_R9, INTREG_R10_UND = INTREG_R10, INTREG_R11_UND = INTREG_R11, INTREG_R12_UND = INTREG_R12,   INTREG_PC_UND = INTREG_PC, INTREG_R15_UND = INTREG_R15, INTREG_R0_IRQ = INTREG_R0, INTREG_R1_IRQ = INTREG_R1,   INTREG_R2_IRQ = INTREG_R2, INTREG_R3_IRQ = INTREG_R3, INTREG_R4_IRQ = INTREG_R4, INTREG_R5_IRQ = INTREG_R5,   INTREG_R6_IRQ = INTREG_R6, INTREG_R7_IRQ = INTREG_R7, INTREG_R8_IRQ = INTREG_R8, INTREG_R9_IRQ = INTREG_R9,   INTREG_R10_IRQ = INTREG_R10, INTREG_R11_IRQ = INTREG_R11, INTREG_R12_IRQ = INTREG_R12, INTREG_PC_IRQ = INTREG_PC,   INTREG_R15_IRQ = INTREG_R15, INTREG_R0_FIQ = INTREG_R0, INTREG_R1_FIQ = INTREG_R1, INTREG_R2_FIQ = INTREG_R2,   INTREG_R3_FIQ = INTREG_R3, INTREG_R4_FIQ = INTREG_R4, INTREG_R5_FIQ = INTREG_R5, INTREG_R6_FIQ = INTREG_R6,   INTREG_R7_FIQ = INTREG_R7, INTREG_PC_FIQ = INTREG_PC, INTREG_R15_FIQ = INTREG_R15 }
enum	InterruptTypes {   INT_RST, INT_ABT, INT_IRQ, INT_FIQ,   INT_SEV, INT_VIRT_IRQ, INT_VIRT_FIQ, NumInterruptTypes }
enum	MiscRegIndex {   MISCREG_CPSR = 0, MISCREG_SPSR, MISCREG_SPSR_FIQ, MISCREG_SPSR_IRQ,   MISCREG_SPSR_SVC, MISCREG_SPSR_MON, MISCREG_SPSR_ABT, MISCREG_SPSR_HYP,   MISCREG_SPSR_UND, MISCREG_ELR_HYP, MISCREG_FPSID, MISCREG_FPSCR,   MISCREG_MVFR1, MISCREG_MVFR0, MISCREG_FPEXC, MISCREG_CPSR_MODE,   MISCREG_CPSR_Q, MISCREG_FPSCR_EXC, MISCREG_FPSCR_QC, MISCREG_LOCKADDR,   MISCREG_LOCKFLAG, MISCREG_PRRR_MAIR0, MISCREG_PRRR_MAIR0_NS, MISCREG_PRRR_MAIR0_S,   MISCREG_NMRR_MAIR1, MISCREG_NMRR_MAIR1_NS, MISCREG_NMRR_MAIR1_S, MISCREG_PMXEVTYPER_PMCCFILTR,   MISCREG_SCTLR_RST, MISCREG_SEV_MAILBOX, MISCREG_DBGDIDR, MISCREG_DBGDSCRint,   MISCREG_DBGDCCINT, MISCREG_DBGDTRTXint, MISCREG_DBGDTRRXint, MISCREG_DBGWFAR,   MISCREG_DBGVCR, MISCREG_DBGDTRRXext, MISCREG_DBGDSCRext, MISCREG_DBGDTRTXext,   MISCREG_DBGOSECCR, MISCREG_DBGBVR0, MISCREG_DBGBVR1, MISCREG_DBGBVR2,   MISCREG_DBGBVR3, MISCREG_DBGBVR4, MISCREG_DBGBVR5, MISCREG_DBGBCR0,   MISCREG_DBGBCR1, MISCREG_DBGBCR2, MISCREG_DBGBCR3, MISCREG_DBGBCR4,   MISCREG_DBGBCR5, MISCREG_DBGWVR0, MISCREG_DBGWVR1, MISCREG_DBGWVR2,   MISCREG_DBGWVR3, MISCREG_DBGWCR0, MISCREG_DBGWCR1, MISCREG_DBGWCR2,   MISCREG_DBGWCR3, MISCREG_DBGDRAR, MISCREG_DBGBXVR4, MISCREG_DBGBXVR5,   MISCREG_DBGOSLAR, MISCREG_DBGOSLSR, MISCREG_DBGOSDLR, MISCREG_DBGPRCR,   MISCREG_DBGDSAR, MISCREG_DBGCLAIMSET, MISCREG_DBGCLAIMCLR, MISCREG_DBGAUTHSTATUS,   MISCREG_DBGDEVID2, MISCREG_DBGDEVID1, MISCREG_DBGDEVID0, MISCREG_TEECR,   MISCREG_JIDR, MISCREG_TEEHBR, MISCREG_JOSCR, MISCREG_JMCR,   MISCREG_MIDR, MISCREG_CTR, MISCREG_TCMTR, MISCREG_TLBTR,   MISCREG_MPIDR, MISCREG_REVIDR, MISCREG_ID_PFR0, MISCREG_ID_PFR1,   MISCREG_ID_DFR0, MISCREG_ID_AFR0, MISCREG_ID_MMFR0, MISCREG_ID_MMFR1,   MISCREG_ID_MMFR2, MISCREG_ID_MMFR3, MISCREG_ID_ISAR0, MISCREG_ID_ISAR1,   MISCREG_ID_ISAR2, MISCREG_ID_ISAR3, MISCREG_ID_ISAR4, MISCREG_ID_ISAR5,   MISCREG_CCSIDR, MISCREG_CLIDR, MISCREG_AIDR, MISCREG_CSSELR,   MISCREG_CSSELR_NS, MISCREG_CSSELR_S, MISCREG_VPIDR, MISCREG_VMPIDR,   MISCREG_SCTLR, MISCREG_SCTLR_NS, MISCREG_SCTLR_S, MISCREG_ACTLR,   MISCREG_ACTLR_NS, MISCREG_ACTLR_S, MISCREG_CPACR, MISCREG_SCR,   MISCREG_SDER, MISCREG_NSACR, MISCREG_HSCTLR, MISCREG_HACTLR,   MISCREG_HCR, MISCREG_HDCR, MISCREG_HCPTR, MISCREG_HSTR,   MISCREG_HACR, MISCREG_TTBR0, MISCREG_TTBR0_NS, MISCREG_TTBR0_S,   MISCREG_TTBR1, MISCREG_TTBR1_NS, MISCREG_TTBR1_S, MISCREG_TTBCR,   MISCREG_TTBCR_NS, MISCREG_TTBCR_S, MISCREG_HTCR, MISCREG_VTCR,   MISCREG_DACR, MISCREG_DACR_NS, MISCREG_DACR_S, MISCREG_DFSR,   MISCREG_DFSR_NS, MISCREG_DFSR_S, MISCREG_IFSR, MISCREG_IFSR_NS,   MISCREG_IFSR_S, MISCREG_ADFSR, MISCREG_ADFSR_NS, MISCREG_ADFSR_S,   MISCREG_AIFSR, MISCREG_AIFSR_NS, MISCREG_AIFSR_S, MISCREG_HADFSR,   MISCREG_HAIFSR, MISCREG_HSR, MISCREG_DFAR, MISCREG_DFAR_NS,   MISCREG_DFAR_S, MISCREG_IFAR, MISCREG_IFAR_NS, MISCREG_IFAR_S,   MISCREG_HDFAR, MISCREG_HIFAR, MISCREG_HPFAR, MISCREG_ICIALLUIS,   MISCREG_BPIALLIS, MISCREG_PAR, MISCREG_PAR_NS, MISCREG_PAR_S,   MISCREG_ICIALLU, MISCREG_ICIMVAU, MISCREG_CP15ISB, MISCREG_BPIALL,   MISCREG_BPIMVA, MISCREG_DCIMVAC, MISCREG_DCISW, MISCREG_ATS1CPR,   MISCREG_ATS1CPW, MISCREG_ATS1CUR, MISCREG_ATS1CUW, MISCREG_ATS12NSOPR,   MISCREG_ATS12NSOPW, MISCREG_ATS12NSOUR, MISCREG_ATS12NSOUW, MISCREG_DCCMVAC,   MISCREG_DCCSW, MISCREG_CP15DSB, MISCREG_CP15DMB, MISCREG_DCCMVAU,   MISCREG_DCCIMVAC, MISCREG_DCCISW, MISCREG_ATS1HR, MISCREG_ATS1HW,   MISCREG_TLBIALLIS, MISCREG_TLBIMVAIS, MISCREG_TLBIASIDIS, MISCREG_TLBIMVAAIS,   MISCREG_TLBIMVALIS, MISCREG_TLBIMVAALIS, MISCREG_ITLBIALL, MISCREG_ITLBIMVA,   MISCREG_ITLBIASID, MISCREG_DTLBIALL, MISCREG_DTLBIMVA, MISCREG_DTLBIASID,   MISCREG_TLBIALL, MISCREG_TLBIMVA, MISCREG_TLBIASID, MISCREG_TLBIMVAA,   MISCREG_TLBIMVAL, MISCREG_TLBIMVAAL, MISCREG_TLBIIPAS2IS, MISCREG_TLBIIPAS2LIS,   MISCREG_TLBIALLHIS, MISCREG_TLBIMVAHIS, MISCREG_TLBIALLNSNHIS, MISCREG_TLBIMVALHIS,   MISCREG_TLBIIPAS2, MISCREG_TLBIIPAS2L, MISCREG_TLBIALLH, MISCREG_TLBIMVAH,   MISCREG_TLBIALLNSNH, MISCREG_TLBIMVALH, MISCREG_PMCR, MISCREG_PMCNTENSET,   MISCREG_PMCNTENCLR, MISCREG_PMOVSR, MISCREG_PMSWINC, MISCREG_PMSELR,   MISCREG_PMCEID0, MISCREG_PMCEID1, MISCREG_PMCCNTR, MISCREG_PMXEVTYPER,   MISCREG_PMCCFILTR, MISCREG_PMXEVCNTR, MISCREG_PMUSERENR, MISCREG_PMINTENSET,   MISCREG_PMINTENCLR, MISCREG_PMOVSSET, MISCREG_L2CTLR, MISCREG_L2ECTLR,   MISCREG_PRRR, MISCREG_PRRR_NS, MISCREG_PRRR_S, MISCREG_MAIR0,   MISCREG_MAIR0_NS, MISCREG_MAIR0_S, MISCREG_NMRR, MISCREG_NMRR_NS,   MISCREG_NMRR_S, MISCREG_MAIR1, MISCREG_MAIR1_NS, MISCREG_MAIR1_S,   MISCREG_AMAIR0, MISCREG_AMAIR0_NS, MISCREG_AMAIR0_S, MISCREG_AMAIR1,   MISCREG_AMAIR1_NS, MISCREG_AMAIR1_S, MISCREG_HMAIR0, MISCREG_HMAIR1,   MISCREG_HAMAIR0, MISCREG_HAMAIR1, MISCREG_VBAR, MISCREG_VBAR_NS,   MISCREG_VBAR_S, MISCREG_MVBAR, MISCREG_RMR, MISCREG_ISR,   MISCREG_HVBAR, MISCREG_FCSEIDR, MISCREG_CONTEXTIDR, MISCREG_CONTEXTIDR_NS,   MISCREG_CONTEXTIDR_S, MISCREG_TPIDRURW, MISCREG_TPIDRURW_NS, MISCREG_TPIDRURW_S,   MISCREG_TPIDRURO, MISCREG_TPIDRURO_NS, MISCREG_TPIDRURO_S, MISCREG_TPIDRPRW,   MISCREG_TPIDRPRW_NS, MISCREG_TPIDRPRW_S, MISCREG_HTPIDR, MISCREG_CNTFRQ,   MISCREG_CNTKCTL, MISCREG_CNTP_TVAL, MISCREG_CNTP_TVAL_NS, MISCREG_CNTP_TVAL_S,   MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_NS, MISCREG_CNTP_CTL_S, MISCREG_CNTV_TVAL,   MISCREG_CNTV_CTL, MISCREG_CNTHCTL, MISCREG_CNTHP_TVAL, MISCREG_CNTHP_CTL,   MISCREG_IL1DATA0, MISCREG_IL1DATA1, MISCREG_IL1DATA2, MISCREG_IL1DATA3,   MISCREG_DL1DATA0, MISCREG_DL1DATA1, MISCREG_DL1DATA2, MISCREG_DL1DATA3,   MISCREG_DL1DATA4, MISCREG_RAMINDEX, MISCREG_L2ACTLR, MISCREG_CBAR,   MISCREG_HTTBR, MISCREG_VTTBR, MISCREG_CNTPCT, MISCREG_CNTVCT,   MISCREG_CNTP_CVAL, MISCREG_CNTP_CVAL_NS, MISCREG_CNTP_CVAL_S, MISCREG_CNTV_CVAL,   MISCREG_CNTVOFF, MISCREG_CNTHP_CVAL, MISCREG_CPUMERRSR, MISCREG_L2MERRSR,   MISCREG_MDCCINT_EL1, MISCREG_OSDTRRX_EL1, MISCREG_MDSCR_EL1, MISCREG_OSDTRTX_EL1,   MISCREG_OSECCR_EL1, MISCREG_DBGBVR0_EL1, MISCREG_DBGBVR1_EL1, MISCREG_DBGBVR2_EL1,   MISCREG_DBGBVR3_EL1, MISCREG_DBGBVR4_EL1, MISCREG_DBGBVR5_EL1, MISCREG_DBGBCR0_EL1,   MISCREG_DBGBCR1_EL1, MISCREG_DBGBCR2_EL1, MISCREG_DBGBCR3_EL1, MISCREG_DBGBCR4_EL1,   MISCREG_DBGBCR5_EL1, MISCREG_DBGWVR0_EL1, MISCREG_DBGWVR1_EL1, MISCREG_DBGWVR2_EL1,   MISCREG_DBGWVR3_EL1, MISCREG_DBGWCR0_EL1, MISCREG_DBGWCR1_EL1, MISCREG_DBGWCR2_EL1,   MISCREG_DBGWCR3_EL1, MISCREG_MDCCSR_EL0, MISCREG_MDDTR_EL0, MISCREG_MDDTRTX_EL0,   MISCREG_MDDTRRX_EL0, MISCREG_DBGVCR32_EL2, MISCREG_MDRAR_EL1, MISCREG_OSLAR_EL1,   MISCREG_OSLSR_EL1, MISCREG_OSDLR_EL1, MISCREG_DBGPRCR_EL1, MISCREG_DBGCLAIMSET_EL1,   MISCREG_DBGCLAIMCLR_EL1, MISCREG_DBGAUTHSTATUS_EL1, MISCREG_TEECR32_EL1, MISCREG_TEEHBR32_EL1,   MISCREG_MIDR_EL1, MISCREG_MPIDR_EL1, MISCREG_REVIDR_EL1, MISCREG_ID_PFR0_EL1,   MISCREG_ID_PFR1_EL1, MISCREG_ID_DFR0_EL1, MISCREG_ID_AFR0_EL1, MISCREG_ID_MMFR0_EL1,   MISCREG_ID_MMFR1_EL1, MISCREG_ID_MMFR2_EL1, MISCREG_ID_MMFR3_EL1, MISCREG_ID_ISAR0_EL1,   MISCREG_ID_ISAR1_EL1, MISCREG_ID_ISAR2_EL1, MISCREG_ID_ISAR3_EL1, MISCREG_ID_ISAR4_EL1,   MISCREG_ID_ISAR5_EL1, MISCREG_MVFR0_EL1, MISCREG_MVFR1_EL1, MISCREG_MVFR2_EL1,   MISCREG_ID_AA64PFR0_EL1, MISCREG_ID_AA64PFR1_EL1, MISCREG_ID_AA64DFR0_EL1, MISCREG_ID_AA64DFR1_EL1,   MISCREG_ID_AA64AFR0_EL1, MISCREG_ID_AA64AFR1_EL1, MISCREG_ID_AA64ISAR0_EL1, MISCREG_ID_AA64ISAR1_EL1,   MISCREG_ID_AA64MMFR0_EL1, MISCREG_ID_AA64MMFR1_EL1, MISCREG_CCSIDR_EL1, MISCREG_CLIDR_EL1,   MISCREG_AIDR_EL1, MISCREG_CSSELR_EL1, MISCREG_CTR_EL0, MISCREG_DCZID_EL0,   MISCREG_VPIDR_EL2, MISCREG_VMPIDR_EL2, MISCREG_SCTLR_EL1, MISCREG_ACTLR_EL1,   MISCREG_CPACR_EL1, MISCREG_SCTLR_EL2, MISCREG_ACTLR_EL2, MISCREG_HCR_EL2,   MISCREG_MDCR_EL2, MISCREG_CPTR_EL2, MISCREG_HSTR_EL2, MISCREG_HACR_EL2,   MISCREG_SCTLR_EL3, MISCREG_ACTLR_EL3, MISCREG_SCR_EL3, MISCREG_SDER32_EL3,   MISCREG_CPTR_EL3, MISCREG_MDCR_EL3, MISCREG_TTBR0_EL1, MISCREG_TTBR1_EL1,   MISCREG_TCR_EL1, MISCREG_TTBR0_EL2, MISCREG_TCR_EL2, MISCREG_VTTBR_EL2,   MISCREG_VTCR_EL2, MISCREG_TTBR0_EL3, MISCREG_TCR_EL3, MISCREG_DACR32_EL2,   MISCREG_SPSR_EL1, MISCREG_ELR_EL1, MISCREG_SP_EL0, MISCREG_SPSEL,   MISCREG_CURRENTEL, MISCREG_NZCV, MISCREG_DAIF, MISCREG_FPCR,   MISCREG_FPSR, MISCREG_DSPSR_EL0, MISCREG_DLR_EL0, MISCREG_SPSR_EL2,   MISCREG_ELR_EL2, MISCREG_SP_EL1, MISCREG_SPSR_IRQ_AA64, MISCREG_SPSR_ABT_AA64,   MISCREG_SPSR_UND_AA64, MISCREG_SPSR_FIQ_AA64, MISCREG_SPSR_EL3, MISCREG_ELR_EL3,   MISCREG_SP_EL2, MISCREG_AFSR0_EL1, MISCREG_AFSR1_EL1, MISCREG_ESR_EL1,   MISCREG_IFSR32_EL2, MISCREG_AFSR0_EL2, MISCREG_AFSR1_EL2, MISCREG_ESR_EL2,   MISCREG_FPEXC32_EL2, MISCREG_AFSR0_EL3, MISCREG_AFSR1_EL3, MISCREG_ESR_EL3,   MISCREG_FAR_EL1, MISCREG_FAR_EL2, MISCREG_HPFAR_EL2, MISCREG_FAR_EL3,   MISCREG_IC_IALLUIS, MISCREG_PAR_EL1, MISCREG_IC_IALLU, MISCREG_DC_IVAC_Xt,   MISCREG_DC_ISW_Xt, MISCREG_AT_S1E1R_Xt, MISCREG_AT_S1E1W_Xt, MISCREG_AT_S1E0R_Xt,   MISCREG_AT_S1E0W_Xt, MISCREG_DC_CSW_Xt, MISCREG_DC_CISW_Xt, MISCREG_DC_ZVA_Xt,   MISCREG_IC_IVAU_Xt, MISCREG_DC_CVAC_Xt, MISCREG_DC_CVAU_Xt, MISCREG_DC_CIVAC_Xt,   MISCREG_AT_S1E2R_Xt, MISCREG_AT_S1E2W_Xt, MISCREG_AT_S12E1R_Xt, MISCREG_AT_S12E1W_Xt,   MISCREG_AT_S12E0R_Xt, MISCREG_AT_S12E0W_Xt, MISCREG_AT_S1E3R_Xt, MISCREG_AT_S1E3W_Xt,   MISCREG_TLBI_VMALLE1IS, MISCREG_TLBI_VAE1IS_Xt, MISCREG_TLBI_ASIDE1IS_Xt, MISCREG_TLBI_VAAE1IS_Xt,   MISCREG_TLBI_VALE1IS_Xt, MISCREG_TLBI_VAALE1IS_Xt, MISCREG_TLBI_VMALLE1, MISCREG_TLBI_VAE1_Xt,   MISCREG_TLBI_ASIDE1_Xt, MISCREG_TLBI_VAAE1_Xt, MISCREG_TLBI_VALE1_Xt, MISCREG_TLBI_VAALE1_Xt,   MISCREG_TLBI_IPAS2E1IS_Xt, MISCREG_TLBI_IPAS2LE1IS_Xt, MISCREG_TLBI_ALLE2IS, MISCREG_TLBI_VAE2IS_Xt,   MISCREG_TLBI_ALLE1IS, MISCREG_TLBI_VALE2IS_Xt, MISCREG_TLBI_VMALLS12E1IS, MISCREG_TLBI_IPAS2E1_Xt,   MISCREG_TLBI_IPAS2LE1_Xt, MISCREG_TLBI_ALLE2, MISCREG_TLBI_VAE2_Xt, MISCREG_TLBI_ALLE1,   MISCREG_TLBI_VALE2_Xt, MISCREG_TLBI_VMALLS12E1, MISCREG_TLBI_ALLE3IS, MISCREG_TLBI_VAE3IS_Xt,   MISCREG_TLBI_VALE3IS_Xt, MISCREG_TLBI_ALLE3, MISCREG_TLBI_VAE3_Xt, MISCREG_TLBI_VALE3_Xt,   MISCREG_PMINTENSET_EL1, MISCREG_PMINTENCLR_EL1, MISCREG_PMCR_EL0, MISCREG_PMCNTENSET_EL0,   MISCREG_PMCNTENCLR_EL0, MISCREG_PMOVSCLR_EL0, MISCREG_PMSWINC_EL0, MISCREG_PMSELR_EL0,   MISCREG_PMCEID0_EL0, MISCREG_PMCEID1_EL0, MISCREG_PMCCNTR_EL0, MISCREG_PMXEVTYPER_EL0,   MISCREG_PMCCFILTR_EL0, MISCREG_PMXEVCNTR_EL0, MISCREG_PMUSERENR_EL0, MISCREG_PMOVSSET_EL0,   MISCREG_MAIR_EL1, MISCREG_AMAIR_EL1, MISCREG_MAIR_EL2, MISCREG_AMAIR_EL2,   MISCREG_MAIR_EL3, MISCREG_AMAIR_EL3, MISCREG_L2CTLR_EL1, MISCREG_L2ECTLR_EL1,   MISCREG_VBAR_EL1, MISCREG_RVBAR_EL1, MISCREG_ISR_EL1, MISCREG_VBAR_EL2,   MISCREG_RVBAR_EL2, MISCREG_VBAR_EL3, MISCREG_RVBAR_EL3, MISCREG_RMR_EL3,   MISCREG_CONTEXTIDR_EL1, MISCREG_TPIDR_EL1, MISCREG_TPIDR_EL0, MISCREG_TPIDRRO_EL0,   MISCREG_TPIDR_EL2, MISCREG_TPIDR_EL3, MISCREG_CNTKCTL_EL1, MISCREG_CNTFRQ_EL0,   MISCREG_CNTPCT_EL0, MISCREG_CNTVCT_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_CTL_EL0,   MISCREG_CNTP_CVAL_EL0, MISCREG_CNTV_TVAL_EL0, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_CVAL_EL0,   MISCREG_PMEVCNTR0_EL0, MISCREG_PMEVCNTR1_EL0, MISCREG_PMEVCNTR2_EL0, MISCREG_PMEVCNTR3_EL0,   MISCREG_PMEVCNTR4_EL0, MISCREG_PMEVCNTR5_EL0, MISCREG_PMEVTYPER0_EL0, MISCREG_PMEVTYPER1_EL0,   MISCREG_PMEVTYPER2_EL0, MISCREG_PMEVTYPER3_EL0, MISCREG_PMEVTYPER4_EL0, MISCREG_PMEVTYPER5_EL0,   MISCREG_CNTVOFF_EL2, MISCREG_CNTHCTL_EL2, MISCREG_CNTHP_TVAL_EL2, MISCREG_CNTHP_CTL_EL2,   MISCREG_CNTHP_CVAL_EL2, MISCREG_CNTPS_TVAL_EL1, MISCREG_CNTPS_CTL_EL1, MISCREG_CNTPS_CVAL_EL1,   MISCREG_IL1DATA0_EL1, MISCREG_IL1DATA1_EL1, MISCREG_IL1DATA2_EL1, MISCREG_IL1DATA3_EL1,   MISCREG_DL1DATA0_EL1, MISCREG_DL1DATA1_EL1, MISCREG_DL1DATA2_EL1, MISCREG_DL1DATA3_EL1,   MISCREG_DL1DATA4_EL1, MISCREG_L2ACTLR_EL1, MISCREG_CPUACTLR_EL1, MISCREG_CPUECTLR_EL1,   MISCREG_CPUMERRSR_EL1, MISCREG_L2MERRSR_EL1, MISCREG_CBAR_EL1, MISCREG_CONTEXTIDR_EL2,   MISCREG_NOP, MISCREG_RAZ, MISCREG_CP14_UNIMPL, MISCREG_CP15_UNIMPL,   MISCREG_A64_UNIMPL, MISCREG_UNKNOWN, NUM_MISCREGS }
enum	MiscRegInfo {   MISCREG_IMPLEMENTED, MISCREG_UNVERIFIABLE, MISCREG_WARN_NOT_FAIL, MISCREG_MUTEX,   MISCREG_BANKED, MISCREG_BANKED_CHILD, MISCREG_USR_NS_RD, MISCREG_USR_NS_WR,   MISCREG_USR_S_RD, MISCREG_USR_S_WR, MISCREG_PRI_NS_RD, MISCREG_PRI_NS_WR,   MISCREG_PRI_S_RD, MISCREG_PRI_S_WR, MISCREG_HYP_RD, MISCREG_HYP_WR,   MISCREG_MON_NS0_RD, MISCREG_MON_NS0_WR, MISCREG_MON_NS1_RD, MISCREG_MON_NS1_WR,   NUM_MISCREG_INFOS }
enum	LookupLevel {   L0 = 0, L1, L2, L3,   MAX_LOOKUP_LEVELS }
enum	ArmShiftType { LSL = 0, LSR, ASR, ROR }
enum	ArmExtendType {   UXTB = 0, UXTH = 1, UXTW = 2, UXTX = 3,   SXTB = 4, SXTH = 5, SXTW = 6, SXTX = 7 }
enum	ConvertType {   SINGLE_TO_DOUBLE, SINGLE_TO_WORD, SINGLE_TO_LONG, DOUBLE_TO_SINGLE,   DOUBLE_TO_WORD, DOUBLE_TO_LONG, LONG_TO_SINGLE, LONG_TO_DOUBLE,   LONG_TO_WORD, LONG_TO_PS, WORD_TO_SINGLE, WORD_TO_DOUBLE,   WORD_TO_LONG, WORD_TO_PS, PL_TO_SINGLE, PU_TO_SINGLE }
enum	RoundMode { RND_ZERO, RND_DOWN, RND_UP, RND_NEAREST }
enum	ExceptionLevel { EL0 = 0, EL1, EL2, EL3 }
enum	OperatingMode {   MODE_EL0T = 0x0, MODE_EL1T = 0x4, MODE_EL1H = 0x5, MODE_EL2T = 0x8,   MODE_EL2H = 0x9, MODE_EL3T = 0xC, MODE_EL3H = 0xD, MODE_USER = 16,   MODE_FIQ = 17, MODE_IRQ = 18, MODE_SVC = 19, MODE_MON = 22,   MODE_ABORT = 23, MODE_HYP = 26, MODE_UNDEFINED = 27, MODE_SYSTEM = 31,   MODE_MAXMODE = MODE_SYSTEM }
enum	ExceptionClass {   EC_INVALID = -1, EC_UNKNOWN = 0x0, EC_TRAPPED_WFI_WFE = 0x1, EC_TRAPPED_CP15_MCR_MRC = 0x3,   EC_TRAPPED_CP15_MCRR_MRRC = 0x4, EC_TRAPPED_CP14_MCR_MRC = 0x5, EC_TRAPPED_CP14_LDC_STC = 0x6, EC_TRAPPED_HCPTR = 0x7,   EC_TRAPPED_SIMD_FP = 0x7, EC_TRAPPED_CP10_MRC_VMRS = 0x8, EC_TRAPPED_BXJ = 0xA, EC_TRAPPED_CP14_MCRR_MRRC = 0xC,   EC_ILLEGAL_INST = 0xE, EC_SVC_TO_HYP = 0x11, EC_SVC = 0x11, EC_HVC = 0x12,   EC_SMC_TO_HYP = 0x13, EC_SMC = 0x13, EC_SVC_64 = 0x15, EC_HVC_64 = 0x16,   EC_SMC_64 = 0x17, EC_TRAPPED_MSR_MRS_64 = 0x18, EC_PREFETCH_ABORT_TO_HYP = 0x20, EC_PREFETCH_ABORT_LOWER_EL = 0x20,   EC_PREFETCH_ABORT_FROM_HYP = 0x21, EC_PREFETCH_ABORT_CURR_EL = 0x21, EC_PC_ALIGNMENT = 0x22, EC_DATA_ABORT_TO_HYP = 0x24,   EC_DATA_ABORT_LOWER_EL = 0x24, EC_DATA_ABORT_FROM_HYP = 0x25, EC_DATA_ABORT_CURR_EL = 0x25, EC_STACK_PTR_ALIGNMENT = 0x26,   EC_FP_EXCEPTION = 0x28, EC_FP_EXCEPTION_64 = 0x2C, EC_SERROR = 0x2F }
enum	DecoderFault : std::uint8_t { OK = 0x0, UNALIGNED = 0x1, PANIC = 0x3 }
	Instruction decoder fault codes in ExtMachInst. More...

Functions
static uint16_t	lsl16 (uint16_t x, uint32_t shift)
static uint16_t	lsr16 (uint16_t x, uint32_t shift)
static uint32_t	lsl32 (uint32_t x, uint32_t shift)
static uint32_t	lsr32 (uint32_t x, uint32_t shift)
static uint64_t	lsl64 (uint64_t x, uint32_t shift)
static uint64_t	lsr64 (uint64_t x, uint32_t shift)
static void	lsl128 (uint64_t *r0, uint64_t *r1, uint64_t x0, uint64_t x1, uint32_t shift)
static void	lsr128 (uint64_t *r0, uint64_t *r1, uint64_t x0, uint64_t x1, uint32_t shift)
static void	mul62x62 (uint64_t *x0, uint64_t *x1, uint64_t a, uint64_t b)
static void	mul64x32 (uint64_t *x0, uint64_t *x1, uint64_t a, uint32_t b)
static void	add128 (uint64_t *x0, uint64_t *x1, uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
static void	sub128 (uint64_t *x0, uint64_t *x1, uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
static int	cmp128 (uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
static uint16_t	fp16_normalise (uint16_t mnt, int *exp)
static uint32_t	fp32_normalise (uint32_t mnt, int *exp)
static uint64_t	fp64_normalise (uint64_t mnt, int *exp)
static void	fp128_normalise (uint64_t *mnt0, uint64_t *mnt1, int *exp)
static uint16_t	fp16_pack (uint16_t sgn, uint16_t exp, uint16_t mnt)
static uint32_t	fp32_pack (uint32_t sgn, uint32_t exp, uint32_t mnt)
static uint64_t	fp64_pack (uint64_t sgn, uint64_t exp, uint64_t mnt)
static uint16_t	fp16_zero (int sgn)
static uint32_t	fp32_zero (int sgn)
static uint64_t	fp64_zero (int sgn)
static uint16_t	fp16_max_normal (int sgn)
static uint32_t	fp32_max_normal (int sgn)
static uint64_t	fp64_max_normal (int sgn)
static uint16_t	fp16_infinity (int sgn)
static uint32_t	fp32_infinity (int sgn)
static uint64_t	fp64_infinity (int sgn)
static uint16_t	fp16_defaultNaN ()
static uint32_t	fp32_defaultNaN ()
static uint64_t	fp64_defaultNaN ()
static void	fp16_unpack (int *sgn, int *exp, uint16_t *mnt, uint16_t x, int mode, int *flags)
static void	fp32_unpack (int *sgn, int *exp, uint32_t *mnt, uint32_t x, int mode, int *flags)
static void	fp64_unpack (int *sgn, int *exp, uint64_t *mnt, uint64_t x, int mode, int *flags)
static uint32_t	fp32_process_NaN (uint32_t a, int mode, int *flags)
static uint64_t	fp64_process_NaN (uint64_t a, int mode, int *flags)
static uint32_t	fp32_process_NaNs (uint32_t a, uint32_t b, int mode, int *flags)
static uint64_t	fp64_process_NaNs (uint64_t a, uint64_t b, int mode, int *flags)
static uint32_t	fp32_process_NaNs3 (uint32_t a, uint32_t b, uint32_t c, int mode, int *flags)
static uint64_t	fp64_process_NaNs3 (uint64_t a, uint64_t b, uint64_t c, int mode, int *flags)
static uint16_t	fp16_round_ (int sgn, int exp, uint16_t mnt, int rm, int mode, int *flags)
static uint32_t	fp32_round_ (int sgn, int exp, uint32_t mnt, int rm, int mode, int *flags)
static uint32_t	fp32_round (int sgn, int exp, uint32_t mnt, int mode, int *flags)
static uint64_t	fp64_round_ (int sgn, int exp, uint64_t mnt, int rm, int mode, int *flags)
static uint64_t	fp64_round (int sgn, int exp, uint64_t mnt, int mode, int *flags)
static int	fp32_compare_eq (uint32_t a, uint32_t b, int mode, int *flags)
static int	fp32_compare_ge (uint32_t a, uint32_t b, int mode, int *flags)
static int	fp32_compare_gt (uint32_t a, uint32_t b, int mode, int *flags)
static int	fp64_compare_eq (uint64_t a, uint64_t b, int mode, int *flags)
static int	fp64_compare_ge (uint64_t a, uint64_t b, int mode, int *flags)
static int	fp64_compare_gt (uint64_t a, uint64_t b, int mode, int *flags)
static uint32_t	fp32_add (uint32_t a, uint32_t b, int neg, int mode, int *flags)
static uint64_t	fp64_add (uint64_t a, uint64_t b, int neg, int mode, int *flags)
static uint32_t	fp32_mul (uint32_t a, uint32_t b, int mode, int *flags)
static uint64_t	fp64_mul (uint64_t a, uint64_t b, int mode, int *flags)
static uint32_t	fp32_muladd (uint32_t a, uint32_t b, uint32_t c, int scale, int mode, int *flags)
static uint64_t	fp64_muladd (uint64_t a, uint64_t b, uint64_t c, int scale, int mode, int *flags)
static uint32_t	fp32_div (uint32_t a, uint32_t b, int mode, int *flags)
static uint64_t	fp64_div (uint64_t a, uint64_t b, int mode, int *flags)
static void	set_fpscr0 (FPSCR &fpscr, int flags)
static uint32_t	fp32_sqrt (uint32_t a, int mode, int *flags)
static uint64_t	fp64_sqrt (uint64_t a, int mode, int *flags)
static int	modeConv (FPSCR fpscr)
static void	set_fpscr (FPSCR &fpscr, int flags)
template<>
bool	fplibCompareEQ (uint32_t a, uint32_t b, FPSCR &fpscr)
template<>
bool	fplibCompareGE (uint32_t a, uint32_t b, FPSCR &fpscr)
template<>
bool	fplibCompareGT (uint32_t a, uint32_t b, FPSCR &fpscr)
template<>
bool	fplibCompareEQ (uint64_t a, uint64_t b, FPSCR &fpscr)
template<>
bool	fplibCompareGE (uint64_t a, uint64_t b, FPSCR &fpscr)
template<>
bool	fplibCompareGT (uint64_t a, uint64_t b, FPSCR &fpscr)
template<>
uint32_t	fplibAbs (uint32_t op)
template<>
uint64_t	fplibAbs (uint64_t op)
template<>
uint32_t	fplibAdd (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibAdd (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
int	fplibCompare (uint32_t op1, uint32_t op2, bool signal_nans, FPSCR &fpscr)
template<>
int	fplibCompare (uint64_t op1, uint64_t op2, bool signal_nans, FPSCR &fpscr)
static uint16_t	fp16_FPConvertNaN_32 (uint32_t op)
static uint16_t	fp16_FPConvertNaN_64 (uint64_t op)
static uint32_t	fp32_FPConvertNaN_16 (uint16_t op)
static uint32_t	fp32_FPConvertNaN_64 (uint64_t op)
static uint64_t	fp64_FPConvertNaN_16 (uint16_t op)
static uint64_t	fp64_FPConvertNaN_32 (uint32_t op)
static uint32_t	fp32_FPOnePointFive (int sgn)
static uint64_t	fp64_FPOnePointFive (int sgn)
static uint32_t	fp32_FPThree (int sgn)
static uint64_t	fp64_FPThree (int sgn)
static uint32_t	fp32_FPTwo (int sgn)
static uint64_t	fp64_FPTwo (int sgn)
template<>
uint16_t	fplibConvert (uint32_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint16_t	fplibConvert (uint64_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibConvert (uint16_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibConvert (uint64_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibConvert (uint16_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibConvert (uint32_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibMulAdd (uint32_t addend, uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMulAdd (uint64_t addend, uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibDiv (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibDiv (uint64_t op1, uint64_t op2, FPSCR &fpscr)
static uint32_t	fp32_repack (int sgn, int exp, uint32_t mnt)
static uint64_t	fp64_repack (int sgn, int exp, uint64_t mnt)
static void	fp32_minmaxnum (uint32_t *op1, uint32_t *op2, int sgn)
static void	fp64_minmaxnum (uint64_t *op1, uint64_t *op2, int sgn)
template<>
uint32_t	fplibMax (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMax (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMaxNum (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMaxNum (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMin (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMin (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMinNum (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMinNum (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMul (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMul (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMulX (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMulX (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibNeg (uint32_t op)
template<>
uint64_t	fplibNeg (uint64_t op)
template<>
uint32_t	fplibRSqrtEstimate (uint32_t op, FPSCR &fpscr)
template<>
uint64_t	fplibRSqrtEstimate (uint64_t op, FPSCR &fpscr)
template<>
uint32_t	fplibRSqrtStepFused (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibRSqrtStepFused (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibRecipStepFused (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibRecipEstimate (uint32_t op, FPSCR &fpscr)
template<>
uint64_t	fplibRecipEstimate (uint64_t op, FPSCR &fpscr)
template<>
uint64_t	fplibRecipStepFused (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibRecpX (uint32_t op, FPSCR &fpscr)
template<>
uint64_t	fplibRecpX (uint64_t op, FPSCR &fpscr)
template<>
uint32_t	fplibRoundInt (uint32_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
template<>
uint64_t	fplibRoundInt (uint64_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
template<>
uint32_t	fplibSqrt (uint32_t op, FPSCR &fpscr)
template<>
uint64_t	fplibSqrt (uint64_t op, FPSCR &fpscr)
template<>
uint32_t	fplibSub (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibSub (uint64_t op1, uint64_t op2, FPSCR &fpscr)
static uint64_t	FPToFixed_64 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
static uint32_t	FPToFixed_32 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
template<>
uint32_t	fplibFPToFixed (uint32_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibFPToFixed (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibFPToFixed (uint32_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibFPToFixed (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
static uint32_t	fp32_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
static uint64_t	fp64_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
template<>
uint32_t	fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
	Floating-point convert from fixed-point. More...
template<>
uint64_t	fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
	Floating-point convert from fixed-point. More...
static FPRounding	FPCRRounding (FPSCR &fpscr)
template<class T >
T	fplibAbs (T op)
	Floating-point absolute value. More...
template<class T >
T	fplibAdd (T op1, T op2, FPSCR &fpscr)
	Floating-point add. More...
template<class T >
int	fplibCompare (T op1, T op2, bool signal_nans, FPSCR &fpscr)
	Floating-point compare (quiet and signaling). More...
template<class T >
bool	fplibCompareEQ (T op1, T op2, FPSCR &fpscr)
	Floating-point compare equal. More...
template<class T >
bool	fplibCompareGE (T op1, T op2, FPSCR &fpscr)
	Floating-point compare greater than or equal. More...
template<class T >
bool	fplibCompareGT (T op1, T op2, FPSCR &fpscr)
	Floating-point compare greater than. More...
template<class T1 , class T2 >
T2	fplibConvert (T1 op, FPRounding rounding, FPSCR &fpscr)
	Floating-point convert precision. More...
template<class T >
T	fplibDiv (T op1, T op2, FPSCR &fpscr)
	Floating-point division. More...
template<class T >
T	fplibMax (T op1, T op2, FPSCR &fpscr)
	Floating-point maximum. More...
template<class T >
T	fplibMaxNum (T op1, T op2, FPSCR &fpscr)
	Floating-point maximum number. More...
template<class T >
T	fplibMin (T op1, T op2, FPSCR &fpscr)
	Floating-point minimum. More...
template<class T >
T	fplibMinNum (T op1, T op2, FPSCR &fpscr)
	Floating-point minimum number. More...
template<class T >
T	fplibMul (T op1, T op2, FPSCR &fpscr)
	Floating-point multiply. More...
template<class T >
T	fplibMulAdd (T addend, T op1, T op2, FPSCR &fpscr)
	Floating-point multiply-add. More...
template<class T >
T	fplibMulX (T op1, T op2, FPSCR &fpscr)
	Floating-point multiply extended. More...
template<class T >
T	fplibNeg (T op)
	Floating-point negate. More...
template<class T >
T	fplibRSqrtEstimate (T op, FPSCR &fpscr)
	Floating-point reciprocal square root estimate. More...
template<class T >
T	fplibRSqrtStepFused (T op1, T op2, FPSCR &fpscr)
	Floating-point reciprocal square root step. More...
template<class T >
T	fplibRecipEstimate (T op, FPSCR &fpscr)
	Floating-point reciprocal estimate. More...
template<class T >
T	fplibRecipStepFused (T op1, T op2, FPSCR &fpscr)
	Floating-point reciprocal step. More...
template<class T >
T	fplibRecpX (T op, FPSCR &fpscr)
	Floating-point reciprocal exponent. More...
template<class T >
T	fplibRoundInt (T op, FPRounding rounding, bool exact, FPSCR &fpscr)
	Floating-point convert to integer. More...
template<class T >
T	fplibSqrt (T op, FPSCR &fpscr)
	Floating-point square root. More...
template<class T >
T	fplibSub (T op1, T op2, FPSCR &fpscr)
	Floating-point subtract. More...
template<class T1 , class T2 >
T2	fplibFPToFixed (T1 op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
	Floating-point convert to fixed-point. More...
template<class T >
T	fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
	Floating-point convert from fixed-point. More...
static unsigned int	number_of_ones (int32_t val)
void	writeVecElem (VReg *dest, XReg src, int index, int eSize)
	Write a single NEON vector element leaving the others untouched. More...
XReg	readVecElem (VReg src, int index, int eSize)
	Read a single NEON vector element. More...
static uint32_t	rotate_imm (uint32_t immValue, uint32_t rotateValue)
static uint32_t	modified_imm (uint8_t ctrlImm, uint8_t dataImm)
static uint64_t	simd_modified_imm (bool op, uint8_t cmode, uint8_t data, bool &immValid, bool isAarch64=false)
static uint64_t	vfp_modified_imm (uint8_t data, bool wide)
static uint8_t	getRestoredITBits (ThreadContext *tc, CPSR spsr)
static bool	illegalExceptionReturn (ThreadContext *tc, CPSR cpsr, CPSR spsr)
VfpSavedState	prepFpState (uint32_t rMode)
void	finishVfp (FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask)
template<class fpType >
fpType	fixDest (bool flush, bool defaultNan, fpType val, fpType op1)
template float	fixDest< float > (bool flush, bool defaultNan, float val, float op1)
template double	fixDest< double > (bool flush, bool defaultNan, double val, double op1)
template<class fpType >
fpType	fixDest (bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
template float	fixDest< float > (bool flush, bool defaultNan, float val, float op1, float op2)
template double	fixDest< double > (bool flush, bool defaultNan, double val, double op1, double op2)
template<class fpType >
fpType	fixDivDest (bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
template float	fixDivDest< float > (bool flush, bool defaultNan, float val, float op1, float op2)
template double	fixDivDest< double > (bool flush, bool defaultNan, double val, double op1, double op2)
float	fixFpDFpSDest (FPSCR fpscr, double val)
double	fixFpSFpDDest (FPSCR fpscr, float val)
static uint16_t	vcvtFpFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, uint64_t opBits, bool isDouble)
uint16_t	vcvtFpSFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, float op)
uint16_t	vcvtFpDFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, double op)
static uint64_t	vcvtFpHFp (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op, bool isDouble)
double	vcvtFpHFpD (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
float	vcvtFpHFpS (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
float	vfpUFixedToFpS (bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
float	vfpSFixedToFpS (bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
double	vfpUFixedToFpD (bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
double	vfpSFixedToFpD (bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
static double	recipSqrtEstimate (double a)
float	fprSqrtEstimate (FPSCR &fpscr, float op)
uint32_t	unsignedRSqrtEstimate (uint32_t op)
static double	recipEstimate (double a)
float	fpRecipEstimate (FPSCR &fpscr, float op)
uint32_t	unsignedRecipEstimate (uint32_t op)
template<class T >
static void	setVfpMicroFlags (VfpMicroMode mode, T &flags)
static float	bitsToFp (uint64_t, float)
static double	bitsToFp (uint64_t, double)
static uint32_t	fpToBits (float)
static uint64_t	fpToBits (double)
template<class fpType >
static bool	flushToZero (fpType &op)
template<class fpType >
static bool	flushToZero (fpType &op1, fpType &op2)
template<class fpType >
static void	vfpFlushToZero (FPSCR &fpscr, fpType &op)
template<class fpType >
static void	vfpFlushToZero (FPSCR &fpscr, fpType &op1, fpType &op2)
template<class fpType >
static bool	isSnan (fpType val)
template<class fpType >
fpType	fixDest (FPSCR fpscr, fpType val, fpType op1)
template<class fpType >
fpType	fixDest (FPSCR fpscr, fpType val, fpType op1, fpType op2)
template<class fpType >
fpType	fixDivDest (FPSCR fpscr, fpType val, fpType op1, fpType op2)
static double	makeDouble (uint32_t low, uint32_t high)
static uint32_t	lowFromDouble (double val)
static uint32_t	highFromDouble (double val)
static void	setFPExceptions (int exceptions)
template<typename T >
uint64_t	vfpFpToFixed (T val, bool isSigned, uint8_t width, uint8_t imm, bool useRmode=true, VfpRoundingMode roundMode=VfpRoundZero, bool aarch64=false)
template<typename T >
static T	fpAdd (T a, T b)
template<typename T >
static T	fpSub (T a, T b)
static float	fpAddS (float a, float b)
static double	fpAddD (double a, double b)
static float	fpSubS (float a, float b)
static double	fpSubD (double a, double b)
static float	fpDivS (float a, float b)
static double	fpDivD (double a, double b)
template<typename T >
static T	fpDiv (T a, T b)
template<typename T >
static T	fpMulX (T a, T b)
template<typename T >
static T	fpMul (T a, T b)
static float	fpMulS (float a, float b)
static double	fpMulD (double a, double b)
template<typename T >
static T	fpMulAdd (T op1, T op2, T addend)
template<typename T >
static T	fpRIntX (T a, FPSCR &fpscr)
template<typename T >
static T	fpMaxNum (T a, T b)
template<typename T >
static T	fpMax (T a, T b)
template<typename T >
static T	fpMinNum (T a, T b)
template<typename T >
static T	fpMin (T a, T b)
template<typename T >
static T	fpRSqrts (T a, T b)
template<typename T >
static T	fpRecps (T a, T b)
static float	fpRSqrtsS (float a, float b)
static float	fpRecpsS (float a, float b)
template<typename T >
static T	roundNEven (T a)
static IntRegIndex	INTREG_USR (unsigned index)
static IntRegIndex	INTREG_HYP (unsigned index)
static IntRegIndex	INTREG_SVC (unsigned index)
static IntRegIndex	INTREG_MON (unsigned index)
static IntRegIndex	INTREG_ABT (unsigned index)
static IntRegIndex	INTREG_UND (unsigned index)
static IntRegIndex	INTREG_IRQ (unsigned index)
static IntRegIndex	INTREG_FIQ (unsigned index)
static int	intRegInMode (OperatingMode mode, int reg)
static int	flattenIntRegModeIndex (int reg)
static IntRegIndex	makeSP (IntRegIndex reg)
static IntRegIndex	makeZero (IntRegIndex reg)
static bool	isSP (IntRegIndex reg)
	if (!pmu) pmu
pmu	setISA (this)
	if (FullSystem &&system)
	for (auto sw:MiscRegSwitch)
	Fill in the miscReg translation table. More...
	preUnflattenMiscReg ()
	clear ()
Addr	VAddrImpl (Addr a)
Addr	VAddrVPN (Addr a)
Addr	VAddrOffset (Addr a)
template<class XC >
void	handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template<class XC >
void	handleLockedRead (XC *xc, Request *req)
template<class XC >
void	handleLockedSnoopHit (XC *xc)
template<class XC >
bool	handleLockedWrite (XC *xc, Request *req, Addr cacheBlockMask)
MiscRegIndex	decodeCP14Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
MiscRegIndex	decodeCP15Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
MiscRegIndex	decodeCP15Reg64 (unsigned crm, unsigned opc1)
std::tuple< bool, bool >	canReadCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr)
std::tuple< bool, bool >	canWriteCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr)
	Check for permission to read coprocessor registers. More...
int	flattenMiscRegNsBanked (MiscRegIndex reg, ThreadContext *tc)
int	flattenMiscRegNsBanked (MiscRegIndex reg, ThreadContext *tc, bool ns)
int	unflattenMiscReg (int reg)
bool	canReadAArch64SysReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
bool	canWriteAArch64SysReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
MiscRegIndex	decodeAArch64SysReg (unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
bool	aarch64SysRegReadOnly (MiscRegIndex miscReg)
	BitUnion32 (CPSR) Bitfield< 31
	EndBitUnion (CPSR) static const uint32_t CondCodesMask=0xF00F0000
	BitUnion32 (HDCR) Bitfield< 11 > tdra
	EndBitUnion (HDCR) BitUnion32(HCPTR) Bitfield< 31 > tcpac
	EndBitUnion (HCPTR) BitUnion32(HSTR) Bitfield< 17 > tjdbx
	EndBitUnion (HSTR) BitUnion64(HCR) Bitfield< 33 > id
	EndBitUnion (HCR) BitUnion32(NSACR) Bitfield< 20 > nstrcdis
	EndBitUnion (NSACR) BitUnion32(SCR) Bitfield< 13 > twe
	EndBitUnion (SCR) BitUnion32(SCTLR) Bitfield< 30 > te
	EndBitUnion (SCTLR) BitUnion32(CPACR) Bitfield<1
	EndBitUnion (CPACR) BitUnion32(FSR) Bitfield<3
	EndBitUnion (FSR) BitUnion32(FPSCR) Bitfield< 0 > ioc
	EndBitUnion (FPSCR) static const uint32_t FpCondCodesMask=0xF0000000
	BitUnion32 (FPEXC) Bitfield< 31 > ex
	EndBitUnion (FPEXC) BitUnion32(MVFR0) Bitfield<3
	EndBitUnion (MVFR0) BitUnion32(MVFR1) Bitfield<3
	EndBitUnion (MVFR1) BitUnion64(TTBCR) Bitfield<2
	EndBitUnion (TTBCR) BitUnion64(TCR) Bitfield<5
	EndBitUnion (TCR) BitUnion32(HTCR) Bitfield<2
	EndBitUnion (HTCR) BitUnion32(VTCR_t) Bitfield<3
	EndBitUnion (VTCR_t) BitUnion32(PRRR) Bitfield<1
	EndBitUnion (PRRR) BitUnion32(NMRR) Bitfield<1
	EndBitUnion (NMRR) BitUnion32(CONTEXTIDR) Bitfield<7
	EndBitUnion (CONTEXTIDR) BitUnion32(L2CTLR) Bitfield<2
	EndBitUnion (L2CTLR) BitUnion32(CTR) Bitfield<3
	EndBitUnion (CTR) BitUnion32(PMSELR) Bitfield<4
	EndBitUnion (PMSELR) BitUnion64(PAR) Bitfield< 63
	EndBitUnion (PAR) BitUnion32(ESR) Bitfield< 31
	EndBitUnion (ESR) BitUnion32(CPTR) Bitfield< 31 > tcpac
	BitUnion8 (ITSTATE) Bitfield<7
	EndBitUnion (ITSTATE) BitUnion64(ExtMachInst) Bitfield< 63
	SubBitUnion (puswl, 24, 20) Bitfield< 24 > prepost
	EndSubBitUnion (puswl) Bitfield< 24
	EndBitUnion (ExtMachInst) class PCState
	BitUnion8 (OperatingMode64) Bitfield< 0 > spX
	EndBitUnion (OperatingMode64) static bool inline opModeIs64(OperatingMode mode)
static bool	opModeIsH (OperatingMode mode)
static bool	opModeIsT (OperatingMode mode)
static ExceptionLevel	opModeToEL (OperatingMode mode)
static bool	badMode (OperatingMode mode)
static bool	badMode32 (OperatingMode mode)
void	initCPU (ThreadContext *tc, int cpuId)
uint64_t	getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)
void	skipFunction (ThreadContext *tc)
void	copyRegs (ThreadContext *src, ThreadContext *dest)
bool	inSecureState (ThreadContext *tc)
bool	inAArch64 (ThreadContext *tc)
bool	longDescFormatInUse (ThreadContext *tc)
uint32_t	getMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
bool	ELIs64 (ThreadContext *tc, ExceptionLevel el)
bool	isBigEndian64 (ThreadContext *tc)
Addr	purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, TTBCR tcr)
	Removes the tag from tagged addresses if that mode is enabled. More...
Addr	purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el)
Addr	truncPage (Addr addr)
Addr	roundPage (Addr addr)
bool	mcrMrc15TrapToHyp (const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
bool	mcrMrc14TrapToHyp (const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
bool	mcrrMrrc15TrapToHyp (const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr, HCR hcr, uint32_t iss)
bool	msrMrs64TrapToSup (const MiscRegIndex miscReg, ExceptionLevel el, CPACR cpacr)
bool	msrMrs64TrapToHyp (const MiscRegIndex miscReg, ExceptionLevel el, bool isRead, CPTR cptr, HCR hcr, bool *isVfpNeon)
bool	msrMrs64TrapToMon (const MiscRegIndex miscReg, CPTR cptr, ExceptionLevel el, bool *isVfpNeon)
bool	decodeMrsMsrBankedReg (uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
bool	SPAlignmentCheckEnabled (ThreadContext *tc)
int	decodePhysAddrRange64 (uint8_t pa_enc)
	Returns the n. More...
uint8_t	encodePhysAddrRange64 (int pa_size)
	Returns the encoding corresponding to the specified n. More...
PCState	buildRetPC (const PCState &curPC, const PCState &callPC)
bool	testPredicate (uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
template<class TC >
void	zeroRegisters (TC *tc)
	Function to insure ISA semantics about 0 registers. More...
void	startupCPU (ThreadContext *tc, int cpuId)
static void	copyMiscRegs (ThreadContext *src, ThreadContext *dest)
static bool	inUserMode (CPSR cpsr)
static bool	inUserMode (ThreadContext *tc)
static bool	inPrivilegedMode (CPSR cpsr)
static bool	inPrivilegedMode (ThreadContext *tc)
static OperatingMode	currOpMode (ThreadContext *tc)
static ExceptionLevel	currEL (ThreadContext *tc)
static uint8_t	itState (CPSR psr)
static bool	inSecureState (SCR scr, CPSR cpsr)
static uint32_t	mcrMrcIssBuild (bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2)
static void	mcrMrcIssExtract (uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
static uint32_t	mcrrMrrcIssBuild (bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2, uint32_t opc1)
static uint32_t	msrMrs64IssBuild (bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, IntRegIndex rt)
void	advancePC (PCState &pc, const StaticInstPtr &inst)
uint64_t	getExecutingAsid (ThreadContext *tc)
static int	decodeMrsMsrBankedIntRegIndex (uint8_t sysM, bool r)
Addr	PteAddr (Addr a)
Addr	vtophys (Addr vaddr)
Addr	vtophys (ThreadContext *tc, Addr vaddr)
bool	virtvalid (ThreadContext *tc, Addr vaddr)

Variables
const char *const	ccRegName [NUM_CCREGS]
static const uint8_t	recip_sqrt_estimate [256]
const IntRegMap	IntReg64Map
const IntRegMap	IntRegUsrMap
const IntRegMap	IntRegHypMap
const IntRegMap	IntRegSvcMap
const IntRegMap	IntRegMonMap
const IntRegMap	IntRegAbtMap
const IntRegMap	IntRegUndMap
const IntRegMap	IntRegIrqMap
const IntRegMap	IntRegFiqMap
static const unsigned	intRegsPerMode = NUM_INTREGS
	system = dynamic_cast<ArmSystem *>(p->system)
	else
	haveSecurity = haveLPAE = haveVirtualization = false
	haveLargeAsid64 = false
	physAddrRange64 = 32
StaticInstPtr	decodeInst (ExtMachInst)
const Addr	PageShift = 12
const Addr	PageBytes = ULL(1) << PageShift
const Addr	Page_Mask = ~(PageBytes - 1)
const Addr	PageOffset = PageBytes - 1
const Addr	PteShift = 3
const Addr	NPtePageShift = PageShift - PteShift
const Addr	NPtePage = ULL(1) << NPtePageShift
const Addr	PteMask = NPtePage - 1
const Addr	USegBase = ULL(0x0)
const Addr	USegEnd = ULL(0x7FFFFFFF)
const unsigned	VABits = 32
const unsigned	PABits = 32
const Addr	VAddrImplMask = (ULL(1) << VABits) - 1
const Addr	VAddrUnImplMask = ~VAddrImplMask
const Addr	PAddrImplMask = (ULL(1) << PABits) - 1
const unsigned	MaxPhysAddrRange = 48
const ExtMachInst	NoopMachInst = 0x01E320F000ULL
const int	MachineBytes = 4
const uint32_t	HighVecs = 0xFFFF0000
const bool	HasUnalignedMemAcc = true
const bool	CurThreadInfoImplemented = false
const int	CurThreadInfoReg = -1
bitset< NUM_MISCREG_INFOS >	miscRegInfo [NUM_MISCREGS]
int	unflattenResultMiscReg [NUM_MISCREGS]
	If the reg is a child reg of a banked set, then the parent is the last banked one in the list. More...
const char *const	miscRegName []
	nz
Bitfield< 29 >	c
Bitfield< 28 >	v
Bitfield< 27 >	q
Bitfield< 26, 25 >	it1
Bitfield< 24 >	j
Bitfield< 23, 22 >	res0_23_22
Bitfield< 21 >	ss
Bitfield< 20 >	il
Bitfield< 19, 16 >	ge
Bitfield< 15, 10 >	it2
Bitfield< 9 >	d
Bitfield< 9 >	e
Bitfield< 8 >	a
Bitfield< 7 >	i
Bitfield< 6 >	f
Bitfield< 8, 6 >	aif
Bitfield< 9, 6 >	daif
Bitfield< 5 >	t
Bitfield< 4 >	width
Bitfield< 3, 2 >	el
Bitfield< 4, 0 >	mode
Bitfield< 0 >	sp
static const uint32_t	CpsrMaskQ = 0x08000000
Bitfield< 10 >	tdosa
Bitfield< 9 >	tda
Bitfield< 8 >	tde
Bitfield< 7 >	hpme
Bitfield< 6 >	tpm
Bitfield< 5 >	tpmcr
Bitfield< 4, 0 >	hpmn
Bitfield< 20 >	tta
Bitfield< 15 >	tase
Bitfield< 13 >	tcp13
Bitfield< 12 >	tcp12
Bitfield< 11 >	tcp11
Bitfield< 10 >	tcp10
Bitfield< 10 >	tfp
Bitfield< 9 >	tcp9
Bitfield< 8 >	tcp8
Bitfield< 7 >	tcp7
Bitfield< 6 >	tcp6
Bitfield< 5 >	tcp5
Bitfield< 4 >	tcp4
Bitfield< 3 >	tcp3
Bitfield< 2 >	tcp2
Bitfield< 1 >	tcp1
Bitfield< 0 >	tcp0
Bitfield< 16 >	ttee
Bitfield< 15 >	t15
Bitfield< 13 >	t13
Bitfield< 12 >	t12
Bitfield< 11 >	t11
Bitfield< 10 >	t10
Bitfield< 9 >	t9
Bitfield< 8 >	t8
Bitfield< 7 >	t7
Bitfield< 6 >	t6
Bitfield< 5 >	t5
Bitfield< 4 >	t4
Bitfield< 3 >	t3
Bitfield< 2 >	t2
Bitfield< 1 >	t1
Bitfield< 0 >	t0
Bitfield< 32 >	cd
Bitfield< 31 >	rw
Bitfield< 30 >	trvm
Bitfield< 29 >	hcd
Bitfield< 28 >	tdz
Bitfield< 27 >	tge
Bitfield< 26 >	tvm
Bitfield< 25 >	ttlb
Bitfield< 24 >	tpu
Bitfield< 23 >	tpc
Bitfield< 22 >	tsw
Bitfield< 21 >	tac
Bitfield< 21 >	tacr
Bitfield< 20 >	tidcp
Bitfield< 19 >	tsc
Bitfield< 18 >	tid3
Bitfield< 17 >	tid2
Bitfield< 16 >	tid1
Bitfield< 15 >	tid0
Bitfield< 14 >	twe
Bitfield< 13 >	twi
Bitfield< 12 >	dc
Bitfield< 11, 10 >	bsu
Bitfield< 9 >	fb
Bitfield< 8 >	va
Bitfield< 8 >	vse
Bitfield< 7 >	vi
Bitfield< 6 >	vf
Bitfield< 5 >	amo
Bitfield< 4 >	imo
Bitfield< 3 >	fmo
Bitfield< 2 >	ptw
Bitfield< 1 >	swio
Bitfield< 0 >	vm
Bitfield< 19 >	rfr
Bitfield< 15 >	nsasedis
Bitfield< 14 >	nsd32dis
Bitfield< 13 >	cp13
Bitfield< 12 >	cp12
Bitfield< 11 >	cp11
Bitfield< 10 >	cp10
Bitfield< 9 >	cp9
Bitfield< 8 >	cp8
Bitfield< 7 >	cp7
Bitfield< 6 >	cp6
Bitfield< 5 >	cp5
Bitfield< 4 >	cp4
Bitfield< 3 >	cp3
Bitfield< 2 >	cp2
Bitfield< 1 >	cp1
Bitfield< 0 >	cp0
Bitfield< 11 >	st
Bitfield< 9 >	sif
Bitfield< 8 >	hce
Bitfield< 7 >	scd
Bitfield< 7 >	smd
Bitfield< 6 >	nEt
Bitfield< 5 >	aw
Bitfield< 4 >	fw
Bitfield< 3 >	ea
Bitfield< 2 >	fiq
Bitfield< 1 >	irq
Bitfield< 0 >	ns
Bitfield< 29 >	afe
Bitfield< 28 >	tre
Bitfield< 27 >	nmfi
Bitfield< 26 >	uci
Bitfield< 25 >	ee
Bitfield< 24 >	ve
Bitfield< 24 >	e0e
Bitfield< 23 >	xp
Bitfield< 22 >	u
Bitfield< 21 >	fi
Bitfield< 20 >	uwxn
Bitfield< 19 >	dz
Bitfield< 19 >	wxn
Bitfield< 18 >	ntwe
Bitfield< 18 >	rao2
Bitfield< 16 >	ntwi
Bitfield< 16 >	rao3
Bitfield< 15 >	uct
Bitfield< 14 >	rr
Bitfield< 14 >	dze
Bitfield< 11 >	z
Bitfield< 10 >	sw
Bitfield< 9, 8 >	rs
Bitfield< 9 >	uma
Bitfield< 8 >	sed
Bitfield< 7 >	b
Bitfield< 7 >	itd
Bitfield< 6, 3 >	rao4
Bitfield< 6 >	thee
Bitfield< 5 >	cp15ben
Bitfield< 4 >	sa0
Bitfield< 3 >	sa
Bitfield< 0 >	m
Bitfield< 21, 20 >	fpen
Bitfield< 29, 28 >	rsvd
Bitfield< 30 >	d32dis
Bitfield< 31 >	asedis
	fsLow
Bitfield< 5, 0 >	status
Bitfield< 7, 4 >	domain
Bitfield< 9 >	lpae
Bitfield< 10 >	fsHigh
Bitfield< 11 >	wnr
Bitfield< 12 >	ext
Bitfield< 13 >	cm
Bitfield< 1 >	dzc
Bitfield< 2 >	ofc
Bitfield< 3 >	ufc
Bitfield< 4 >	ixc
Bitfield< 7 >	idc
Bitfield< 8 >	ioe
Bitfield< 10 >	ofe
Bitfield< 11 >	ufe
Bitfield< 12 >	ixe
Bitfield< 15 >	ide
Bitfield< 18, 16 >	len
Bitfield< 21, 20 >	stride
Bitfield< 23, 22 >	rMode
Bitfield< 24 >	fz
Bitfield< 25 >	dn
Bitfield< 26 >	ahp
Bitfield< 27 >	qc
Bitfield< 31 >	n
static const uint32_t	FpscrExcMask = 0x0000009F
static const uint32_t	FpscrQcMask = 0x08000000
Bitfield< 30 >	en
Bitfield< 29, 0 >	subArchDefined
	advSimdRegisters
Bitfield< 7, 4 >	singlePrecision
Bitfield< 11, 8 >	doublePrecision
Bitfield< 15, 12 >	vfpExceptionTrapping
Bitfield< 19, 16 >	divide
Bitfield< 23, 20 >	squareRoot
Bitfield< 27, 24 >	shortVectors
Bitfield< 31, 28 >	roundingModes
	flushToZero
Bitfield< 7, 4 >	defaultNaN
Bitfield< 11, 8 >	advSimdLoadStore
Bitfield< 15, 12 >	advSimdInteger
Bitfield< 19, 16 >	advSimdSinglePrecision
Bitfield< 23, 20 >	advSimdHalfPrecision
Bitfield< 27, 24 >	vfpHalfPrecision
Bitfield< 31, 28 >	raz
Bitfield< 4 >	pd0
Bitfield< 5 >	pd1
Bitfield< 5, 0 >	t0sz
Bitfield< 7 >	epd0
Bitfield< 9, 8 >	irgn0
Bitfield< 11, 10 >	orgn0
Bitfield< 13, 12 >	sh0
Bitfield< 14 >	tg0
Bitfield< 21, 16 >	t1sz
Bitfield< 22 >	a1
Bitfield< 23 >	epd1
Bitfield< 25, 24 >	irgn1
Bitfield< 27, 26 >	orgn1
Bitfield< 29, 28 >	sh1
Bitfield< 30 >	tg1
Bitfield< 34, 32 >	ips
Bitfield< 36 >	as
Bitfield< 37 >	tbi0
Bitfield< 38 >	tbi1
Bitfield< 31 >	eae
Bitfield< 18, 16 >	ps
Bitfield< 20 >	tbi
Bitfield< 4 >	s
Bitfield< 5, 0 >	t0sz64
Bitfield< 7, 6 >	sl0
	tr0
Bitfield< 3, 2 >	tr1
Bitfield< 5, 4 >	tr2
Bitfield< 7, 6 >	tr3
Bitfield< 9, 8 >	tr4
Bitfield< 11, 10 >	tr5
Bitfield< 13, 12 >	tr6
Bitfield< 15, 14 >	tr7
Bitfield< 16 >	ds0
Bitfield< 17 >	ds1
Bitfield< 18 >	ns0
Bitfield< 19 >	ns1
Bitfield< 24 >	nos0
Bitfield< 25 >	nos1
Bitfield< 26 >	nos2
Bitfield< 27 >	nos3
Bitfield< 28 >	nos4
Bitfield< 29 >	nos5
Bitfield< 30 >	nos6
Bitfield< 31 >	nos7
	ir0
Bitfield< 3, 2 >	ir1
Bitfield< 5, 4 >	ir2
Bitfield< 7, 6 >	ir3
Bitfield< 9, 8 >	ir4
Bitfield< 11, 10 >	ir5
Bitfield< 13, 12 >	ir6
Bitfield< 15, 14 >	ir7
Bitfield< 17, 16 >	or0
Bitfield< 19, 18 >	or1
Bitfield< 21, 20 >	or2
Bitfield< 23, 22 >	or3
Bitfield< 25, 24 >	or4
Bitfield< 27, 26 >	or5
Bitfield< 29, 28 >	or6
Bitfield< 31, 30 >	or7
	asid
Bitfield< 31, 8 >	procid
	sataRAMLatency
Bitfield< 4, 3 >	reserved_4_3
Bitfield< 5 >	dataRAMSetup
Bitfield< 8, 6 >	tagRAMLatency
Bitfield< 9 >	tagRAMSetup
Bitfield< 11, 10 >	dataRAMSlice
Bitfield< 12 >	tagRAMSlice
Bitfield< 20, 13 >	reserved_20_13
Bitfield< 21 >	eccandParityEnable
Bitfield< 22 >	reserved_22
Bitfield< 23 >	interptCtrlPresent
Bitfield< 25, 24 >	numCPUs
Bitfield< 30, 26 >	reserved_30_26
Bitfield< 31 >	l2rstDISABLE_monitor
	iCacheLineSize
Bitfield< 13, 4 >	raz_13_4
Bitfield< 15, 14 >	l1IndexPolicy
Bitfield< 19, 16 >	dCacheLineSize
Bitfield< 23, 20 >	erg
Bitfield< 27, 24 >	cwg
Bitfield< 28 >	raz_28
Bitfield< 31, 29 >	format
	sel
	attr
Bitfield< 39, 12 >	pa
Bitfield< 8, 7 >	sh
	ec
Bitfield< 15, 0 >	imm16
Bitfield< 13, 12 >	res1_13_12_el2
Bitfield< 9, 0 >	res1_9_0_el2
const int	MaxInstSrcRegs
const int	NumIntArchRegs = NUM_ARCH_INTREGS
const int	NumFloatV7ArchRegs = 64
const int	NumFloatV8ArchRegs = 128
const int	NumFloatSpecialRegs = 32
const int	NumIntRegs = NUM_INTREGS
const int	NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs
const int	NumCCRegs = NUM_CCREGS
const int	NumMiscRegs = NUM_MISCREGS
const int	TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs
const int	ReturnValueReg = 0
const int	ReturnValueReg1 = 1
const int	ReturnValueReg2 = 2
const int	NumArgumentRegs = 4
const int	NumArgumentRegs64 = 8
const int	ArgumentReg0 = 0
const int	ArgumentReg1 = 1
const int	ArgumentReg2 = 2
const int	ArgumentReg3 = 3
const int	FramePointerReg = 11
const int	StackPointerReg = INTREG_SP
const int	ReturnAddressReg = INTREG_LR
const int	PCReg = INTREG_PC
const int	ZeroReg = INTREG_ZERO
const int	SyscallNumReg = ReturnValueReg
const int	SyscallPseudoReturnReg = ReturnValueReg
const int	SyscallSuccessReg = ReturnValueReg
const int	FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1)
const int	CC_Reg_Base = FP_Reg_Base + NumFloatRegs
const int	Misc_Reg_Base = CC_Reg_Base + NumCCRegs
const int	Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
	cond
Bitfield< 3, 0 >	mask
Bitfield< 7, 2 >	top6
Bitfield< 1, 0 >	bottom2
	decoderFault
Bitfield< 55, 48 >	itstate
Bitfield< 55, 52 >	itstateCond
Bitfield< 51, 48 >	itstateMask
Bitfield< 41, 40 >	fpscrStride
Bitfield< 39, 37 >	fpscrLen
Bitfield< 36 >	thumb
Bitfield< 35 >	bigThumb
Bitfield< 34 >	aarch64
Bitfield< 33 >	sevenAndFour
Bitfield< 32 >	isMisc
uint32_t	instBits
Bitfield< 27, 25 >	encoding
Bitfield< 25 >	useImm
Bitfield< 24, 21 >	opcode
Bitfield< 24, 20 >	mediaOpcode
Bitfield< 24 >	opcode24
Bitfield< 24, 23 >	opcode24_23
Bitfield< 23, 20 >	opcode23_20
Bitfield< 23, 21 >	opcode23_21
Bitfield< 20 >	opcode20
Bitfield< 22 >	opcode22
Bitfield< 19, 16 >	opcode19_16
Bitfield< 19 >	opcode19
Bitfield< 18 >	opcode18
Bitfield< 15, 12 >	opcode15_12
Bitfield< 15 >	opcode15
Bitfield< 7, 4 >	miscOpcode
Bitfield< 7, 5 >	opc2
Bitfield< 7 >	opcode7
Bitfield< 6 >	opcode6
Bitfield< 4 >	opcode4
Bitfield< 31, 28 >	condCode
Bitfield< 20 >	sField
Bitfield< 19, 16 >	rn
Bitfield< 15, 12 >	rd
Bitfield< 15, 12 >	rt
Bitfield< 11, 7 >	shiftSize
Bitfield< 6, 5 >	shift
Bitfield< 3, 0 >	rm
Bitfield< 23 >	up
Bitfield< 22 >	psruser
Bitfield< 21 >	writeback
Bitfield< 20 >	loadOp
	pubwl
Bitfield< 7, 0 >	imm
Bitfield< 11, 8 >	rotate
Bitfield< 11, 0 >	immed11_0
Bitfield< 7, 0 >	immed7_0
Bitfield< 11, 8 >	immedHi11_8
Bitfield< 3, 0 >	immedLo3_0
Bitfield< 15, 0 >	regList
Bitfield< 23, 0 >	offset
Bitfield< 23, 0 >	immed23_0
Bitfield< 11, 8 >	cpNum
Bitfield< 18, 16 >	fn
Bitfield< 14, 12 >	fd
Bitfield< 3 >	fpRegImm
Bitfield< 3, 0 >	fm
Bitfield< 2, 0 >	fpImm
Bitfield< 24, 20 >	punwl
Bitfield< 15, 8 >	m5Func
Bitfield< 15, 13 >	topcode15_13
Bitfield< 13, 11 >	topcode13_11
Bitfield< 12, 11 >	topcode12_11
Bitfield< 12, 10 >	topcode12_10
Bitfield< 11, 9 >	topcode11_9
Bitfield< 11, 8 >	topcode11_8
Bitfield< 10, 9 >	topcode10_9
Bitfield< 10, 8 >	topcode10_8
Bitfield< 9, 6 >	topcode9_6
Bitfield< 7 >	topcode7
Bitfield< 7, 6 >	topcode7_6
Bitfield< 7, 5 >	topcode7_5
Bitfield< 7, 4 >	topcode7_4
Bitfield< 3, 0 >	topcode3_0
Bitfield< 28, 27 >	htopcode12_11
Bitfield< 26, 25 >	htopcode10_9
Bitfield< 25 >	htopcode9
Bitfield< 25, 24 >	htopcode9_8
Bitfield< 25, 21 >	htopcode9_5
Bitfield< 25, 20 >	htopcode9_4
Bitfield< 24 >	htopcode8
Bitfield< 24, 23 >	htopcode8_7
Bitfield< 24, 22 >	htopcode8_6
Bitfield< 24, 21 >	htopcode8_5
Bitfield< 23 >	htopcode7
Bitfield< 23, 21 >	htopcode7_5
Bitfield< 22 >	htopcode6
Bitfield< 22, 21 >	htopcode6_5
Bitfield< 21, 20 >	htopcode5_4
Bitfield< 20 >	htopcode4
Bitfield< 19, 16 >	htrn
Bitfield< 20 >	hts
Bitfield< 15 >	ltopcode15
Bitfield< 11, 8 >	ltopcode11_8
Bitfield< 7, 6 >	ltopcode7_6
Bitfield< 7, 4 >	ltopcode7_4
Bitfield< 4 >	ltopcode4
Bitfield< 11, 8 >	ltrd
Bitfield< 11, 8 >	ltcoproc

Typedef Documentation

typedef uint64_t ArmISA::CCReg

Definition at line 73 of file registers.hh.

typedef Addr ArmISA::FaultOffset

Definition at line 61 of file faults.hh.

typedef float ArmISA::FloatReg

Definition at line 67 of file registers.hh.

typedef uint32_t ArmISA::FloatRegBits

Definition at line 66 of file registers.hh.

typedef uint64_t ArmISA::IntReg

Definition at line 63 of file registers.hh.

typedef IntRegIndex ArmISA::IntRegMap[NUM_ARCH_INTREGS]

Definition at line 304 of file intregs.hh.

typedef uint32_t ArmISA::MachInst

Definition at line 54 of file types.hh.

typedef uint64_t ArmISA::MiscReg

Definition at line 70 of file registers.hh.

typedef int ArmISA::RegContextParam

Definition at line 527 of file types.hh.

typedef int ArmISA::RegContextVal

Definition at line 528 of file types.hh.

typedef uint16_t ArmISA::RegIndex

Definition at line 61 of file registers.hh.

typedef int ArmISA::VfpSavedState

Definition at line 213 of file vfp.hh.

typedef uint64_t ArmISA::XReg

Definition at line 50 of file neon64_mem.hh.

Enumeration Type Documentation

enum ArmISA::ArmExtendType

Enumerator
UXTB
UXTH
UXTW
UXTX
SXTB
SXTH
SXTW
SXTX

Definition at line 516 of file types.hh.

enum ArmISA::ArmShiftType

Enumerator
LSL
LSR
ASR
ROR

Definition at line 508 of file types.hh.

enum ArmISA::ccRegIndex

Enumerator
CCREG_NZ
CCREG_C
CCREG_V
CCREG_GE
CCREG_FP
CCREG_ZERO
NUM_CCREGS

Definition at line 45 of file ccregs.hh.

enum ArmISA::ConditionCode

Enumerator
COND_EQ
COND_NE
COND_CS
COND_CC
COND_MI
COND_PL
COND_VS
COND_VC
COND_HI
COND_LS
COND_GE
COND_LT
COND_GT
COND_LE
COND_AL
COND_UC

Definition at line 64 of file ccregs.hh.

enum ArmISA::ConvertType

Enumerator
SINGLE_TO_DOUBLE
SINGLE_TO_WORD
SINGLE_TO_LONG
DOUBLE_TO_SINGLE
DOUBLE_TO_WORD
DOUBLE_TO_LONG
LONG_TO_SINGLE
LONG_TO_DOUBLE
LONG_TO_WORD
LONG_TO_PS
WORD_TO_SINGLE
WORD_TO_DOUBLE
WORD_TO_LONG
WORD_TO_PS
PL_TO_SINGLE
PU_TO_SINGLE

Definition at line 531 of file types.hh.

enum ArmISA::DecoderFault : std::uint8_t

Instruction decoder fault codes in ExtMachInst.

Enumerator
OK	No fault.
UNALIGNED	Unaligned instruction fault.
PANIC	Internal gem5 error.

Definition at line 630 of file types.hh.

enum ArmISA::ExceptionClass

Enumerator
EC_INVALID
EC_UNKNOWN
EC_TRAPPED_WFI_WFE
EC_TRAPPED_CP15_MCR_MRC
EC_TRAPPED_CP15_MCRR_MRRC
EC_TRAPPED_CP14_MCR_MRC
EC_TRAPPED_CP14_LDC_STC
EC_TRAPPED_HCPTR
EC_TRAPPED_SIMD_FP
EC_TRAPPED_CP10_MRC_VMRS
EC_TRAPPED_BXJ
EC_TRAPPED_CP14_MCRR_MRRC
EC_ILLEGAL_INST
EC_SVC_TO_HYP
EC_SVC
EC_HVC
EC_SMC_TO_HYP
EC_SMC
EC_SVC_64
EC_HVC_64
EC_SMC_64
EC_TRAPPED_MSR_MRS_64
EC_PREFETCH_ABORT_TO_HYP
EC_PREFETCH_ABORT_LOWER_EL
EC_PREFETCH_ABORT_FROM_HYP
EC_PREFETCH_ABORT_CURR_EL
EC_PC_ALIGNMENT
EC_DATA_ABORT_TO_HYP
EC_DATA_ABORT_LOWER_EL
EC_DATA_ABORT_FROM_HYP
EC_DATA_ABORT_CURR_EL
EC_STACK_PTR_ALIGNMENT
EC_FP_EXCEPTION
EC_FP_EXCEPTION_64
EC_SERROR

Definition at line 589 of file types.hh.

enum ArmISA::ExceptionLevel

Enumerator
EL0
EL1
EL2
EL3

Definition at line 562 of file types.hh.

enum ArmISA::FeExceptionBit

Enumerator
FeDivByZero
FeInexact
FeInvalid
FeOverflow
FeUnderflow
FeAllExceptions

Definition at line 84 of file vfp.hh.

enum ArmISA::FeRoundingMode

Enumerator
FeRoundDown
FeRoundNearest
FeRoundZero
FeRoundUpward

Definition at line 94 of file vfp.hh.

enum ArmISA::FPRounding

Enumerator
FPRounding_TIEEVEN
FPRounding_POSINF
FPRounding_NEGINF
FPRounding_ZERO
FPRounding_TIEAWAY
FPRounding_ODD

Definition at line 59 of file fplib.hh.

enum ArmISA::InterruptTypes

Enumerator
INT_RST
INT_ABT
INT_IRQ
INT_FIQ
INT_SEV
INT_VIRT_IRQ
INT_VIRT_FIQ
NumInterruptTypes

Definition at line 112 of file isa_traits.hh.

enum ArmISA::IntRegIndex

Enumerator
INTREG_R0
INTREG_R1
INTREG_R2
INTREG_R3
INTREG_R4
INTREG_R5
INTREG_R6
INTREG_R7
INTREG_R8
INTREG_R9
INTREG_R10
INTREG_R11
INTREG_R12
INTREG_R13
INTREG_SP
INTREG_R14
INTREG_LR
INTREG_R15
INTREG_PC
INTREG_R13_SVC
INTREG_SP_SVC
INTREG_R14_SVC
INTREG_LR_SVC
INTREG_R13_MON
INTREG_SP_MON
INTREG_R14_MON
INTREG_LR_MON
INTREG_R13_HYP
INTREG_SP_HYP
INTREG_R13_ABT
INTREG_SP_ABT
INTREG_R14_ABT
INTREG_LR_ABT
INTREG_R13_UND
INTREG_SP_UND
INTREG_R14_UND
INTREG_LR_UND
INTREG_R13_IRQ
INTREG_SP_IRQ
INTREG_R14_IRQ
INTREG_LR_IRQ
INTREG_R8_FIQ
INTREG_R9_FIQ
INTREG_R10_FIQ
INTREG_R11_FIQ
INTREG_R12_FIQ
INTREG_R13_FIQ
INTREG_SP_FIQ
INTREG_R14_FIQ
INTREG_LR_FIQ
INTREG_ZERO
INTREG_UREG0
INTREG_UREG1
INTREG_UREG2
INTREG_DUMMY
INTREG_SP0
INTREG_SP1
INTREG_SP2
INTREG_SP3
NUM_INTREGS
NUM_ARCH_INTREGS
INTREG_X0
INTREG_X1
INTREG_X2
INTREG_X3
INTREG_X4
INTREG_X5
INTREG_X6
INTREG_X7
INTREG_X8
INTREG_X9
INTREG_X10
INTREG_X11
INTREG_X12
INTREG_X13
INTREG_X14
INTREG_X15
INTREG_X16
INTREG_X17
INTREG_X18
INTREG_X19
INTREG_X20
INTREG_X21
INTREG_X22
INTREG_X23
INTREG_X24
INTREG_X25
INTREG_X26
INTREG_X27
INTREG_X28
INTREG_X29
INTREG_X30
INTREG_X31
INTREG_SPX
INTREG_R0_USR
INTREG_R1_USR
INTREG_R2_USR
INTREG_R3_USR
INTREG_R4_USR
INTREG_R5_USR
INTREG_R6_USR
INTREG_R7_USR
INTREG_R8_USR
INTREG_R9_USR
INTREG_R10_USR
INTREG_R11_USR
INTREG_R12_USR
INTREG_R13_USR
INTREG_SP_USR
INTREG_R14_USR
INTREG_LR_USR
INTREG_R15_USR
INTREG_PC_USR
INTREG_R0_SVC
INTREG_R1_SVC
INTREG_R2_SVC
INTREG_R3_SVC
INTREG_R4_SVC
INTREG_R5_SVC
INTREG_R6_SVC
INTREG_R7_SVC
INTREG_R8_SVC
INTREG_R9_SVC
INTREG_R10_SVC
INTREG_R11_SVC
INTREG_R12_SVC
INTREG_PC_SVC
INTREG_R15_SVC
INTREG_R0_MON
INTREG_R1_MON
INTREG_R2_MON
INTREG_R3_MON
INTREG_R4_MON
INTREG_R5_MON
INTREG_R6_MON
INTREG_R7_MON
INTREG_R8_MON
INTREG_R9_MON
INTREG_R10_MON
INTREG_R11_MON
INTREG_R12_MON
INTREG_PC_MON
INTREG_R15_MON
INTREG_R0_ABT
INTREG_R1_ABT
INTREG_R2_ABT
INTREG_R3_ABT
INTREG_R4_ABT
INTREG_R5_ABT
INTREG_R6_ABT
INTREG_R7_ABT
INTREG_R8_ABT
INTREG_R9_ABT
INTREG_R10_ABT
INTREG_R11_ABT
INTREG_R12_ABT
INTREG_PC_ABT
INTREG_R15_ABT
INTREG_R0_HYP
INTREG_R1_HYP
INTREG_R2_HYP
INTREG_R3_HYP
INTREG_R4_HYP
INTREG_R5_HYP
INTREG_R6_HYP
INTREG_R7_HYP
INTREG_R8_HYP
INTREG_R9_HYP
INTREG_R10_HYP
INTREG_R11_HYP
INTREG_R12_HYP
INTREG_LR_HYP
INTREG_R14_HYP
INTREG_PC_HYP
INTREG_R15_HYP
INTREG_R0_UND
INTREG_R1_UND
INTREG_R2_UND
INTREG_R3_UND
INTREG_R4_UND
INTREG_R5_UND
INTREG_R6_UND
INTREG_R7_UND
INTREG_R8_UND
INTREG_R9_UND
INTREG_R10_UND
INTREG_R11_UND
INTREG_R12_UND
INTREG_PC_UND
INTREG_R15_UND
INTREG_R0_IRQ
INTREG_R1_IRQ
INTREG_R2_IRQ
INTREG_R3_IRQ
INTREG_R4_IRQ
INTREG_R5_IRQ
INTREG_R6_IRQ
INTREG_R7_IRQ
INTREG_R8_IRQ
INTREG_R9_IRQ
INTREG_R10_IRQ
INTREG_R11_IRQ
INTREG_R12_IRQ
INTREG_PC_IRQ
INTREG_R15_IRQ
INTREG_R0_FIQ
INTREG_R1_FIQ
INTREG_R2_FIQ
INTREG_R3_FIQ
INTREG_R4_FIQ
INTREG_R5_FIQ
INTREG_R6_FIQ
INTREG_R7_FIQ
INTREG_PC_FIQ
INTREG_R15_FIQ

Definition at line 53 of file intregs.hh.

enum ArmISA::LookupLevel

Enumerator
L0
L1
L2
L3
MAX_LOOKUP_LEVELS

Definition at line 77 of file pagetable.hh.

enum ArmISA::MiscRegIndex

Enumerator
MISCREG_CPSR
MISCREG_SPSR
MISCREG_SPSR_FIQ
MISCREG_SPSR_IRQ
MISCREG_SPSR_SVC
MISCREG_SPSR_MON
MISCREG_SPSR_ABT
MISCREG_SPSR_HYP
MISCREG_SPSR_UND
MISCREG_ELR_HYP
MISCREG_FPSID
MISCREG_FPSCR
MISCREG_MVFR1
MISCREG_MVFR0
MISCREG_FPEXC
MISCREG_CPSR_MODE
MISCREG_CPSR_Q
MISCREG_FPSCR_EXC
MISCREG_FPSCR_QC
MISCREG_LOCKADDR
MISCREG_LOCKFLAG
MISCREG_PRRR_MAIR0
MISCREG_PRRR_MAIR0_NS
MISCREG_PRRR_MAIR0_S
MISCREG_NMRR_MAIR1
MISCREG_NMRR_MAIR1_NS
MISCREG_NMRR_MAIR1_S
MISCREG_PMXEVTYPER_PMCCFILTR
MISCREG_SCTLR_RST
MISCREG_SEV_MAILBOX
MISCREG_DBGDIDR
MISCREG_DBGDSCRint
MISCREG_DBGDCCINT
MISCREG_DBGDTRTXint
MISCREG_DBGDTRRXint
MISCREG_DBGWFAR
MISCREG_DBGVCR
MISCREG_DBGDTRRXext
MISCREG_DBGDSCRext
MISCREG_DBGDTRTXext
MISCREG_DBGOSECCR
MISCREG_DBGBVR0
MISCREG_DBGBVR1
MISCREG_DBGBVR2
MISCREG_DBGBVR3
MISCREG_DBGBVR4
MISCREG_DBGBVR5
MISCREG_DBGBCR0
MISCREG_DBGBCR1
MISCREG_DBGBCR2
MISCREG_DBGBCR3
MISCREG_DBGBCR4
MISCREG_DBGBCR5
MISCREG_DBGWVR0
MISCREG_DBGWVR1
MISCREG_DBGWVR2
MISCREG_DBGWVR3
MISCREG_DBGWCR0
MISCREG_DBGWCR1
MISCREG_DBGWCR2
MISCREG_DBGWCR3
MISCREG_DBGDRAR
MISCREG_DBGBXVR4
MISCREG_DBGBXVR5
MISCREG_DBGOSLAR
MISCREG_DBGOSLSR
MISCREG_DBGOSDLR
MISCREG_DBGPRCR
MISCREG_DBGDSAR
MISCREG_DBGCLAIMSET
MISCREG_DBGCLAIMCLR
MISCREG_DBGAUTHSTATUS
MISCREG_DBGDEVID2
MISCREG_DBGDEVID1
MISCREG_DBGDEVID0
MISCREG_TEECR
MISCREG_JIDR
MISCREG_TEEHBR
MISCREG_JOSCR
MISCREG_JMCR
MISCREG_MIDR
MISCREG_CTR
MISCREG_TCMTR
MISCREG_TLBTR
MISCREG_MPIDR
MISCREG_REVIDR
MISCREG_ID_PFR0
MISCREG_ID_PFR1
MISCREG_ID_DFR0
MISCREG_ID_AFR0
MISCREG_ID_MMFR0
MISCREG_ID_MMFR1
MISCREG_ID_MMFR2
MISCREG_ID_MMFR3
MISCREG_ID_ISAR0
MISCREG_ID_ISAR1
MISCREG_ID_ISAR2
MISCREG_ID_ISAR3
MISCREG_ID_ISAR4
MISCREG_ID_ISAR5
MISCREG_CCSIDR
MISCREG_CLIDR
MISCREG_AIDR
MISCREG_CSSELR
MISCREG_CSSELR_NS
MISCREG_CSSELR_S
MISCREG_VPIDR
MISCREG_VMPIDR
MISCREG_SCTLR
MISCREG_SCTLR_NS
MISCREG_SCTLR_S
MISCREG_ACTLR
MISCREG_ACTLR_NS
MISCREG_ACTLR_S
MISCREG_CPACR
MISCREG_SCR
MISCREG_SDER
MISCREG_NSACR
MISCREG_HSCTLR
MISCREG_HACTLR
MISCREG_HCR
MISCREG_HDCR
MISCREG_HCPTR
MISCREG_HSTR
MISCREG_HACR
MISCREG_TTBR0
MISCREG_TTBR0_NS
MISCREG_TTBR0_S
MISCREG_TTBR1
MISCREG_TTBR1_NS
MISCREG_TTBR1_S
MISCREG_TTBCR
MISCREG_TTBCR_NS
MISCREG_TTBCR_S
MISCREG_HTCR
MISCREG_VTCR
MISCREG_DACR
MISCREG_DACR_NS
MISCREG_DACR_S
MISCREG_DFSR
MISCREG_DFSR_NS
MISCREG_DFSR_S
MISCREG_IFSR
MISCREG_IFSR_NS
MISCREG_IFSR_S
MISCREG_ADFSR
MISCREG_ADFSR_NS
MISCREG_ADFSR_S
MISCREG_AIFSR
MISCREG_AIFSR_NS
MISCREG_AIFSR_S
MISCREG_HADFSR
MISCREG_HAIFSR
MISCREG_HSR
MISCREG_DFAR
MISCREG_DFAR_NS
MISCREG_DFAR_S
MISCREG_IFAR
MISCREG_IFAR_NS
MISCREG_IFAR_S
MISCREG_HDFAR
MISCREG_HIFAR
MISCREG_HPFAR
MISCREG_ICIALLUIS
MISCREG_BPIALLIS
MISCREG_PAR
MISCREG_PAR_NS
MISCREG_PAR_S
MISCREG_ICIALLU
MISCREG_ICIMVAU
MISCREG_CP15ISB
MISCREG_BPIALL
MISCREG_BPIMVA
MISCREG_DCIMVAC
MISCREG_DCISW
MISCREG_ATS1CPR
MISCREG_ATS1CPW
MISCREG_ATS1CUR
MISCREG_ATS1CUW
MISCREG_ATS12NSOPR
MISCREG_ATS12NSOPW
MISCREG_ATS12NSOUR
MISCREG_ATS12NSOUW
MISCREG_DCCMVAC
MISCREG_DCCSW
MISCREG_CP15DSB
MISCREG_CP15DMB
MISCREG_DCCMVAU
MISCREG_DCCIMVAC
MISCREG_DCCISW
MISCREG_ATS1HR
MISCREG_ATS1HW
MISCREG_TLBIALLIS
MISCREG_TLBIMVAIS
MISCREG_TLBIASIDIS
MISCREG_TLBIMVAAIS
MISCREG_TLBIMVALIS
MISCREG_TLBIMVAALIS
MISCREG_ITLBIALL
MISCREG_ITLBIMVA
MISCREG_ITLBIASID
MISCREG_DTLBIALL
MISCREG_DTLBIMVA
MISCREG_DTLBIASID
MISCREG_TLBIALL
MISCREG_TLBIMVA
MISCREG_TLBIASID
MISCREG_TLBIMVAA
MISCREG_TLBIMVAL
MISCREG_TLBIMVAAL
MISCREG_TLBIIPAS2IS
MISCREG_TLBIIPAS2LIS
MISCREG_TLBIALLHIS
MISCREG_TLBIMVAHIS
MISCREG_TLBIALLNSNHIS
MISCREG_TLBIMVALHIS
MISCREG_TLBIIPAS2
MISCREG_TLBIIPAS2L
MISCREG_TLBIALLH
MISCREG_TLBIMVAH
MISCREG_TLBIALLNSNH
MISCREG_TLBIMVALH
MISCREG_PMCR
MISCREG_PMCNTENSET
MISCREG_PMCNTENCLR
MISCREG_PMOVSR
MISCREG_PMSWINC
MISCREG_PMSELR
MISCREG_PMCEID0
MISCREG_PMCEID1
MISCREG_PMCCNTR
MISCREG_PMXEVTYPER
MISCREG_PMCCFILTR
MISCREG_PMXEVCNTR
MISCREG_PMUSERENR
MISCREG_PMINTENSET
MISCREG_PMINTENCLR
MISCREG_PMOVSSET
MISCREG_L2CTLR
MISCREG_L2ECTLR
MISCREG_PRRR
MISCREG_PRRR_NS
MISCREG_PRRR_S
MISCREG_MAIR0
MISCREG_MAIR0_NS
MISCREG_MAIR0_S
MISCREG_NMRR
MISCREG_NMRR_NS
MISCREG_NMRR_S
MISCREG_MAIR1
MISCREG_MAIR1_NS
MISCREG_MAIR1_S
MISCREG_AMAIR0
MISCREG_AMAIR0_NS
MISCREG_AMAIR0_S
MISCREG_AMAIR1
MISCREG_AMAIR1_NS
MISCREG_AMAIR1_S
MISCREG_HMAIR0
MISCREG_HMAIR1
MISCREG_HAMAIR0
MISCREG_HAMAIR1
MISCREG_VBAR
MISCREG_VBAR_NS
MISCREG_VBAR_S
MISCREG_MVBAR
MISCREG_RMR
MISCREG_ISR
MISCREG_HVBAR
MISCREG_FCSEIDR
MISCREG_CONTEXTIDR
MISCREG_CONTEXTIDR_NS
MISCREG_CONTEXTIDR_S
MISCREG_TPIDRURW
MISCREG_TPIDRURW_NS
MISCREG_TPIDRURW_S
MISCREG_TPIDRURO
MISCREG_TPIDRURO_NS
MISCREG_TPIDRURO_S
MISCREG_TPIDRPRW
MISCREG_TPIDRPRW_NS
MISCREG_TPIDRPRW_S
MISCREG_HTPIDR
MISCREG_CNTFRQ
MISCREG_CNTKCTL
MISCREG_CNTP_TVAL
MISCREG_CNTP_TVAL_NS
MISCREG_CNTP_TVAL_S
MISCREG_CNTP_CTL
MISCREG_CNTP_CTL_NS
MISCREG_CNTP_CTL_S
MISCREG_CNTV_TVAL
MISCREG_CNTV_CTL
MISCREG_CNTHCTL
MISCREG_CNTHP_TVAL
MISCREG_CNTHP_CTL
MISCREG_IL1DATA0
MISCREG_IL1DATA1
MISCREG_IL1DATA2
MISCREG_IL1DATA3
MISCREG_DL1DATA0
MISCREG_DL1DATA1
MISCREG_DL1DATA2
MISCREG_DL1DATA3
MISCREG_DL1DATA4
MISCREG_RAMINDEX
MISCREG_L2ACTLR
MISCREG_CBAR
MISCREG_HTTBR
MISCREG_VTTBR
MISCREG_CNTPCT
MISCREG_CNTVCT
MISCREG_CNTP_CVAL
MISCREG_CNTP_CVAL_NS
MISCREG_CNTP_CVAL_S
MISCREG_CNTV_CVAL
MISCREG_CNTVOFF
MISCREG_CNTHP_CVAL
MISCREG_CPUMERRSR
MISCREG_L2MERRSR
MISCREG_MDCCINT_EL1
MISCREG_OSDTRRX_EL1
MISCREG_MDSCR_EL1
MISCREG_OSDTRTX_EL1
MISCREG_OSECCR_EL1
MISCREG_DBGBVR0_EL1
MISCREG_DBGBVR1_EL1
MISCREG_DBGBVR2_EL1
MISCREG_DBGBVR3_EL1
MISCREG_DBGBVR4_EL1
MISCREG_DBGBVR5_EL1
MISCREG_DBGBCR0_EL1
MISCREG_DBGBCR1_EL1
MISCREG_DBGBCR2_EL1
MISCREG_DBGBCR3_EL1
MISCREG_DBGBCR4_EL1
MISCREG_DBGBCR5_EL1
MISCREG_DBGWVR0_EL1
MISCREG_DBGWVR1_EL1
MISCREG_DBGWVR2_EL1
MISCREG_DBGWVR3_EL1
MISCREG_DBGWCR0_EL1
MISCREG_DBGWCR1_EL1
MISCREG_DBGWCR2_EL1
MISCREG_DBGWCR3_EL1
MISCREG_MDCCSR_EL0
MISCREG_MDDTR_EL0
MISCREG_MDDTRTX_EL0
MISCREG_MDDTRRX_EL0
MISCREG_DBGVCR32_EL2
MISCREG_MDRAR_EL1
MISCREG_OSLAR_EL1
MISCREG_OSLSR_EL1
MISCREG_OSDLR_EL1
MISCREG_DBGPRCR_EL1
MISCREG_DBGCLAIMSET_EL1
MISCREG_DBGCLAIMCLR_EL1
MISCREG_DBGAUTHSTATUS_EL1
MISCREG_TEECR32_EL1
MISCREG_TEEHBR32_EL1
MISCREG_MIDR_EL1
MISCREG_MPIDR_EL1
MISCREG_REVIDR_EL1
MISCREG_ID_PFR0_EL1
MISCREG_ID_PFR1_EL1
MISCREG_ID_DFR0_EL1
MISCREG_ID_AFR0_EL1
MISCREG_ID_MMFR0_EL1
MISCREG_ID_MMFR1_EL1
MISCREG_ID_MMFR2_EL1
MISCREG_ID_MMFR3_EL1
MISCREG_ID_ISAR0_EL1
MISCREG_ID_ISAR1_EL1
MISCREG_ID_ISAR2_EL1
MISCREG_ID_ISAR3_EL1
MISCREG_ID_ISAR4_EL1
MISCREG_ID_ISAR5_EL1
MISCREG_MVFR0_EL1
MISCREG_MVFR1_EL1
MISCREG_MVFR2_EL1
MISCREG_ID_AA64PFR0_EL1
MISCREG_ID_AA64PFR1_EL1
MISCREG_ID_AA64DFR0_EL1
MISCREG_ID_AA64DFR1_EL1
MISCREG_ID_AA64AFR0_EL1
MISCREG_ID_AA64AFR1_EL1
MISCREG_ID_AA64ISAR0_EL1
MISCREG_ID_AA64ISAR1_EL1
MISCREG_ID_AA64MMFR0_EL1
MISCREG_ID_AA64MMFR1_EL1
MISCREG_CCSIDR_EL1
MISCREG_CLIDR_EL1
MISCREG_AIDR_EL1
MISCREG_CSSELR_EL1
MISCREG_CTR_EL0
MISCREG_DCZID_EL0
MISCREG_VPIDR_EL2
MISCREG_VMPIDR_EL2
MISCREG_SCTLR_EL1
MISCREG_ACTLR_EL1
MISCREG_CPACR_EL1
MISCREG_SCTLR_EL2
MISCREG_ACTLR_EL2
MISCREG_HCR_EL2
MISCREG_MDCR_EL2
MISCREG_CPTR_EL2
MISCREG_HSTR_EL2
MISCREG_HACR_EL2
MISCREG_SCTLR_EL3
MISCREG_ACTLR_EL3
MISCREG_SCR_EL3
MISCREG_SDER32_EL3
MISCREG_CPTR_EL3
MISCREG_MDCR_EL3
MISCREG_TTBR0_EL1
MISCREG_TTBR1_EL1
MISCREG_TCR_EL1
MISCREG_TTBR0_EL2
MISCREG_TCR_EL2
MISCREG_VTTBR_EL2
MISCREG_VTCR_EL2
MISCREG_TTBR0_EL3
MISCREG_TCR_EL3
MISCREG_DACR32_EL2
MISCREG_SPSR_EL1
MISCREG_ELR_EL1
MISCREG_SP_EL0
MISCREG_SPSEL
MISCREG_CURRENTEL
MISCREG_NZCV
MISCREG_DAIF
MISCREG_FPCR
MISCREG_FPSR
MISCREG_DSPSR_EL0
MISCREG_DLR_EL0
MISCREG_SPSR_EL2
MISCREG_ELR_EL2
MISCREG_SP_EL1
MISCREG_SPSR_IRQ_AA64
MISCREG_SPSR_ABT_AA64
MISCREG_SPSR_UND_AA64
MISCREG_SPSR_FIQ_AA64
MISCREG_SPSR_EL3
MISCREG_ELR_EL3
MISCREG_SP_EL2
MISCREG_AFSR0_EL1
MISCREG_AFSR1_EL1
MISCREG_ESR_EL1
MISCREG_IFSR32_EL2
MISCREG_AFSR0_EL2
MISCREG_AFSR1_EL2
MISCREG_ESR_EL2
MISCREG_FPEXC32_EL2
MISCREG_AFSR0_EL3
MISCREG_AFSR1_EL3
MISCREG_ESR_EL3
MISCREG_FAR_EL1
MISCREG_FAR_EL2
MISCREG_HPFAR_EL2
MISCREG_FAR_EL3
MISCREG_IC_IALLUIS
MISCREG_PAR_EL1
MISCREG_IC_IALLU
MISCREG_DC_IVAC_Xt
MISCREG_DC_ISW_Xt
MISCREG_AT_S1E1R_Xt
MISCREG_AT_S1E1W_Xt
MISCREG_AT_S1E0R_Xt
MISCREG_AT_S1E0W_Xt
MISCREG_DC_CSW_Xt
MISCREG_DC_CISW_Xt
MISCREG_DC_ZVA_Xt
MISCREG_IC_IVAU_Xt
MISCREG_DC_CVAC_Xt
MISCREG_DC_CVAU_Xt
MISCREG_DC_CIVAC_Xt
MISCREG_AT_S1E2R_Xt
MISCREG_AT_S1E2W_Xt
MISCREG_AT_S12E1R_Xt
MISCREG_AT_S12E1W_Xt
MISCREG_AT_S12E0R_Xt
MISCREG_AT_S12E0W_Xt
MISCREG_AT_S1E3R_Xt
MISCREG_AT_S1E3W_Xt
MISCREG_TLBI_VMALLE1IS
MISCREG_TLBI_VAE1IS_Xt
MISCREG_TLBI_ASIDE1IS_Xt
MISCREG_TLBI_VAAE1IS_Xt
MISCREG_TLBI_VALE1IS_Xt
MISCREG_TLBI_VAALE1IS_Xt
MISCREG_TLBI_VMALLE1
MISCREG_TLBI_VAE1_Xt
MISCREG_TLBI_ASIDE1_Xt
MISCREG_TLBI_VAAE1_Xt
MISCREG_TLBI_VALE1_Xt
MISCREG_TLBI_VAALE1_Xt
MISCREG_TLBI_IPAS2E1IS_Xt
MISCREG_TLBI_IPAS2LE1IS_Xt
MISCREG_TLBI_ALLE2IS
MISCREG_TLBI_VAE2IS_Xt
MISCREG_TLBI_ALLE1IS
MISCREG_TLBI_VALE2IS_Xt
MISCREG_TLBI_VMALLS12E1IS
MISCREG_TLBI_IPAS2E1_Xt
MISCREG_TLBI_IPAS2LE1_Xt
MISCREG_TLBI_ALLE2
MISCREG_TLBI_VAE2_Xt
MISCREG_TLBI_ALLE1
MISCREG_TLBI_VALE2_Xt
MISCREG_TLBI_VMALLS12E1
MISCREG_TLBI_ALLE3IS
MISCREG_TLBI_VAE3IS_Xt
MISCREG_TLBI_VALE3IS_Xt
MISCREG_TLBI_ALLE3
MISCREG_TLBI_VAE3_Xt
MISCREG_TLBI_VALE3_Xt
MISCREG_PMINTENSET_EL1
MISCREG_PMINTENCLR_EL1
MISCREG_PMCR_EL0
MISCREG_PMCNTENSET_EL0
MISCREG_PMCNTENCLR_EL0
MISCREG_PMOVSCLR_EL0
MISCREG_PMSWINC_EL0
MISCREG_PMSELR_EL0
MISCREG_PMCEID0_EL0
MISCREG_PMCEID1_EL0
MISCREG_PMCCNTR_EL0
MISCREG_PMXEVTYPER_EL0
MISCREG_PMCCFILTR_EL0
MISCREG_PMXEVCNTR_EL0
MISCREG_PMUSERENR_EL0
MISCREG_PMOVSSET_EL0
MISCREG_MAIR_EL1
MISCREG_AMAIR_EL1
MISCREG_MAIR_EL2
MISCREG_AMAIR_EL2
MISCREG_MAIR_EL3
MISCREG_AMAIR_EL3
MISCREG_L2CTLR_EL1
MISCREG_L2ECTLR_EL1
MISCREG_VBAR_EL1
MISCREG_RVBAR_EL1
MISCREG_ISR_EL1
MISCREG_VBAR_EL2
MISCREG_RVBAR_EL2
MISCREG_VBAR_EL3
MISCREG_RVBAR_EL3
MISCREG_RMR_EL3
MISCREG_CONTEXTIDR_EL1
MISCREG_TPIDR_EL1
MISCREG_TPIDR_EL0
MISCREG_TPIDRRO_EL0
MISCREG_TPIDR_EL2
MISCREG_TPIDR_EL3
MISCREG_CNTKCTL_EL1
MISCREG_CNTFRQ_EL0
MISCREG_CNTPCT_EL0
MISCREG_CNTVCT_EL0
MISCREG_CNTP_TVAL_EL0
MISCREG_CNTP_CTL_EL0
MISCREG_CNTP_CVAL_EL0
MISCREG_CNTV_TVAL_EL0
MISCREG_CNTV_CTL_EL0
MISCREG_CNTV_CVAL_EL0
MISCREG_PMEVCNTR0_EL0
MISCREG_PMEVCNTR1_EL0
MISCREG_PMEVCNTR2_EL0
MISCREG_PMEVCNTR3_EL0
MISCREG_PMEVCNTR4_EL0
MISCREG_PMEVCNTR5_EL0
MISCREG_PMEVTYPER0_EL0
MISCREG_PMEVTYPER1_EL0
MISCREG_PMEVTYPER2_EL0
MISCREG_PMEVTYPER3_EL0
MISCREG_PMEVTYPER4_EL0
MISCREG_PMEVTYPER5_EL0
MISCREG_CNTVOFF_EL2
MISCREG_CNTHCTL_EL2
MISCREG_CNTHP_TVAL_EL2
MISCREG_CNTHP_CTL_EL2
MISCREG_CNTHP_CVAL_EL2
MISCREG_CNTPS_TVAL_EL1
MISCREG_CNTPS_CTL_EL1
MISCREG_CNTPS_CVAL_EL1
MISCREG_IL1DATA0_EL1
MISCREG_IL1DATA1_EL1
MISCREG_IL1DATA2_EL1
MISCREG_IL1DATA3_EL1
MISCREG_DL1DATA0_EL1
MISCREG_DL1DATA1_EL1
MISCREG_DL1DATA2_EL1
MISCREG_DL1DATA3_EL1
MISCREG_DL1DATA4_EL1
MISCREG_L2ACTLR_EL1
MISCREG_CPUACTLR_EL1
MISCREG_CPUECTLR_EL1
MISCREG_CPUMERRSR_EL1
MISCREG_L2MERRSR_EL1
MISCREG_CBAR_EL1
MISCREG_CONTEXTIDR_EL2
MISCREG_NOP
MISCREG_RAZ
MISCREG_CP14_UNIMPL
MISCREG_CP15_UNIMPL
MISCREG_A64_UNIMPL
MISCREG_UNKNOWN
NUM_MISCREGS

Definition at line 57 of file miscregs.hh.

enum ArmISA::MiscRegInfo

Enumerator
MISCREG_IMPLEMENTED
MISCREG_UNVERIFIABLE
MISCREG_WARN_NOT_FAIL
MISCREG_MUTEX
MISCREG_BANKED
MISCREG_BANKED_CHILD
MISCREG_USR_NS_RD
MISCREG_USR_NS_WR
MISCREG_USR_S_RD
MISCREG_USR_S_WR
MISCREG_PRI_NS_RD
MISCREG_PRI_NS_WR
MISCREG_PRI_S_RD
MISCREG_PRI_S_WR
MISCREG_HYP_RD
MISCREG_HYP_WR
MISCREG_MON_NS0_RD
MISCREG_MON_NS0_WR
MISCREG_MON_NS1_RD
MISCREG_MON_NS1_WR
NUM_MISCREG_INFOS

Definition at line 680 of file miscregs.hh.

enum ArmISA::OperatingMode

Enumerator
MODE_EL0T
MODE_EL1T
MODE_EL1H
MODE_EL2T
MODE_EL2H
MODE_EL3T
MODE_EL3H
MODE_USER
MODE_FIQ
MODE_IRQ
MODE_SVC
MODE_MON
MODE_ABORT
MODE_HYP
MODE_UNDEFINED
MODE_SYSTEM
MODE_MAXMODE

Definition at line 569 of file types.hh.

enum ArmISA::RoundMode

Enumerator
RND_ZERO
RND_DOWN
RND_UP
RND_NEAREST

Definition at line 555 of file types.hh.

enum ArmISA::VfpMicroMode

Enumerator
VfpNotAMicroop
VfpMicroop
VfpFirstMicroop
VfpLastMicroop

Definition at line 53 of file vfp.hh.

enum ArmISA::VfpRoundingMode

Enumerator
VfpRoundNearest
VfpRoundUpward
VfpRoundDown
VfpRoundZero
VfpRoundAway

Definition at line 102 of file vfp.hh.

Function Documentation

bool ArmISA::aarch64SysRegReadOnly

(

MiscRegIndex

miscReg

)

static void ArmISA::add128 ( uint64_t *  x0, uint64_t *  x1, uint64_t  a0, uint64_t  a1, uint64_t  b0, uint64_t  b1  )

inlinestatic

Definition at line 165 of file fplib.cc.

References MipsISA::a0.

Referenced by fp64_muladd().

void ArmISA::advancePC ( PCState &  pc, const StaticInstPtr &  inst  )

inline

Definition at line 280 of file utility.hh.

static bool ArmISA::badMode ( OperatingMode  mode )

inlinestatic

Definition at line 692 of file types.hh.

References MODE_ABORT, MODE_EL0T, MODE_EL1H, MODE_EL1T, MODE_EL2H, MODE_EL2T, MODE_EL3H, MODE_EL3T, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, and MODE_USER.

Referenced by ArmISA::ArmStaticInst::cpsrWriteByInstr(), and illegalExceptionReturn().

static bool ArmISA::badMode32 ( OperatingMode  mode )

inlinestatic

Definition at line 719 of file types.hh.

References MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, and MODE_USER.

Referenced by ArmISA::ArmStaticInst::getPSTATEFromPSR(), and illegalExceptionReturn().

static float ArmISA::bitsToFp ( uint64_t  bits, float  junk  )

inlinestatic

Definition at line 180 of file vfp.hh.

References bits(), MipsISA::fp, and X86ISA::val.

Referenced by ArmISA::FpOp::binaryOp(), ArmISA::FpOp::dbl(), fixDest(), fixDivDest(), fixFpDFpSDest(), fixFpSFpDDest(), flushToZero(), fpMulAdd(), fpRecipEstimate(), fprSqrtEstimate(), makeDouble(), ArmISA::FpOp::processNans(), ArmISA::FpOp::ternaryOp(), ArmISA::FpOp::unaryOp(), unsignedRecipEstimate(), unsignedRSqrtEstimate(), vcvtFpHFpD(), and vcvtFpHFpS().

static double ArmISA::bitsToFp ( uint64_t  bits, double  junk  )

inlinestatic

Definition at line 192 of file vfp.hh.

References bits(), MipsISA::fp, and X86ISA::val.

ArmISA::BitUnion32

(

CPSR

)

ArmISA::BitUnion32

(

HDCR

)

ArmISA::BitUnion32

(

FPEXC

)

ArmISA::BitUnion8

(

ITSTATE

)

ArmISA::BitUnion8

(

OperatingMode64

)

PCState ArmISA::buildRetPC ( const PCState &  curPC, const PCState &  callPC  )

inline

Definition at line 62 of file utility.hh.

bool ArmISA::canReadAArch64SysReg	(	MiscRegIndex	reg,
		SCR	scr,
		CPSR	cpsr,
		ThreadContext *	tc
	)

Definition at line 2096 of file miscregs.cc.

References EL0, EL1, EL2, EL3, ArmSystem::haveSecurity(), ArmSystem::highestEL(), MISCREG_HYP_RD, MISCREG_MON_NS0_RD, MISCREG_MON_NS1_RD, MISCREG_PRI_NS_RD, MISCREG_PRI_S_RD, MISCREG_RVBAR_EL1, MISCREG_RVBAR_EL2, MISCREG_SP_EL0, MISCREG_SPSEL, MISCREG_USR_NS_RD, MISCREG_USR_S_RD, miscRegInfo, opModeToEL(), panic, ThreadContext::readMiscReg(), and X86ISA::reg.

std::tuple<bool, bool> ArmISA::canReadCoprocReg	(	MiscRegIndex	reg,
		SCR	scr,
		CPSR	cpsr
	)

Definition at line 1973 of file miscregs.cc.

References MISCREG_BANKED, MISCREG_HYP_RD, MISCREG_MON_NS0_RD, MISCREG_MON_NS1_RD, MISCREG_PRI_NS_RD, MISCREG_PRI_S_RD, MISCREG_USR_NS_RD, MISCREG_USR_S_RD, miscRegInfo, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, and X86ISA::reg.

bool ArmISA::canWriteAArch64SysReg	(	MiscRegIndex	reg,
		SCR	scr,
		CPSR	cpsr,
		ThreadContext *	tc
	)

Definition at line 2134 of file miscregs.cc.

References el, EL0, EL1, EL2, EL3, FullSystem, ArmSystem::haveSecurity(), MISCREG_DAIF, MISCREG_DC_CIVAC_Xt, MISCREG_DC_CVAC_Xt, MISCREG_DC_ZVA_Xt, MISCREG_HYP_WR, MISCREG_MON_NS0_WR, MISCREG_MON_NS1_WR, MISCREG_PRI_NS_WR, MISCREG_PRI_S_WR, MISCREG_SCTLR_EL1, MISCREG_SP_EL0, MISCREG_SPSEL, MISCREG_USR_NS_WR, MISCREG_USR_S_WR, miscRegInfo, opModeToEL(), panic, ThreadContext::readMiscReg(), and X86ISA::reg.

std::tuple<bool, bool> ArmISA::canWriteCoprocReg	(	MiscRegIndex	reg,
		SCR	scr,
		CPSR	cpsr
	)

Check for permission to read coprocessor registers.

Checks whether an instruction at the current program mode has permissions to read the coprocessor registers. This function returns whether the check is undefined and if not whether the read access is permitted.

Parameters

the	misc reg indicating the coprocessor
the	SCR
the	CPSR

Returns

a tuple of booleans: can_read, undefined Check for permission to write coprocessor registers.

Checks whether an instruction at the current program mode has permissions to write the coprocessor registers. This function returns whether the check is undefined and if not whether the write access is permitted.

Parameters

the	misc reg indicating the coprocessor
the	SCR
the	CPSR

Returns

a tuple of booleans: can_write, undefined

Definition at line 2009 of file miscregs.cc.

References MISCREG_BANKED, MISCREG_HYP_WR, MISCREG_MON_NS0_WR, MISCREG_MON_NS1_WR, MISCREG_PRI_NS_WR, MISCREG_PRI_S_WR, MISCREG_USR_NS_WR, MISCREG_USR_S_WR, miscRegInfo, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, and X86ISA::reg.

ArmISA::clear

(

)

Referenced by ElasticTrace::addDepTraceRecord(), BlockBloomFilter::BlockBloomFilter(), BulkBloomFilter::BulkBloomFilter(), Histogram::clear(), TraceCPU::ElasticDataGen::completeMemAccess(), MuxingKvmGic::copyGicState(), TraceCPU::ElasticDataGen::execute(), H3BloomFilter::H3BloomFilter(), Histogram::Histogram(), LSB_CountingBloomFilter::LSB_CountingBloomFilter(), MultiBitSelBloomFilter::MultiBitSelBloomFilter(), MultiGrainBloomFilter::MultiGrainBloomFilter(), NonCountingBloomFilter::NonCountingBloomFilter(), and SymbolTable::unserialize().

static int ArmISA::cmp128 ( uint64_t  a0, uint64_t  a1, uint64_t  b0, uint64_t  b1  )

inlinestatic

Definition at line 181 of file fplib.cc.

Referenced by fp64_div(), fp64_muladd(), and fp64_sqrt().

static void ArmISA::copyMiscRegs ( ThreadContext *  src, ThreadContext *  dest  )

inlinestatic

Definition at line 113 of file utility.hh.

References panic.

void ArmISA::copyRegs	(	ThreadContext *	src,
		ThreadContext *	dest
	)

Definition at line 149 of file utility.cc.

References ThreadContext::getDTBPtr(), ThreadContext::getITBPtr(), i, MISCREG_CPSR, NumCCRegs, NumFloatRegs, NumIntRegs, NumMiscRegs, ThreadContext::pcState(), ThreadContext::readCCReg(), ThreadContext::readFloatRegFlat(), ThreadContext::readIntRegFlat(), ThreadContext::readMiscRegNoEffect(), ThreadContext::setCCReg(), ThreadContext::setFloatRegFlat(), ThreadContext::setIntRegFlat(), ThreadContext::setMiscReg(), and ThreadContext::setMiscRegNoEffect().

static ExceptionLevel ArmISA::currEL ( ThreadContext *  tc )

inlinestatic

Definition at line 154 of file utility.hh.

References MISCREG_CPSR, and ThreadContext::readMiscReg().

Referenced by ArmISA::TableWalker::processWalkWrapper(), and ArmISA::TableWalker::walk().

static OperatingMode ArmISA::currOpMode ( ThreadContext *  tc )

inlinestatic

Definition at line 147 of file utility.hh.

References MISCREG_CPSR, and ThreadContext::readMiscReg().

Referenced by ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), ELIs64(), isBigEndian64(), SPAlignmentCheckEnabled(), and ArmISA::TableWalker::walk().

MiscRegIndex ArmISA::decodeAArch64SysReg	(	unsigned	op0,
		unsigned	op1,
		unsigned	crn,
		unsigned	crm,
		unsigned	op2
	)

Definition at line 2178 of file miscregs.cc.

References MISCREG_ACTLR_EL1, MISCREG_ACTLR_EL2, MISCREG_ACTLR_EL3, MISCREG_AFSR0_EL1, MISCREG_AFSR0_EL2, MISCREG_AFSR0_EL3, MISCREG_AFSR1_EL1, MISCREG_AFSR1_EL2, MISCREG_AFSR1_EL3, MISCREG_AIDR_EL1, MISCREG_AMAIR_EL1, MISCREG_AMAIR_EL2, MISCREG_AMAIR_EL3, MISCREG_AT_S12E0R_Xt, MISCREG_AT_S12E0W_Xt, MISCREG_AT_S12E1R_Xt, MISCREG_AT_S12E1W_Xt, MISCREG_AT_S1E0R_Xt, MISCREG_AT_S1E0W_Xt, MISCREG_AT_S1E1R_Xt, MISCREG_AT_S1E1W_Xt, MISCREG_AT_S1E2R_Xt, MISCREG_AT_S1E2W_Xt, MISCREG_AT_S1E3R_Xt, MISCREG_AT_S1E3W_Xt, MISCREG_CBAR_EL1, MISCREG_CCSIDR_EL1, MISCREG_CLIDR_EL1, MISCREG_CNTFRQ_EL0, MISCREG_CNTHCTL_EL2, MISCREG_CNTHP_CTL_EL2, MISCREG_CNTHP_CVAL_EL2, MISCREG_CNTHP_TVAL_EL2, MISCREG_CNTKCTL_EL1, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_CVAL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTPCT_EL0, MISCREG_CNTPS_CTL_EL1, MISCREG_CNTPS_CVAL_EL1, MISCREG_CNTPS_TVAL_EL1, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_CVAL_EL0, MISCREG_CNTV_TVAL_EL0, MISCREG_CNTVCT_EL0, MISCREG_CNTVOFF_EL2, MISCREG_CONTEXTIDR_EL1, MISCREG_CONTEXTIDR_EL2, MISCREG_CPACR_EL1, MISCREG_CPTR_EL2, MISCREG_CPTR_EL3, MISCREG_CPUACTLR_EL1, MISCREG_CPUECTLR_EL1, MISCREG_CPUMERRSR_EL1, MISCREG_CSSELR_EL1, MISCREG_CTR_EL0, MISCREG_CURRENTEL, MISCREG_DACR32_EL2, MISCREG_DAIF, MISCREG_DBGAUTHSTATUS_EL1, MISCREG_DBGBCR0_EL1, MISCREG_DBGBCR1_EL1, MISCREG_DBGBCR2_EL1, MISCREG_DBGBCR3_EL1, MISCREG_DBGBCR4_EL1, MISCREG_DBGBCR5_EL1, MISCREG_DBGBVR0_EL1, MISCREG_DBGBVR1_EL1, MISCREG_DBGBVR2_EL1, MISCREG_DBGBVR3_EL1, MISCREG_DBGBVR4_EL1, MISCREG_DBGBVR5_EL1, MISCREG_DBGCLAIMCLR_EL1, MISCREG_DBGCLAIMSET_EL1, MISCREG_DBGPRCR_EL1, MISCREG_DBGVCR32_EL2, MISCREG_DBGWCR0_EL1, MISCREG_DBGWCR1_EL1, MISCREG_DBGWCR2_EL1, MISCREG_DBGWCR3_EL1, MISCREG_DBGWVR0_EL1, MISCREG_DBGWVR1_EL1, MISCREG_DBGWVR2_EL1, MISCREG_DBGWVR3_EL1, MISCREG_DC_CISW_Xt, MISCREG_DC_CIVAC_Xt, MISCREG_DC_CSW_Xt, MISCREG_DC_CVAC_Xt, MISCREG_DC_CVAU_Xt, MISCREG_DC_ISW_Xt, MISCREG_DC_IVAC_Xt, MISCREG_DC_ZVA_Xt, MISCREG_DCZID_EL0, MISCREG_DL1DATA0_EL1, MISCREG_DL1DATA1_EL1, MISCREG_DL1DATA2_EL1, MISCREG_DL1DATA3_EL1, MISCREG_DL1DATA4_EL1, MISCREG_DLR_EL0, MISCREG_DSPSR_EL0, MISCREG_ELR_EL1, MISCREG_ELR_EL2, MISCREG_ELR_EL3, MISCREG_ESR_EL1, MISCREG_ESR_EL2, MISCREG_ESR_EL3, MISCREG_FAR_EL1, MISCREG_FAR_EL2, MISCREG_FAR_EL3, MISCREG_FPCR, MISCREG_FPEXC32_EL2, MISCREG_FPSR, MISCREG_HACR_EL2, MISCREG_HCR_EL2, MISCREG_HPFAR_EL2, MISCREG_HSTR_EL2, MISCREG_IC_IALLU, MISCREG_IC_IALLUIS, MISCREG_IC_IVAU_Xt, MISCREG_ID_AA64AFR0_EL1, MISCREG_ID_AA64AFR1_EL1, MISCREG_ID_AA64DFR0_EL1, MISCREG_ID_AA64DFR1_EL1, MISCREG_ID_AA64ISAR0_EL1, MISCREG_ID_AA64ISAR1_EL1, MISCREG_ID_AA64MMFR0_EL1, MISCREG_ID_AA64MMFR1_EL1, MISCREG_ID_AA64PFR0_EL1, MISCREG_ID_AA64PFR1_EL1, MISCREG_ID_AFR0_EL1, MISCREG_ID_DFR0_EL1, MISCREG_ID_ISAR0_EL1, MISCREG_ID_ISAR1_EL1, MISCREG_ID_ISAR2_EL1, MISCREG_ID_ISAR3_EL1, MISCREG_ID_ISAR4_EL1, MISCREG_ID_ISAR5_EL1, MISCREG_ID_MMFR0_EL1, MISCREG_ID_MMFR1_EL1, MISCREG_ID_MMFR2_EL1, MISCREG_ID_MMFR3_EL1, MISCREG_ID_PFR0_EL1, MISCREG_ID_PFR1_EL1, MISCREG_IFSR32_EL2, MISCREG_IL1DATA0_EL1, MISCREG_IL1DATA1_EL1, MISCREG_IL1DATA2_EL1, MISCREG_IL1DATA3_EL1, MISCREG_ISR_EL1, MISCREG_L2ACTLR_EL1, MISCREG_L2CTLR_EL1, MISCREG_L2ECTLR_EL1, MISCREG_L2MERRSR_EL1, MISCREG_MAIR_EL1, MISCREG_MAIR_EL2, MISCREG_MAIR_EL3, MISCREG_MDCCINT_EL1, MISCREG_MDCCSR_EL0, MISCREG_MDCR_EL2, MISCREG_MDCR_EL3, MISCREG_MDDTR_EL0, MISCREG_MDDTRRX_EL0, MISCREG_MDRAR_EL1, MISCREG_MDSCR_EL1, MISCREG_MIDR_EL1, MISCREG_MPIDR_EL1, MISCREG_MVFR0_EL1, MISCREG_MVFR1_EL1, MISCREG_MVFR2_EL1, MISCREG_NZCV, MISCREG_OSDLR_EL1, MISCREG_OSDTRRX_EL1, MISCREG_OSDTRTX_EL1, MISCREG_OSECCR_EL1, MISCREG_OSLAR_EL1, MISCREG_OSLSR_EL1, MISCREG_PAR_EL1, MISCREG_PMCCFILTR_EL0, MISCREG_PMCCNTR_EL0, MISCREG_PMCEID0_EL0, MISCREG_PMCEID1_EL0, MISCREG_PMCNTENCLR_EL0, MISCREG_PMCNTENSET_EL0, MISCREG_PMCR_EL0, MISCREG_PMEVCNTR0_EL0, MISCREG_PMEVCNTR1_EL0, MISCREG_PMEVCNTR2_EL0, MISCREG_PMEVCNTR3_EL0, MISCREG_PMEVCNTR4_EL0, MISCREG_PMEVCNTR5_EL0, MISCREG_PMEVTYPER0_EL0, MISCREG_PMEVTYPER1_EL0, MISCREG_PMEVTYPER2_EL0, MISCREG_PMEVTYPER3_EL0, MISCREG_PMEVTYPER4_EL0, MISCREG_PMEVTYPER5_EL0, MISCREG_PMINTENCLR_EL1, MISCREG_PMINTENSET_EL1, MISCREG_PMOVSCLR_EL0, MISCREG_PMOVSSET_EL0, MISCREG_PMSELR_EL0, MISCREG_PMSWINC_EL0, MISCREG_PMUSERENR_EL0, MISCREG_PMXEVCNTR_EL0, MISCREG_PMXEVTYPER_EL0, MISCREG_RAZ, MISCREG_REVIDR_EL1, MISCREG_RMR_EL3, MISCREG_RVBAR_EL1, MISCREG_RVBAR_EL2, MISCREG_RVBAR_EL3, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, MISCREG_SDER32_EL3, MISCREG_SP_EL0, MISCREG_SP_EL1, MISCREG_SP_EL2, MISCREG_SPSEL, MISCREG_SPSR_ABT_AA64, MISCREG_SPSR_EL1, MISCREG_SPSR_EL2, MISCREG_SPSR_EL3, MISCREG_SPSR_FIQ_AA64, MISCREG_SPSR_IRQ_AA64, MISCREG_SPSR_UND_AA64, MISCREG_TCR_EL1, MISCREG_TCR_EL2, MISCREG_TCR_EL3, MISCREG_TEECR32_EL1, MISCREG_TEEHBR32_EL1, MISCREG_TLBI_ALLE1, MISCREG_TLBI_ALLE1IS, MISCREG_TLBI_ALLE2, MISCREG_TLBI_ALLE2IS, MISCREG_TLBI_ALLE3, MISCREG_TLBI_ALLE3IS, MISCREG_TLBI_ASIDE1_Xt, MISCREG_TLBI_ASIDE1IS_Xt, MISCREG_TLBI_IPAS2E1_Xt, MISCREG_TLBI_IPAS2E1IS_Xt, MISCREG_TLBI_IPAS2LE1_Xt, MISCREG_TLBI_IPAS2LE1IS_Xt, MISCREG_TLBI_VAAE1_Xt, MISCREG_TLBI_VAAE1IS_Xt, MISCREG_TLBI_VAALE1_Xt, MISCREG_TLBI_VAALE1IS_Xt, MISCREG_TLBI_VAE1_Xt, MISCREG_TLBI_VAE1IS_Xt, MISCREG_TLBI_VAE2_Xt, MISCREG_TLBI_VAE2IS_Xt, MISCREG_TLBI_VAE3_Xt, MISCREG_TLBI_VAE3IS_Xt, MISCREG_TLBI_VALE1_Xt, MISCREG_TLBI_VALE1IS_Xt, MISCREG_TLBI_VALE2_Xt, MISCREG_TLBI_VALE2IS_Xt, MISCREG_TLBI_VALE3_Xt, MISCREG_TLBI_VALE3IS_Xt, MISCREG_TLBI_VMALLE1, MISCREG_TLBI_VMALLE1IS, MISCREG_TLBI_VMALLS12E1, MISCREG_TLBI_VMALLS12E1IS, MISCREG_TPIDR_EL0, MISCREG_TPIDR_EL1, MISCREG_TPIDR_EL2, MISCREG_TPIDR_EL3, MISCREG_TPIDRRO_EL0, MISCREG_TTBR0_EL1, MISCREG_TTBR0_EL2, MISCREG_TTBR0_EL3, MISCREG_TTBR1_EL1, MISCREG_UNKNOWN, MISCREG_VBAR_EL1, MISCREG_VBAR_EL2, MISCREG_VBAR_EL3, MISCREG_VMPIDR_EL2, MISCREG_VPIDR_EL2, MISCREG_VTCR_EL2, and MISCREG_VTTBR_EL2.

Referenced by ArmV8KvmCPU::dump(), and ArmV8KvmCPU::getSysRegMap().

MiscRegIndex ArmISA::decodeCP14Reg	(	unsigned	crn,
		unsigned	opc1,
		unsigned	crm,
		unsigned	opc2
	)

Definition at line 55 of file miscregs.cc.

References MISCREG_CP14_UNIMPL, MISCREG_DBGDIDR, MISCREG_DBGDSCRint, MISCREG_JIDR, MISCREG_JMCR, MISCREG_JOSCR, MISCREG_TEEHBR, and warn.

Referenced by ArmKvmCPU::decodeCoProcReg().

MiscRegIndex ArmISA::decodeCP15Reg	(	unsigned	crn,
		unsigned	opc1,
		unsigned	crm,
		unsigned	opc2
	)

Definition at line 1359 of file miscregs.cc.

References MISCREG_ACTLR, MISCREG_ADFSR, MISCREG_AIDR, MISCREG_AIFSR, MISCREG_AMAIR0, MISCREG_AMAIR1, MISCREG_ATS12NSOPR, MISCREG_ATS12NSOPW, MISCREG_ATS12NSOUR, MISCREG_ATS12NSOUW, MISCREG_ATS1CPR, MISCREG_ATS1CPW, MISCREG_ATS1CUR, MISCREG_ATS1CUW, MISCREG_ATS1HR, MISCREG_ATS1HW, MISCREG_BPIALL, MISCREG_BPIALLIS, MISCREG_BPIMVA, MISCREG_CCSIDR, MISCREG_CLIDR, MISCREG_CNTFRQ, MISCREG_CNTHCTL, MISCREG_CNTHP_CTL, MISCREG_CNTHP_TVAL, MISCREG_CNTKCTL, MISCREG_CNTP_CTL, MISCREG_CNTP_TVAL, MISCREG_CNTV_CTL, MISCREG_CNTV_TVAL, MISCREG_CONTEXTIDR, MISCREG_CP15_UNIMPL, MISCREG_CP15DMB, MISCREG_CP15DSB, MISCREG_CP15ISB, MISCREG_CPACR, MISCREG_CSSELR, MISCREG_CTR, MISCREG_DACR, MISCREG_DCCIMVAC, MISCREG_DCCISW, MISCREG_DCCMVAC, MISCREG_DCCMVAU, MISCREG_DCCSW, MISCREG_DCIMVAC, MISCREG_DCISW, MISCREG_DFAR, MISCREG_DFSR, MISCREG_DTLBIALL, MISCREG_DTLBIASID, MISCREG_DTLBIMVA, MISCREG_FCSEIDR, MISCREG_HACR, MISCREG_HACTLR, MISCREG_HADFSR, MISCREG_HAIFSR, MISCREG_HAMAIR0, MISCREG_HAMAIR1, MISCREG_HCPTR, MISCREG_HCR, MISCREG_HDCR, MISCREG_HDFAR, MISCREG_HIFAR, MISCREG_HMAIR0, MISCREG_HMAIR1, MISCREG_HPFAR, MISCREG_HSCTLR, MISCREG_HSR, MISCREG_HSTR, MISCREG_HTCR, MISCREG_HTPIDR, MISCREG_HVBAR, MISCREG_ICIALLU, MISCREG_ICIALLUIS, MISCREG_ICIMVAU, MISCREG_ID_AFR0, MISCREG_ID_DFR0, MISCREG_ID_ISAR0, MISCREG_ID_ISAR1, MISCREG_ID_ISAR2, MISCREG_ID_ISAR3, MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, MISCREG_ID_MMFR0, MISCREG_ID_MMFR1, MISCREG_ID_MMFR2, MISCREG_ID_MMFR3, MISCREG_ID_PFR0, MISCREG_ID_PFR1, MISCREG_IFAR, MISCREG_IFSR, MISCREG_ISR, MISCREG_ITLBIALL, MISCREG_ITLBIASID, MISCREG_ITLBIMVA, MISCREG_L2CTLR, MISCREG_L2ECTLR, MISCREG_MIDR, MISCREG_MPIDR, MISCREG_MVBAR, MISCREG_NMRR_MAIR1, MISCREG_NOP, MISCREG_NSACR, MISCREG_PAR, MISCREG_PMCCNTR, MISCREG_PMCEID0, MISCREG_PMCEID1, MISCREG_PMCNTENCLR, MISCREG_PMCNTENSET, MISCREG_PMCR, MISCREG_PMINTENCLR, MISCREG_PMINTENSET, MISCREG_PMOVSR, MISCREG_PMOVSSET, MISCREG_PMSELR, MISCREG_PMSWINC, MISCREG_PMUSERENR, MISCREG_PMXEVCNTR, MISCREG_PMXEVTYPER_PMCCFILTR, MISCREG_PRRR_MAIR0, MISCREG_RAZ, MISCREG_REVIDR, MISCREG_SCR, MISCREG_SCTLR, MISCREG_SDER, MISCREG_TCMTR, MISCREG_TLBIALL, MISCREG_TLBIALLH, MISCREG_TLBIALLHIS, MISCREG_TLBIALLIS, MISCREG_TLBIALLNSNH, MISCREG_TLBIALLNSNHIS, MISCREG_TLBIASID, MISCREG_TLBIASIDIS, MISCREG_TLBIMVA, MISCREG_TLBIMVAA, MISCREG_TLBIMVAAIS, MISCREG_TLBIMVAH, MISCREG_TLBIMVAHIS, MISCREG_TLBIMVAIS, MISCREG_TLBTR, MISCREG_TPIDRPRW, MISCREG_TPIDRURO, MISCREG_TPIDRURW, MISCREG_TTBCR, MISCREG_TTBR0, MISCREG_TTBR1, MISCREG_VBAR, MISCREG_VMPIDR, MISCREG_VPIDR, and MISCREG_VTCR.

Referenced by ArmKvmCPU::decodeCoProcReg().

MiscRegIndex ArmISA::decodeCP15Reg64	(	unsigned	crm,
		unsigned	opc1
	)

Definition at line 1926 of file miscregs.cc.

References MISCREG_CNTHP_CVAL, MISCREG_CNTP_CVAL, MISCREG_CNTPCT, MISCREG_CNTV_CVAL, MISCREG_CNTVCT, MISCREG_CNTVOFF, MISCREG_CP15_UNIMPL, MISCREG_CPUMERRSR, MISCREG_HTTBR, MISCREG_L2MERRSR, MISCREG_PAR, MISCREG_TTBR0, MISCREG_TTBR1, and MISCREG_VTTBR.

static int ArmISA::decodeMrsMsrBankedIntRegIndex ( uint8_t  sysM, bool  r  )

inlinestatic

Definition at line 304 of file utility.hh.

References decodeMrsMsrBankedReg(), and INTREG_DUMMY.

bool ArmISA::decodeMrsMsrBankedReg	(	uint8_t	sysM,
		bool	r,
		bool &	isIntReg,
		int &	regIdx,
		CPSR	cpsr,
		SCR	scr,
		NSACR	nsacr,
		bool	checkSecurity
	)

Definition at line 756 of file utility.cc.

References bits(), intRegInMode(), MISCREG_ELR_HYP, MISCREG_SPSR_ABT, MISCREG_SPSR_FIQ, MISCREG_SPSR_HYP, MISCREG_SPSR_IRQ, MISCREG_SPSR_MON, MISCREG_SPSR_SVC, MISCREG_SPSR_UND, mode, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, panic, and MipsISA::r.

Referenced by decodeMrsMsrBankedIntRegIndex().

int ArmISA::decodePhysAddrRange64

(

uint8_t

pa_enc

)

Returns the n.

of PA bits corresponding to the specified encoding.

Definition at line 893 of file utility.cc.

References panic.

bool ArmISA::ELIs64	(	ThreadContext *	tc,
		ExceptionLevel	el
	)

Definition at line 228 of file utility.cc.

References currOpMode(), EL0, EL1, EL2, ArmSystem::haveSecurity(), ArmSystem::haveVirtualization(), ArmSystem::highestEL(), ArmSystem::highestELIs64(), MISCREG_HCR_EL2, MISCREG_SCR_EL3, panic, and ThreadContext::readMiscReg().

Referenced by ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), ArmISA::ArmFault::invoke(), ArmISA::TLB::updateMiscReg(), and ArmISA::TableWalker::walk().

uint8_t ArmISA::encodePhysAddrRange64

(

int

pa_size

)

Returns the encoding corresponding to the specified n.

of PA bits.

Definition at line 916 of file utility.cc.

References panic.

Referenced by ArmISA::ISA::clear64().

ArmISA::EndBitUnion

(

ITSTATE

)

ArmISA::EndBitUnion

(

ExtMachInst

)

Definition at line 208 of file types.hh.

References aarch64, bits(), DPRINTF, itstate, mask, operator!=(), X86ISA::operator==(), pc, replaceBits(), s, X86ISA::serialize(), SERIALIZE_SCALAR, X86ISA::size(), thumb, X86ISA::unserialize(), UNSERIALIZE_SCALAR, and X86ISA::val.

ArmISA::EndBitUnion

(

OperatingMode64

)

Definition at line 641 of file types.hh.

ArmISA::EndBitUnion ( CPSR  ) const

pure virtual

ArmISA::EndBitUnion

(

HDCR

)

ArmISA::EndBitUnion

(

HCPTR

)

ArmISA::EndBitUnion

(

HSTR

)

ArmISA::EndBitUnion

(

HCR

)

ArmISA::EndBitUnion

(

NSACR

)

ArmISA::EndBitUnion

(

SCR

)

ArmISA::EndBitUnion

(

SCTLR

)

ArmISA::EndBitUnion

(

CPACR

)

ArmISA::EndBitUnion

(

FSR

)

ArmISA::EndBitUnion ( FPSCR  ) const

pure virtual

ArmISA::EndBitUnion

(

FPEXC

)

ArmISA::EndBitUnion

(

MVFR0

)

ArmISA::EndBitUnion

(

MVFR1

)

ArmISA::EndBitUnion

(

TTBCR

)

ArmISA::EndBitUnion

(

TCR

)

ArmISA::EndBitUnion

(

HTCR

)

ArmISA::EndBitUnion

(

VTCR_t

)

ArmISA::EndBitUnion

(

PRRR

)

ArmISA::EndBitUnion

(

NMRR

)

ArmISA::EndBitUnion

(

CONTEXTIDR

)

ArmISA::EndBitUnion

(

L2CTLR

)

ArmISA::EndBitUnion

(

CTR

)

ArmISA::EndBitUnion

(

PMSELR

)

ArmISA::EndBitUnion

(

PAR

)

ArmISA::EndBitUnion

(

ESR

)

ArmISA::EndSubBitUnion

(

puswl

)

void ArmISA::finishVfp	(	FPSCR &	fpscr,
		VfpSavedState	state,
		bool	flush,
		FPSCR	mask
	)

Definition at line 195 of file vfp.cc.

References FeAllExceptions, FeDivByZero, FeInexact, FeInvalid, FeOverflow, and FeUnderflow.

Referenced by ArmISA::FpOp::binaryOp(), ArmISA::FpOp::ternaryOp(), and ArmISA::FpOp::unaryOp().

template<class fpType >

fpType ArmISA::fixDest	(	FPSCR	fpscr,
		fpType	val,
		fpType	op1
	)

template<class fpType >

fpType ArmISA::fixDest	(	bool	flush,
		bool	defaultNan,
		fpType	val,
		fpType	op1
	)

Definition at line 221 of file vfp.cc.

References bitsToFp(), FeInexact, FeUnderflow, HsailISA::fpclassify(), fpToBits(), ULL, and X86ISA::val.

Referenced by fixDivDest(), fixFpDFpSDest(), and fixFpSFpDDest().

template<class fpType >

fpType ArmISA::fixDest	(	FPSCR	fpscr,
		fpType	val,
		fpType	op1,
		fpType	op2
	)

template<class fpType >

fpType ArmISA::fixDest	(	bool	flush,
		bool	defaultNan,
		fpType	val,
		fpType	op1,
		fpType	op2
	)

Definition at line 251 of file vfp.cc.

References bitsToFp(), FeInexact, FeUnderflow, HsailISA::fpclassify(), fpToBits(), ULL, and X86ISA::val.

template double ArmISA::fixDest< double >	(	bool	flush,
		bool	defaultNan,
		double	val,
		double	op1
	)

template double ArmISA::fixDest< double >	(	bool	flush,
		bool	defaultNan,
		double	val,
		double	op1,
		double	op2
	)

template float ArmISA::fixDest< float >	(	bool	flush,
		bool	defaultNan,
		float	val,
		float	op1
	)

template float ArmISA::fixDest< float >	(	bool	flush,
		bool	defaultNan,
		float	val,
		float	op1,
		float	op2
	)

template<class fpType >

fpType ArmISA::fixDivDest	(	FPSCR	fpscr,
		fpType	val,
		fpType	op1,
		fpType	op2
	)

template<class fpType >

fpType ArmISA::fixDivDest	(	bool	flush,
		bool	defaultNan,
		fpType	val,
		fpType	op1,
		fpType	op2
	)

Definition at line 292 of file vfp.cc.

References bitsToFp(), FeInexact, FeRoundZero, FeUnderflow, fixDest(), flushToZero, and ULL.

Referenced by vfpSFixedToFpD(), vfpSFixedToFpS(), vfpUFixedToFpD(), and vfpUFixedToFpS().

template double ArmISA::fixDivDest< double >	(	bool	flush,
		bool	defaultNan,
		double	val,
		double	op1,
		double	op2
	)

template float ArmISA::fixDivDest< float >	(	bool	flush,
		bool	defaultNan,
		float	val,
		float	op1,
		float	op2
	)

float ArmISA::fixFpDFpSDest	(	FPSCR	fpscr,
		double	val
	)

Definition at line 327 of file vfp.cc.

References bits(), bitsToFp(), FeInexact, FeRoundZero, FeUnderflow, fixDest(), flushToZero, fpToBits(), mask, and X86ISA::val.

double ArmISA::fixFpSFpDDest	(	FPSCR	fpscr,
		float	val
	)

Definition at line 363 of file vfp.cc.

References bits(), bitsToFp(), FeInexact, FeRoundZero, FeUnderflow, fixDest(), flushToZero, fpToBits(), mask, ULL, and X86ISA::val.

static int ArmISA::flattenIntRegModeIndex ( int  reg )

inlinestatic

Definition at line 471 of file intregs.hh.

References curTick(), INTREG_ABT(), INTREG_FIQ(), INTREG_HYP(), INTREG_IRQ(), INTREG_MON(), INTREG_SVC(), INTREG_UND(), INTREG_USR(), intRegsPerMode, mode, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, and panic.

Referenced by ArmISA::ISA::flattenIntIndex().

int ArmISA::flattenMiscRegNsBanked	(	MiscRegIndex	reg,
		ThreadContext *	tc
	)

Definition at line 2045 of file miscregs.cc.

References MISCREG_SCR, and ThreadContext::readMiscReg().

Referenced by ArmISA::TableWalker::memAttrs(), ArmISA::TableWalker::memAttrsLPAE(), ArmISA::TableWalker::processWalk(), ArmISA::TableWalker::processWalkLPAE(), ArmISA::TLB::updateMiscReg(), and ArmISA::TableWalker::walk().

int ArmISA::flattenMiscRegNsBanked	(	MiscRegIndex	reg,
		ThreadContext *	tc,
		bool	ns
	)

Definition at line 2052 of file miscregs.cc.

References ArmSystem::haveSecurity(), ArmSystem::highestELIs64(), MISCREG_BANKED, miscRegInfo, ns, and X86ISA::reg.

template<class fpType >

static bool ArmISA::flushToZero ( fpType &  op )

inlinestatic

Definition at line 118 of file vfp.hh.

References bitsToFp(), HsailISA::fpclassify(), fpToBits(), and ULL.

template<class fpType >

static bool ArmISA::flushToZero ( fpType &  op1, fpType &  op2  )

inlinestatic

Definition at line 131 of file vfp.hh.

References flushToZero.

ArmISA::for

(

auto sw:MiscRegSwitch

)

Fill in the miscReg translation table.

Definition at line 244 of file isa.cc.

References sw.

static void ArmISA::fp128_normalise ( uint64_t *  mnt0, uint64_t *  mnt1, int *  exp  )

inlinestatic

Definition at line 241 of file fplib.cc.

References shift.

Referenced by fp64_mul(), and fp64_muladd().

static uint16_t ArmISA::fp16_defaultNaN ( )

inlinestatic

Definition at line 342 of file fplib.cc.

References fp16_pack().

Referenced by fplibConvert().

static uint16_t ArmISA::fp16_FPConvertNaN_32 ( uint32_t  op )

static

Definition at line 1712 of file fplib.cc.

References fp16_pack().

Referenced by fplibConvert().

static uint16_t ArmISA::fp16_FPConvertNaN_64 ( uint64_t  op )

static

Definition at line 1718 of file fplib.cc.

References fp16_pack().

Referenced by fplibConvert().

static uint16_t ArmISA::fp16_infinity ( int  sgn )

inlinestatic

Definition at line 324 of file fplib.cc.

References fp16_pack().

Referenced by fp16_round_(), and fplibConvert().

static uint16_t ArmISA::fp16_max_normal ( int  sgn )

inlinestatic

Definition at line 306 of file fplib.cc.

References fp16_pack().

Referenced by fp16_round_().

static uint16_t ArmISA::fp16_normalise ( uint16_t  mnt, int *  exp  )

inlinestatic

Definition at line 187 of file fplib.cc.

References shift.

Referenced by fplibConvert().

static uint16_t ArmISA::fp16_pack ( uint16_t  sgn, uint16_t  exp, uint16_t  mnt  )

inlinestatic

Definition at line 270 of file fplib.cc.

Referenced by fp16_defaultNaN(), fp16_FPConvertNaN_32(), fp16_FPConvertNaN_64(), fp16_infinity(), fp16_max_normal(), fp16_round_(), and fp16_zero().

static uint16_t ArmISA::fp16_round_ ( int  sgn, int  exp, uint16_t  mnt, int  rm, int  mode, int *  flags  )

static

Definition at line 541 of file fplib.cc.

References fp16_infinity(), fp16_max_normal(), fp16_pack(), FPLIB_AHP, FPLIB_IOC, FPLIB_IXC, FPLIB_OFC, FPLIB_RM, FPLIB_RN, FPLIB_RP, FPLIB_UFC, FPRounding_ODD, FPRounding_TIEAWAY, lsl16(), and lsr16().

Referenced by fplibConvert().

static void ArmISA::fp16_unpack ( int *  sgn, int *  exp, uint16_t *  mnt, uint16_t  x, int  mode, int *  flags  )

inlinestatic

Definition at line 360 of file fplib.cc.

Referenced by fplibConvert().

static uint16_t ArmISA::fp16_zero ( int  sgn )

inlinestatic

Definition at line 288 of file fplib.cc.

References fp16_pack().

Referenced by fplibConvert().

static uint32_t ArmISA::fp32_add ( uint32_t  a, uint32_t  b, int  neg, int  mode, int *  flags  )

static

Definition at line 904 of file fplib.cc.

References fp32_defaultNaN(), fp32_infinity(), fp32_normalise(), fp32_process_NaNs(), fp32_round(), fp32_unpack(), fp32_zero(), FPLIB_IOC, lsl32(), lsr32(), and X86ISA::x.

Referenced by fplibAdd(), and fplibSub().

static int ArmISA::fp32_compare_eq ( uint32_t  a, uint32_t  b, int  mode, int *  flags  )

static

Definition at line 766 of file fplib.cc.

References fp32_unpack(), and FPLIB_IOC.

Referenced by fplibCompareEQ().

static int ArmISA::fp32_compare_ge ( uint32_t  a, uint32_t  b, int  mode, int *  flags  )

static

Definition at line 785 of file fplib.cc.

References fp32_unpack(), and FPLIB_IOC.

Referenced by fplibCompareGE().

static int ArmISA::fp32_compare_gt ( uint32_t  a, uint32_t  b, int  mode, int *  flags  )

static

Definition at line 810 of file fplib.cc.

References fp32_unpack(), and FPLIB_IOC.

Referenced by fplibCompareGT().

static uint32_t ArmISA::fp32_cvtf ( uint64_t  a, int  fbits, int  u, int  mode, int *  flags  )

static

Definition at line 3016 of file fplib.cc.

References a, fp32_round(), fp32_zero(), and fp64_normalise().

Referenced by fplibFixedToFP().

static uint32_t ArmISA::fp32_defaultNaN ( )

inlinestatic

Definition at line 348 of file fplib.cc.

References fp32_pack().

Referenced by fp32_add(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_process_NaN(), fp32_sqrt(), fplibConvert(), and fplibRSqrtEstimate().

static uint32_t ArmISA::fp32_div ( uint32_t  a, uint32_t  b, int  mode, int *  flags  )

static

Definition at line 1269 of file fplib.cc.

References fp32_defaultNaN(), fp32_infinity(), fp32_normalise(), fp32_process_NaNs(), fp32_round(), fp32_unpack(), fp32_zero(), fp64_normalise(), FPLIB_DZC, FPLIB_IOC, and X86ISA::x.

Referenced by fplibDiv().

static uint32_t ArmISA::fp32_FPConvertNaN_16 ( uint16_t  op )

static

Definition at line 1724 of file fplib.cc.

References fp32_pack().

Referenced by fplibConvert().

static uint32_t ArmISA::fp32_FPConvertNaN_64 ( uint64_t  op )

static

Definition at line 1730 of file fplib.cc.

References fp32_pack().

Referenced by fplibConvert().

static uint32_t ArmISA::fp32_FPOnePointFive ( int  sgn )

static

Definition at line 1748 of file fplib.cc.

References fp32_pack().

Referenced by fplibRSqrtStepFused().

static uint32_t ArmISA::fp32_FPThree ( int  sgn )

static

Definition at line 1760 of file fplib.cc.

References fp32_pack().

Referenced by fplibRSqrtStepFused().

static uint32_t ArmISA::fp32_FPTwo ( int  sgn )

static

Definition at line 1772 of file fplib.cc.

References fp32_pack().

Referenced by fplibMulX(), and fplibRecipStepFused().

static uint32_t ArmISA::fp32_infinity ( int  sgn )

inlinestatic

Definition at line 330 of file fplib.cc.

References fp32_pack().

Referenced by fp32_add(), fp32_div(), fp32_minmaxnum(), fp32_mul(), fp32_muladd(), fp32_round_(), fp32_sqrt(), fplibConvert(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibRSqrtStepFused().

static uint32_t ArmISA::fp32_max_normal ( int  sgn )

inlinestatic

Definition at line 312 of file fplib.cc.

References fp32_pack().

Referenced by fp32_round_(), and fplibRecipEstimate().

static void ArmISA::fp32_minmaxnum ( uint32_t *  op1, uint32_t *  op2, int  sgn  )

static

Definition at line 2073 of file fplib.cc.

References fp32_infinity().

Referenced by fplibMaxNum(), and fplibMinNum().

static uint32_t ArmISA::fp32_mul ( uint32_t  a, uint32_t  b, int  mode, int *  flags  )

static

Definition at line 1022 of file fplib.cc.

References fp32_defaultNaN(), fp32_infinity(), fp32_process_NaNs(), fp32_round(), fp32_unpack(), fp32_zero(), fp64_normalise(), FPLIB_IOC, lsl64(), lsr64(), and X86ISA::x.

Referenced by fplibMul(), and fplibMulX().

static uint32_t ArmISA::fp32_muladd ( uint32_t  a, uint32_t  b, uint32_t  c, int  scale, int  mode, int *  flags  )

static

Definition at line 1094 of file fplib.cc.

References fp32_defaultNaN(), fp32_infinity(), fp32_process_NaNs3(), fp32_round(), fp32_unpack(), fp32_zero(), fp64_normalise(), FPLIB_IOC, lsl64(), lsr64(), and X86ISA::x.

Referenced by fplibMulAdd(), fplibRecipStepFused(), and fplibRSqrtStepFused().

static uint32_t ArmISA::fp32_normalise ( uint32_t  mnt, int *  exp  )

inlinestatic

Definition at line 205 of file fplib.cc.

References shift.

Referenced by fp32_add(), fp32_div(), fp32_sqrt(), fplibConvert(), fplibRecipEstimate(), fplibRoundInt(), and fplibRSqrtEstimate().

static uint32_t ArmISA::fp32_pack ( uint32_t  sgn, uint32_t  exp, uint32_t  mnt  )

inlinestatic

Definition at line 276 of file fplib.cc.

Referenced by fp32_defaultNaN(), fp32_FPConvertNaN_16(), fp32_FPConvertNaN_64(), fp32_FPOnePointFive(), fp32_FPThree(), fp32_FPTwo(), fp32_infinity(), fp32_max_normal(), fp32_repack(), fp32_round_(), fp32_zero(), fplibConvert(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

static uint32_t ArmISA::fp32_process_NaN ( uint32_t  a, int  mode, int *  flags  )

inlinestatic

Definition at line 417 of file fplib.cc.

References a, fp32_defaultNaN(), FPLIB_DN, and FPLIB_IOC.

Referenced by fp32_process_NaNs(), fp32_process_NaNs3(), fp32_sqrt(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

static uint32_t ArmISA::fp32_process_NaNs ( uint32_t  a, uint32_t  b, int  mode, int *  flags  )

static

Definition at line 437 of file fplib.cc.

References fp32_process_NaN().

Referenced by fp32_add(), fp32_div(), fp32_mul(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipStepFused(), and fplibRSqrtStepFused().

static uint32_t ArmISA::fp32_process_NaNs3 ( uint32_t  a, uint32_t  b, uint32_t  c, int  mode, int *  flags  )

static

Definition at line 483 of file fplib.cc.

References fp32_process_NaN().

Referenced by fp32_muladd().

static uint32_t ArmISA::fp32_repack ( int  sgn, int  exp, uint32_t  mnt  )

static

Definition at line 2061 of file fplib.cc.

References fp32_pack().

Referenced by fplibMax(), and fplibMin().

static uint32_t ArmISA::fp32_round ( int  sgn, int  exp, uint32_t  mnt, int  mode, int *  flags  )

static

Definition at line 684 of file fplib.cc.

References fp32_round_().

Referenced by fp32_add(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), and fp32_sqrt().

static uint32_t ArmISA::fp32_round_ ( int  sgn, int  exp, uint32_t  mnt, int  rm, int  mode, int *  flags  )

static

Definition at line 614 of file fplib.cc.

References fp32_infinity(), fp32_max_normal(), fp32_pack(), fp32_zero(), FPLIB_FZ, FPLIB_IXC, FPLIB_OFC, FPLIB_RM, FPLIB_RN, FPLIB_RP, FPLIB_UFC, FPRounding_ODD, FPRounding_TIEAWAY, lsl32(), and lsr32().

Referenced by fp32_round(), and fplibConvert().

static uint32_t ArmISA::fp32_sqrt ( uint32_t  a, int  mode, int *  flags  )

static

Definition at line 1386 of file fplib.cc.

References fp32_defaultNaN(), fp32_infinity(), fp32_normalise(), fp32_process_NaN(), fp32_round(), fp32_unpack(), fp32_zero(), FPLIB_IOC, t0, t1, and X86ISA::x.

Referenced by fplibSqrt().

static void ArmISA::fp32_unpack ( int *  sgn, int *  exp, uint32_t *  mnt, uint32_t  x, int  mode, int *  flags  )

inlinestatic

Definition at line 377 of file fplib.cc.

References FPLIB_FZ, and FPLIB_IDC.

Referenced by fp32_add(), fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibRSqrtStepFused().

static uint32_t ArmISA::fp32_zero ( int  sgn )

inlinestatic

Definition at line 294 of file fplib.cc.

References fp32_pack().

Referenced by fp32_add(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_round_(), fp32_sqrt(), fplibConvert(), fplibMulX(), fplibRecipEstimate(), fplibRoundInt(), and fplibRSqrtEstimate().

static uint64_t ArmISA::fp64_add ( uint64_t  a, uint64_t  b, int  neg, int  mode, int *  flags  )

static

Definition at line 963 of file fplib.cc.

References fp64_defaultNaN(), fp64_infinity(), fp64_normalise(), fp64_process_NaNs(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_IOC, lsl64(), lsr64(), and X86ISA::x.

Referenced by fplibAdd(), and fplibSub().

static int ArmISA::fp64_compare_eq ( uint64_t  a, uint64_t  b, int  mode, int *  flags  )

static

Definition at line 835 of file fplib.cc.

References fp64_unpack(), and FPLIB_IOC.

Referenced by fplibCompareEQ().

static int ArmISA::fp64_compare_ge ( uint64_t  a, uint64_t  b, int  mode, int *  flags  )

static

Definition at line 854 of file fplib.cc.

References fp64_unpack(), and FPLIB_IOC.

Referenced by fplibCompareGE().

static int ArmISA::fp64_compare_gt ( uint64_t  a, uint64_t  b, int  mode, int *  flags  )

static

Definition at line 879 of file fplib.cc.

References fp64_unpack(), and FPLIB_IOC.

Referenced by fplibCompareGT().

static uint64_t ArmISA::fp64_cvtf ( uint64_t  a, int  fbits, int  u, int  mode, int *  flags  )

static

Definition at line 3035 of file fplib.cc.

References a, fp64_normalise(), fp64_round(), and fp64_zero().

Referenced by fplibFixedToFP().

static uint64_t ArmISA::fp64_defaultNaN ( )

inlinestatic

Definition at line 354 of file fplib.cc.

References fp64_pack().

Referenced by fp64_add(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_process_NaN(), fp64_sqrt(), fplibConvert(), and fplibRSqrtEstimate().

static uint64_t ArmISA::fp64_div ( uint64_t  a, uint64_t  b, int  mode, int *  flags  )

static

Definition at line 1309 of file fplib.cc.

References c, cmp128(), fp64_defaultNaN(), fp64_infinity(), fp64_normalise(), fp64_process_NaNs(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_DZC, FPLIB_IOC, lsr128(), mul62x62(), mul64x32(), sub128(), and X86ISA::x.

Referenced by fplibDiv().

static uint64_t ArmISA::fp64_FPConvertNaN_16 ( uint16_t  op )

static

Definition at line 1736 of file fplib.cc.

References fp64_pack().

Referenced by fplibConvert().

static uint64_t ArmISA::fp64_FPConvertNaN_32 ( uint32_t  op )

static

Definition at line 1742 of file fplib.cc.

References fp64_pack().

Referenced by fplibConvert().

static uint64_t ArmISA::fp64_FPOnePointFive ( int  sgn )

static

Definition at line 1754 of file fplib.cc.

References fp64_pack().

Referenced by fplibRSqrtStepFused().

static uint64_t ArmISA::fp64_FPThree ( int  sgn )

static

Definition at line 1766 of file fplib.cc.

References fp64_pack().

Referenced by fplibRSqrtStepFused().

static uint64_t ArmISA::fp64_FPTwo ( int  sgn )

static

Definition at line 1778 of file fplib.cc.

References fp64_pack().

Referenced by fplibMulX(), and fplibRecipStepFused().

static uint64_t ArmISA::fp64_infinity ( int  sgn )

inlinestatic

Definition at line 336 of file fplib.cc.

References fp64_pack().

Referenced by fp64_add(), fp64_div(), fp64_minmaxnum(), fp64_mul(), fp64_muladd(), fp64_round_(), fp64_sqrt(), fplibConvert(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibRSqrtStepFused().

static uint64_t ArmISA::fp64_max_normal ( int  sgn )

inlinestatic

Definition at line 318 of file fplib.cc.

References fp64_pack().

Referenced by fp64_round_(), and fplibRecipEstimate().

static void ArmISA::fp64_minmaxnum ( uint64_t *  op1, uint64_t *  op2, int  sgn  )

static

Definition at line 2083 of file fplib.cc.

References fp64_infinity().

Referenced by fplibMaxNum(), and fplibMinNum().

static uint64_t ArmISA::fp64_mul ( uint64_t  a, uint64_t  b, int  mode, int *  flags  )

static

Definition at line 1058 of file fplib.cc.

References fp128_normalise(), fp64_defaultNaN(), fp64_infinity(), fp64_process_NaNs(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_IOC, mul62x62(), and X86ISA::x.

Referenced by fplibMul(), and fplibMulX().

static uint64_t ArmISA::fp64_muladd ( uint64_t  a, uint64_t  b, uint64_t  c, int  scale, int  mode, int *  flags  )

static

Definition at line 1178 of file fplib.cc.

References add128(), cmp128(), fp128_normalise(), fp64_defaultNaN(), fp64_infinity(), fp64_process_NaNs3(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_IOC, lsl128(), lsr128(), mul62x62(), sub128(), t0, t1, and X86ISA::x.

Referenced by fplibMulAdd(), fplibRecipStepFused(), and fplibRSqrtStepFused().

static uint64_t ArmISA::fp64_normalise ( uint64_t  mnt, int *  exp  )

inlinestatic

Definition at line 223 of file fplib.cc.

References shift.

Referenced by fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp64_add(), fp64_cvtf(), fp64_div(), fp64_sqrt(), fplibRecipEstimate(), fplibRoundInt(), and fplibRSqrtEstimate().

static uint64_t ArmISA::fp64_pack ( uint64_t  sgn, uint64_t  exp, uint64_t  mnt  )

inlinestatic

Definition at line 282 of file fplib.cc.

Referenced by fp64_defaultNaN(), fp64_FPConvertNaN_16(), fp64_FPConvertNaN_32(), fp64_FPOnePointFive(), fp64_FPThree(), fp64_FPTwo(), fp64_infinity(), fp64_max_normal(), fp64_repack(), fp64_round_(), fp64_zero(), fplibConvert(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

static uint64_t ArmISA::fp64_process_NaN ( uint64_t  a, int  mode, int *  flags  )

inlinestatic

Definition at line 427 of file fplib.cc.

References a, fp64_defaultNaN(), FPLIB_DN, and FPLIB_IOC.

Referenced by fp64_process_NaNs(), fp64_process_NaNs3(), fp64_sqrt(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

static uint64_t ArmISA::fp64_process_NaNs ( uint64_t  a, uint64_t  b, int  mode, int *  flags  )

static

Definition at line 460 of file fplib.cc.

References fp64_process_NaN().

Referenced by fp64_add(), fp64_div(), fp64_mul(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipStepFused(), and fplibRSqrtStepFused().

static uint64_t ArmISA::fp64_process_NaNs3 ( uint64_t  a, uint64_t  b, uint64_t  c, int  mode, int *  flags  )

static

Definition at line 512 of file fplib.cc.

References fp64_process_NaN().

Referenced by fp64_muladd().

static uint64_t ArmISA::fp64_repack ( int  sgn, int  exp, uint64_t  mnt  )

static

Definition at line 2067 of file fplib.cc.

References fp64_pack().

Referenced by fplibMax(), and fplibMin().

static uint64_t ArmISA::fp64_round ( int  sgn, int  exp, uint64_t  mnt, int  mode, int *  flags  )

static

Definition at line 760 of file fplib.cc.

References fp64_round_().

Referenced by fp64_add(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), and fp64_sqrt().

static uint64_t ArmISA::fp64_round_ ( int  sgn, int  exp, uint64_t  mnt, int  rm, int  mode, int *  flags  )

static

Definition at line 690 of file fplib.cc.

References fp64_infinity(), fp64_max_normal(), fp64_pack(), fp64_zero(), FPLIB_FZ, FPLIB_IXC, FPLIB_OFC, FPLIB_RM, FPLIB_RN, FPLIB_RP, FPLIB_UFC, FPRounding_ODD, FPRounding_TIEAWAY, lsl64(), and lsr64().

Referenced by fp64_round().

static uint64_t ArmISA::fp64_sqrt ( uint64_t  a, int  mode, int *  flags  )

static

Definition at line 1443 of file fplib.cc.

References c, cmp128(), fp64_defaultNaN(), fp64_infinity(), fp64_normalise(), fp64_process_NaN(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_IOC, lsl128(), lsr128(), mul62x62(), mul64x32(), MipsISA::r, and X86ISA::x.

Referenced by fplibSqrt().

static void ArmISA::fp64_unpack ( int *  sgn, int *  exp, uint64_t *  mnt, uint64_t  x, int  mode, int *  flags  )

inlinestatic

Definition at line 397 of file fplib.cc.

References FPLIB_FZ, and FPLIB_IDC.

Referenced by fp64_add(), fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibRSqrtStepFused().

static uint64_t ArmISA::fp64_zero ( int  sgn )

inlinestatic

Definition at line 300 of file fplib.cc.

References fp64_pack().

Referenced by fp64_add(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_round_(), fp64_sqrt(), fplibConvert(), fplibMulX(), fplibRecipEstimate(), and fplibRoundInt().

template<typename T >

static T ArmISA::fpAdd ( T  a, T  b  )

inlinestatic

Definition at line 475 of file vfp.hh.

References b.

static double ArmISA::fpAddD ( double  a, double  b  )

inlinestatic

Definition at line 494 of file vfp.hh.

References b.

static float ArmISA::fpAddS ( float  a, float  b  )

inlinestatic

Definition at line 488 of file vfp.hh.

References b.

static FPRounding ArmISA::FPCRRounding ( FPSCR &  fpscr )

inlinestatic

Definition at line 69 of file fplib.hh.

Referenced by fplibRecipEstimate().

template<typename T >

static T ArmISA::fpDiv ( T  a, T  b  )

inlinestatic

Definition at line 525 of file vfp.hh.

References b.

static double ArmISA::fpDivD ( double  a, double  b  )

inlinestatic

Definition at line 518 of file vfp.hh.

References b.

static float ArmISA::fpDivS ( float  a, float  b  )

inlinestatic

Definition at line 512 of file vfp.hh.

References b.

template<class T >

T ArmISA::fplibAbs

(

T

op

)

Floating-point absolute value.

template<>

uint32_t ArmISA::fplibAbs

(

uint32_t

op

)

Definition at line 1607 of file fplib.cc.

template<>

uint64_t ArmISA::fplibAbs

(

uint64_t

op

)

Definition at line 1614 of file fplib.cc.

template<class T >

T ArmISA::fplibAdd	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point add.

template<>

uint32_t ArmISA::fplibAdd	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr
	)

Definition at line 1621 of file fplib.cc.

References fp32_add(), modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibAdd	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr
	)

Definition at line 1631 of file fplib.cc.

References fp64_add(), modeConv(), and set_fpscr0().

template<class T >

int ArmISA::fplibCompare	(	T	op1,
		T	op2,
		bool	signal_nans,
		FPSCR &	fpscr
	)

Floating-point compare (quiet and signaling).

template<>

int ArmISA::fplibCompare	(	uint32_t	op1,
		uint32_t	op2,
		bool	signal_nans,
		FPSCR &	fpscr
	)

Definition at line 1641 of file fplib.cc.

References fp32_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

template<>

int ArmISA::fplibCompare	(	uint64_t	op1,
		uint64_t	op2,
		bool	signal_nans,
		FPSCR &	fpscr
	)

Definition at line 1677 of file fplib.cc.

References fp64_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

template<class T >

bool ArmISA::fplibCompareEQ	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point compare equal.

template<>

bool ArmISA::fplibCompareEQ	(	uint32_t	a,
		uint32_t	b,
		FPSCR &	fpscr
	)

Definition at line 1547 of file fplib.cc.

References fp32_compare_eq(), modeConv(), set_fpscr(), and X86ISA::x.

template<>

bool ArmISA::fplibCompareEQ	(	uint64_t	a,
		uint64_t	b,
		FPSCR &	fpscr
	)

Definition at line 1577 of file fplib.cc.

References fp64_compare_eq(), modeConv(), set_fpscr(), and X86ISA::x.

template<class T >

bool ArmISA::fplibCompareGE	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point compare greater than or equal.

template<>

bool ArmISA::fplibCompareGE	(	uint32_t	a,
		uint32_t	b,
		FPSCR &	fpscr
	)

Definition at line 1557 of file fplib.cc.

References fp32_compare_ge(), modeConv(), set_fpscr(), and X86ISA::x.

template<>

bool ArmISA::fplibCompareGE	(	uint64_t	a,
		uint64_t	b,
		FPSCR &	fpscr
	)

Definition at line 1587 of file fplib.cc.

References fp64_compare_ge(), modeConv(), set_fpscr(), and X86ISA::x.

template<class T >

bool ArmISA::fplibCompareGT	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point compare greater than.

template<>

bool ArmISA::fplibCompareGT	(	uint32_t	a,
		uint32_t	b,
		FPSCR &	fpscr
	)

Definition at line 1567 of file fplib.cc.

References fp32_compare_gt(), modeConv(), set_fpscr(), and X86ISA::x.

template<>

bool ArmISA::fplibCompareGT	(	uint64_t	a,
		uint64_t	b,
		FPSCR &	fpscr
	)

Definition at line 1597 of file fplib.cc.

References fp64_compare_gt(), modeConv(), set_fpscr(), and X86ISA::x.

template<class T1 , class T2 >

T2 ArmISA::fplibConvert	(	T1	op,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Floating-point convert precision.

template<>

uint16_t ArmISA::fplibConvert	(	uint32_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Definition at line 1785 of file fplib.cc.

References fp16_defaultNaN(), fp16_FPConvertNaN_32(), fp16_infinity(), fp16_round_(), fp16_zero(), fp32_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

template<>

uint16_t ArmISA::fplibConvert	(	uint64_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Definition at line 1831 of file fplib.cc.

References fp16_defaultNaN(), fp16_FPConvertNaN_64(), fp16_infinity(), fp16_round_(), fp16_zero(), fp64_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

template<>

uint32_t ArmISA::fplibConvert	(	uint16_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Definition at line 1877 of file fplib.cc.

References fp16_normalise(), fp16_unpack(), fp32_defaultNaN(), fp32_FPConvertNaN_16(), fp32_infinity(), fp32_pack(), fp32_zero(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

template<>

uint32_t ArmISA::fplibConvert	(	uint64_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Definition at line 1913 of file fplib.cc.

References fp32_defaultNaN(), fp32_FPConvertNaN_64(), fp32_infinity(), fp32_round_(), fp32_zero(), fp64_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibConvert	(	uint16_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Definition at line 1950 of file fplib.cc.

References fp16_normalise(), fp16_unpack(), fp64_defaultNaN(), fp64_FPConvertNaN_16(), fp64_infinity(), fp64_pack(), fp64_zero(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibConvert	(	uint32_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Definition at line 1986 of file fplib.cc.

References fp32_normalise(), fp32_unpack(), fp64_defaultNaN(), fp64_FPConvertNaN_32(), fp64_infinity(), fp64_pack(), fp64_zero(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

template<class T >

T ArmISA::fplibDiv	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point division.

template<>

uint32_t ArmISA::fplibDiv	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2042 of file fplib.cc.

References fp32_div(), modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibDiv	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2052 of file fplib.cc.

References fp64_div(), modeConv(), and set_fpscr0().

template<class T >

T ArmISA::fplibFixedToFP	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Floating-point convert from fixed-point.

Definition at line 3053 of file fplib.cc.

References fp32_cvtf(), fp64_cvtf(), and set_fpscr0().

template<>

uint32_t ArmISA::fplibFixedToFP	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Floating-point convert from fixed-point.

Definition at line 3053 of file fplib.cc.

template<>

uint64_t ArmISA::fplibFixedToFP	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Floating-point convert from fixed-point.

Definition at line 3065 of file fplib.cc.

References fp32_cvtf(), fp64_cvtf(), and set_fpscr0().

template<class T1 , class T2 >

T2 ArmISA::fplibFPToFixed	(	T1	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Floating-point convert to fixed-point.

template<>

uint32_t ArmISA::fplibFPToFixed	(	uint32_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Definition at line 2917 of file fplib.cc.

References fp32_unpack(), FPLIB_IOC, FPToFixed_32(), modeConv(), and set_fpscr0().

template<>

uint32_t ArmISA::fplibFPToFixed	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Definition at line 2942 of file fplib.cc.

References fp64_unpack(), FPLIB_IOC, FPToFixed_32(), modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibFPToFixed	(	uint32_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Definition at line 2967 of file fplib.cc.

References fp32_unpack(), FPLIB_IOC, FPToFixed_64(), modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibFPToFixed	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr
	)

Definition at line 2993 of file fplib.cc.

References fp64_unpack(), FPLIB_IOC, FPToFixed_64(), modeConv(), and set_fpscr0().

template<class T >

T ArmISA::fplibMax	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point maximum.

template<>

uint32_t ArmISA::fplibMax	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2094 of file fplib.cc.

References fp32_process_NaNs(), fp32_repack(), fp32_unpack(), mode, modeConv(), set_fpscr0(), and X86ISA::x.

template<>

uint64_t ArmISA::fplibMax	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2117 of file fplib.cc.

References fp64_process_NaNs(), fp64_repack(), fp64_unpack(), mode, modeConv(), set_fpscr0(), and X86ISA::x.

template<class T >

T ArmISA::fplibMaxNum	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point maximum number.

template<>

uint32_t ArmISA::fplibMaxNum	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2140 of file fplib.cc.

References fp32_minmaxnum().

template<>

uint64_t ArmISA::fplibMaxNum	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2148 of file fplib.cc.

References fp64_minmaxnum().

template<class T >

T ArmISA::fplibMin	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point minimum.

template<>

uint32_t ArmISA::fplibMin	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2156 of file fplib.cc.

References fp32_process_NaNs(), fp32_repack(), fp32_unpack(), mode, modeConv(), set_fpscr0(), and X86ISA::x.

template<>

uint64_t ArmISA::fplibMin	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2179 of file fplib.cc.

References fp64_process_NaNs(), fp64_repack(), fp64_unpack(), mode, modeConv(), set_fpscr0(), and X86ISA::x.

template<class T >

T ArmISA::fplibMinNum	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point minimum number.

template<>

uint32_t ArmISA::fplibMinNum	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2202 of file fplib.cc.

References fp32_minmaxnum().

template<>

uint64_t ArmISA::fplibMinNum	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2210 of file fplib.cc.

References fp64_minmaxnum().

template<class T >

T ArmISA::fplibMul	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point multiply.

template<>

uint32_t ArmISA::fplibMul	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2218 of file fplib.cc.

References fp32_mul(), modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibMul	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2228 of file fplib.cc.

References fp64_mul(), modeConv(), and set_fpscr0().

template<class T >

T ArmISA::fplibMulAdd	(	T	addend,
		T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point multiply-add.

template<>

uint32_t ArmISA::fplibMulAdd	(	uint32_t	addend,
		uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2022 of file fplib.cc.

References fp32_muladd(), modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibMulAdd	(	uint64_t	addend,
		uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2032 of file fplib.cc.

References fp64_muladd(), modeConv(), and set_fpscr0().

template<class T >

T ArmISA::fplibMulX	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point multiply extended.

template<>

uint32_t ArmISA::fplibMulX	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2238 of file fplib.cc.

References fp32_FPTwo(), fp32_infinity(), fp32_mul(), fp32_process_NaNs(), fp32_unpack(), fp32_zero(), mode, modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibMulX	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2268 of file fplib.cc.

References fp64_FPTwo(), fp64_infinity(), fp64_mul(), fp64_process_NaNs(), fp64_unpack(), fp64_zero(), mode, modeConv(), and set_fpscr0().

template<class T >

T ArmISA::fplibNeg

(

T

op

)

Floating-point negate.

template<>

uint32_t ArmISA::fplibNeg

(

uint32_t

op

)

Definition at line 2298 of file fplib.cc.

template<>

uint64_t ArmISA::fplibNeg

(

uint64_t

op

)

Definition at line 2305 of file fplib.cc.

template<class T >

T ArmISA::fplibRecipEstimate	(	T	op,
		FPSCR &	fpscr
	)

Floating-point reciprocal estimate.

template<>

uint32_t ArmISA::fplibRecipEstimate	(	uint32_t	op,
		FPSCR &	fpscr
	)

Definition at line 2484 of file fplib.cc.

References fp32_infinity(), fp32_max_normal(), fp32_normalise(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), fp32_zero(), FPCRRounding(), FPLIB_DZC, FPLIB_IXC, FPLIB_OFC, FPLIB_UFC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibRecipEstimate	(	uint64_t	op,
		FPSCR &	fpscr
	)

Definition at line 2545 of file fplib.cc.

References fp64_infinity(), fp64_max_normal(), fp64_normalise(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), fp64_zero(), FPCRRounding(), FPLIB_DZC, FPLIB_IXC, FPLIB_OFC, FPLIB_UFC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), and set_fpscr0().

template<class T >

T ArmISA::fplibRecipStepFused	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point reciprocal step.

template<>

uint32_t ArmISA::fplibRecipStepFused	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2455 of file fplib.cc.

References fp32_FPTwo(), fp32_infinity(), fp32_muladd(), fp32_process_NaNs(), fp32_unpack(), mode, modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibRecipStepFused	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2606 of file fplib.cc.

References fp64_FPTwo(), fp64_infinity(), fp64_muladd(), fp64_process_NaNs(), fp64_unpack(), mode, modeConv(), and set_fpscr0().

template<class T >

T ArmISA::fplibRecpX	(	T	op,
		FPSCR &	fpscr
	)

Floating-point reciprocal exponent.

template<>

uint32_t ArmISA::fplibRecpX	(	uint32_t	op,
		FPSCR &	fpscr
	)

Definition at line 2635 of file fplib.cc.

References fp32_pack(), fp32_process_NaN(), fp32_unpack(), mode, modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibRecpX	(	uint64_t	op,
		FPSCR &	fpscr
	)

Definition at line 2662 of file fplib.cc.

References fp64_pack(), fp64_process_NaN(), fp64_unpack(), mode, modeConv(), and set_fpscr0().

template<class T >

T ArmISA::fplibRoundInt	(	T	op,
		FPRounding	rounding,
		bool	exact,
		FPSCR &	fpscr
	)

Floating-point convert to integer.

template<>

uint32_t ArmISA::fplibRoundInt	(	uint32_t	op,
		FPRounding	rounding,
		bool	exact,
		FPSCR &	fpscr
	)

Definition at line 2689 of file fplib.cc.

References fp32_infinity(), fp32_normalise(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), fp32_zero(), FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), X86ISA::op, set_fpscr0(), and X86ISA::x.

template<>

uint64_t ArmISA::fplibRoundInt	(	uint64_t	op,
		FPRounding	rounding,
		bool	exact,
		FPSCR &	fpscr
	)

Definition at line 2752 of file fplib.cc.

References fp64_infinity(), fp64_normalise(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), fp64_zero(), FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), X86ISA::op, set_fpscr0(), and X86ISA::x.

template<class T >

T ArmISA::fplibRSqrtEstimate	(	T	op,
		FPSCR &	fpscr
	)

Floating-point reciprocal square root estimate.

template<>

uint32_t ArmISA::fplibRSqrtEstimate	(	uint32_t	op,
		FPSCR &	fpscr
	)

Definition at line 2331 of file fplib.cc.

References fp32_defaultNaN(), fp32_infinity(), fp32_normalise(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), fp32_zero(), FPLIB_DZC, FPLIB_IOC, mode, modeConv(), recip_sqrt_estimate, and set_fpscr0().

template<>

uint64_t ArmISA::fplibRSqrtEstimate	(	uint64_t	op,
		FPSCR &	fpscr
	)

Definition at line 2364 of file fplib.cc.

References fp32_zero(), fp64_defaultNaN(), fp64_infinity(), fp64_normalise(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), FPLIB_DZC, FPLIB_IOC, mode, modeConv(), recip_sqrt_estimate, and set_fpscr0().

template<class T >

T ArmISA::fplibRSqrtStepFused	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point reciprocal square root step.

template<>

uint32_t ArmISA::fplibRSqrtStepFused	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2397 of file fplib.cc.

References fp32_FPOnePointFive(), fp32_FPThree(), fp32_infinity(), fp32_muladd(), fp32_process_NaNs(), fp32_unpack(), mode, modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibRSqrtStepFused	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2426 of file fplib.cc.

References fp64_FPOnePointFive(), fp64_FPThree(), fp64_infinity(), fp64_muladd(), fp64_process_NaNs(), fp64_unpack(), mode, modeConv(), and set_fpscr0().

template<class T >

T ArmISA::fplibSqrt	(	T	op,
		FPSCR &	fpscr
	)

Floating-point square root.

template<>

uint32_t ArmISA::fplibSqrt	(	uint32_t	op,
		FPSCR &	fpscr
	)

Definition at line 2815 of file fplib.cc.

References fp32_sqrt(), modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibSqrt	(	uint64_t	op,
		FPSCR &	fpscr
	)

Definition at line 2825 of file fplib.cc.

References fp64_sqrt(), modeConv(), and set_fpscr0().

template<class T >

T ArmISA::fplibSub	(	T	op1,
		T	op2,
		FPSCR &	fpscr
	)

Floating-point subtract.

template<>

uint32_t ArmISA::fplibSub	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2835 of file fplib.cc.

References fp32_add(), modeConv(), and set_fpscr0().

template<>

uint64_t ArmISA::fplibSub	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr
	)

Definition at line 2845 of file fplib.cc.

References fp64_add(), modeConv(), and set_fpscr0().

template<typename T >

static T ArmISA::fpMax ( T  a, T  b  )

inlinestatic

Definition at line 636 of file vfp.hh.

References a, and b.

template<typename T >

static T ArmISA::fpMaxNum ( T  a, T  b  )

inlinestatic

Definition at line 619 of file vfp.hh.

References a, b, fpToBits(), signbit(), and ULL.

template<typename T >

static T ArmISA::fpMin ( T  a, T  b  )

inlinestatic

Definition at line 664 of file vfp.hh.

References a, and b.

template<typename T >

static T ArmISA::fpMinNum ( T  a, T  b  )

inlinestatic

Definition at line 647 of file vfp.hh.

References a, b, fpToBits(), signbit(), and ULL.

template<typename T >

static T ArmISA::fpMul ( T  a, T  b  )

inlinestatic

Definition at line 566 of file vfp.hh.

References b.

template<typename T >

static T ArmISA::fpMulAdd ( T  op1, T  op2, T  addend  )

inlinestatic

Definition at line 586 of file vfp.hh.

References bitsToFp(), fpToBits(), and ULL.

static double ArmISA::fpMulD ( double  a, double  b  )

inlinestatic

Definition at line 578 of file vfp.hh.

References b.

static float ArmISA::fpMulS ( float  a, float  b  )

inlinestatic

Definition at line 572 of file vfp.hh.

References b.

template<typename T >

static T ArmISA::fpMulX ( T  a, T  b  )

inlinestatic

Definition at line 532 of file vfp.hh.

References HsailISA::fpclassify(), and fpToBits().

float ArmISA::fpRecipEstimate	(	FPSCR &	fpscr,
		float	op
	)

Definition at line 843 of file vfp.cc.

References bits(), bitsToFp(), HsailISA::fpclassify(), fpToBits(), recipEstimate(), signbit(), and ULL.

template<typename T >

static T ArmISA::fpRecps ( T  a, T  b  )

inlinestatic

Definition at line 697 of file vfp.hh.

References b, FeUnderflow, and HsailISA::fpclassify().

static float ArmISA::fpRecpsS ( float  a, float  b  )

inlinestatic

Definition at line 740 of file vfp.hh.

References b, FeUnderflow, and HsailISA::fpclassify().

template<typename T >

static T ArmISA::fpRIntX ( T  a, FPSCR &  fpscr  )

inlinestatic

Definition at line 607 of file vfp.hh.

float ArmISA::fprSqrtEstimate	(	FPSCR &	fpscr,
		float	op
	)

Definition at line 761 of file vfp.cc.

References bits(), bitsToFp(), HsailISA::fpclassify(), fpToBits(), recipSqrtEstimate(), signbit(), and ULL.

template<typename T >

static T ArmISA::fpRSqrts ( T  a, T  b  )

inlinestatic

Definition at line 675 of file vfp.hh.

References b, FeUnderflow, and HsailISA::fpclassify().

static float ArmISA::fpRSqrtsS ( float  a, float  b  )

inlinestatic

Definition at line 719 of file vfp.hh.

References b, FeUnderflow, and HsailISA::fpclassify().

template<typename T >

static T ArmISA::fpSub ( T  a, T  b  )

inlinestatic

Definition at line 482 of file vfp.hh.

References b.

static double ArmISA::fpSubD ( double  a, double  b  )

inlinestatic

Definition at line 506 of file vfp.hh.

References b.

static float ArmISA::fpSubS ( float  a, float  b  )

inlinestatic

Definition at line 500 of file vfp.hh.

References b.

static uint32_t ArmISA::fpToBits ( float  fp )

inlinestatic

Definition at line 156 of file vfp.hh.

References bits(), MipsISA::fp, and X86ISA::val.

Referenced by ArmISA::FpOp::binaryOp(), ArmISA::FpOp::dblHi(), ArmISA::FpOp::dblLow(), fixDest(), fixFpDFpSDest(), fixFpSFpDDest(), flushToZero(), fpMaxNum(), fpMinNum(), fpMulAdd(), fpMulX(), fpRecipEstimate(), fprSqrtEstimate(), highFromDouble(), isSnan(), lowFromDouble(), ArmISA::FpOp::processNans(), ArmISA::FpOp::ternaryOp(), ArmISA::FpOp::unaryOp(), unsignedRecipEstimate(), unsignedRSqrtEstimate(), vcvtFpDFpH(), and vcvtFpSFpH().

static uint64_t ArmISA::fpToBits ( double  fp )

inlinestatic

Definition at line 168 of file vfp.hh.

References bits(), MipsISA::fp, and X86ISA::val.

static uint32_t ArmISA::FPToFixed_32 ( int  sgn, int  exp, uint64_t  mnt, bool  u, FPRounding  rounding, int *  flags  )

static

Definition at line 2902 of file fplib.cc.

References FPLIB_IOC, FPToFixed_64(), and X86ISA::x.

Referenced by fplibFPToFixed().

static uint64_t ArmISA::FPToFixed_64 ( int  sgn, int  exp, uint64_t  mnt, bool  u, FPRounding  rounding, int *  flags  )

static

Definition at line 2854 of file fplib.cc.

References FPLIB_IOC, FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, lsl64(), lsr64(), and X86ISA::x.

Referenced by fplibFPToFixed(), and FPToFixed_32().

uint64_t ArmISA::getArgument	(	ThreadContext *	tc,
		int &	number,
		uint16_t	size,
		bool	fp
	)

Definition at line 69 of file utility.cc.

References FullSystem, ThreadContext::getVirtProxy(), inAArch64(), MachineBytes, NumArgumentRegs, panic, PortProxy::read(), ThreadContext::readIntReg(), sp, and StackPointerReg.

uint64_t ArmISA::getExecutingAsid ( ThreadContext *  tc )

inline

Definition at line 289 of file utility.hh.

References MISCREG_CONTEXTIDR, and ThreadContext::readMiscReg().

uint32_t ArmISA::getMPIDR	(	ArmSystem *	arm_sys,
		ThreadContext *	tc
	)

Definition at line 199 of file utility.cc.

References ThreadContext::contextId(), ThreadContext::cpuId(), ArmSystem::multiProc, System::multiThread, and ThreadContext::socketId().

Referenced by ArmISA::Reset::invoke(), and ArmISA::ISA::readMiscReg().

static uint8_t ArmISA::getRestoredITBits ( ThreadContext *  tc, CPSR  spsr  )

static

Definition at line 732 of file static_inst.cc.

References bits(), el, EL2, itd, itState(), MISCREG_HSCTLR, MISCREG_SCTLR, opModeToEL(), and ThreadContext::readMiscReg().

Referenced by ArmISA::ArmStaticInst::getPSTATEFromPSR().

template<class XC >

void ArmISA::handleLockedRead ( XC *  xc, Request *  req  )

inline

Definition at line 94 of file locked_mem.hh.

References DPRINTF, Request::getPaddr(), MISCREG_LOCKADDR, and MISCREG_LOCKFLAG.

template<class XC >

void ArmISA::handleLockedSnoop ( XC *  xc, PacketPtr  pkt, Addr  cacheBlockMask  )

inline

Definition at line 65 of file locked_mem.hh.

References DPRINTF, Packet::getAddr(), Packet::isInvalidate(), Packet::isWrite(), MISCREG_LOCKADDR, MISCREG_LOCKFLAG, and MISCREG_SEV_MAILBOX.

template<class XC >

void ArmISA::handleLockedSnoopHit ( XC *  xc )

inline

Definition at line 104 of file locked_mem.hh.

References DPRINTF, MISCREG_LOCKADDR, MISCREG_LOCKFLAG, and MISCREG_SEV_MAILBOX.

template<class XC >

bool ArmISA::handleLockedWrite ( XC *  xc, Request *  req, Addr  cacheBlockMask  )

inline

Definition at line 114 of file locked_mem.hh.

References DPRINTF, Request::getPaddr(), Request::isSwap(), MISCREG_LOCKADDR, MISCREG_LOCKFLAG, Request::setExtraData(), and warn.

static uint32_t ArmISA::highFromDouble ( double  val )

inlinestatic

Definition at line 252 of file vfp.hh.

References fpToBits().

ArmISA::if

(

!

pmu

)

ArmISA::if

(

FullSystem &&

system

)

Definition at line 229 of file isa.cc.

References haveLargeAsid64, haveSecurity, physAddrRange64, and system.

static bool ArmISA::illegalExceptionReturn ( ThreadContext *  tc, CPSR  cpsr, CPSR  spsr  )

static

Definition at line 761 of file static_inst.cc.

References badMode(), badMode32(), EL0, EL2, EL3, ArmSystem::haveSecurity(), ArmSystem::haveVirtualization(), ArmSystem::highestELIs64(), MISCREG_SCR_EL3, mode, ns, opModeToEL(), and ThreadContext::readMiscReg().

Referenced by ArmISA::ArmStaticInst::getPSTATEFromPSR().

bool ArmISA::inAArch64

(

ThreadContext *

tc

)

Definition at line 185 of file utility.cc.

References MISCREG_CPSR, and ThreadContext::readMiscReg().

Referenced by ArmISA::RemoteGDB::gdbRegs(), getArgument(), ArmISA::Stage2LookUp::getTe(), inSecureState(), skipFunction(), and ArmV8KvmCPU::updateThreadContext().

void ArmISA::initCPU	(	ThreadContext *	tc,
		int	cpuId
	)

Definition at line 58 of file utility.cc.

References reset.

static bool ArmISA::inPrivilegedMode ( CPSR  cpsr )

inlinestatic

Definition at line 133 of file utility.hh.

References inUserMode().

static bool ArmISA::inPrivilegedMode ( ThreadContext *  tc )

inlinestatic

Definition at line 139 of file utility.hh.

References inUserMode().

bool ArmISA::inSecureState

(

ThreadContext *

tc

)

Definition at line 176 of file utility.cc.

References ArmSystem::haveSecurity(), inAArch64(), MISCREG_CPSR, MISCREG_SCR, MISCREG_SCR_EL3, and ThreadContext::readMiscReg().

Referenced by ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), ArmISA::Interrupts::checkInterrupts(), ArmISA::Interrupts::checkWfiWake(), ArmISA::ArmStaticInst::cpsrWriteByInstr(), ArmISA::ISA::flattenMiscIndex(), ArmISA::Interrupts::getInterrupt(), ArmISA::Interrupts::getISR(), ArmISA::ISA::getMiscIndices(), ArmISA::PMU::isFiltered(), mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrrMrrc15TrapToHyp(), ArmISA::ISA::readMiscReg(), ArmISA::UndefinedInstruction::routeToHyp(), ArmISA::SupervisorCall::routeToHyp(), ArmISA::PrefetchAbort::routeToHyp(), ArmISA::DataAbort::routeToHyp(), ArmISA::Interrupt::routeToHyp(), ArmISA::FastInterrupt::routeToHyp(), ArmISA::SystemError::routeToHyp(), ArmISA::ISA::setMiscReg(), ArmISA::Interrupts::takeInt(), and ArmISA::TLB::updateMiscReg().

static bool ArmISA::inSecureState ( SCR  scr, CPSR  cpsr  )

inlinestatic

Definition at line 186 of file utility.hh.

References MODE_EL2H, MODE_EL2T, MODE_EL3H, MODE_EL3T, MODE_HYP, and MODE_MON.

static IntRegIndex ArmISA::INTREG_ABT ( unsigned  index )

inlinestatic

Definition at line 401 of file intregs.hh.

References MipsISA::index, IntRegAbtMap, and NUM_ARCH_INTREGS.

Referenced by flattenIntRegModeIndex().

static IntRegIndex ArmISA::INTREG_FIQ ( unsigned  index )

inlinestatic

Definition at line 455 of file intregs.hh.

References MipsISA::index, IntRegFiqMap, and NUM_ARCH_INTREGS.

Referenced by flattenIntRegModeIndex().

static IntRegIndex ArmISA::INTREG_HYP ( unsigned  index )

inlinestatic

Definition at line 347 of file intregs.hh.

References MipsISA::index, IntRegHypMap, and NUM_ARCH_INTREGS.

Referenced by flattenIntRegModeIndex().

static IntRegIndex ArmISA::INTREG_IRQ ( unsigned  index )

inlinestatic

Definition at line 437 of file intregs.hh.

References MipsISA::index, IntRegIrqMap, and NUM_ARCH_INTREGS.

Referenced by flattenIntRegModeIndex().

static IntRegIndex ArmISA::INTREG_MON ( unsigned  index )

inlinestatic

Definition at line 383 of file intregs.hh.

References MipsISA::index, IntRegMonMap, and NUM_ARCH_INTREGS.

Referenced by flattenIntRegModeIndex().

static IntRegIndex ArmISA::INTREG_SVC ( unsigned  index )

inlinestatic

Definition at line 365 of file intregs.hh.

References MipsISA::index, IntRegSvcMap, and NUM_ARCH_INTREGS.

Referenced by flattenIntRegModeIndex().

static IntRegIndex ArmISA::INTREG_UND ( unsigned  index )

inlinestatic

Definition at line 419 of file intregs.hh.

References MipsISA::index, IntRegUndMap, and NUM_ARCH_INTREGS.

Referenced by flattenIntRegModeIndex().

static IntRegIndex ArmISA::INTREG_USR ( unsigned  index )

inlinestatic

Definition at line 329 of file intregs.hh.

References MipsISA::index, IntRegUsrMap, and NUM_ARCH_INTREGS.

Referenced by flattenIntRegModeIndex().

static int ArmISA::intRegInMode ( OperatingMode  mode, int  reg  )

inlinestatic

Definition at line 464 of file intregs.hh.

References intRegsPerMode, NUM_ARCH_INTREGS, and X86ISA::reg.

Referenced by decodeMrsMsrBankedReg(), and ArmISA::MacroMemOp::MacroMemOp().

static bool ArmISA::inUserMode ( CPSR  cpsr )

inlinestatic

Definition at line 121 of file utility.hh.

References MODE_EL0T, and MODE_USER.

Referenced by inPrivilegedMode(), and inUserMode().

static bool ArmISA::inUserMode ( ThreadContext *  tc )

inlinestatic

Definition at line 127 of file utility.hh.

References inUserMode(), MISCREG_CPSR, and ThreadContext::readMiscRegNoEffect().

bool ArmISA::isBigEndian64

(

ThreadContext *

tc

)

Definition at line 261 of file utility.cc.

References currOpMode(), e0e, ee, EL0, EL1, EL2, EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, opModeToEL(), panic, and ThreadContext::readMiscReg().

template<class fpType >

static bool ArmISA::isSnan ( fpType  val )

inlinestatic

Definition at line 205 of file vfp.hh.

References fpToBits(), and ULL.

static bool ArmISA::isSP ( IntRegIndex  reg )

inlinestatic

Definition at line 517 of file intregs.hh.

References INTREG_SPX.

Referenced by ArmISA::Memory64::Memory64(), ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp64::VstMultOp64(), and ArmISA::VstSingleOp64::VstSingleOp64().

static uint8_t ArmISA::itState ( CPSR  psr )

inlinestatic

Definition at line 165 of file utility.hh.

Referenced by getRestoredITBits().

bool ArmISA::longDescFormatInUse

(

ThreadContext *

tc

)

Definition at line 192 of file utility.cc.

References ArmSystem::haveLPAE(), MISCREG_TTBCR, and ThreadContext::readMiscReg().

Referenced by ArmISA::AbortFault< T >::invoke(), ArmISA::TableWalker::processWalkLPAE(), ArmISA::TableWalker::processWalkWrapper(), ArmISA::TLB::translateFs(), ArmISA::TLB::updateMiscReg(), and ArmISA::TableWalker::walk().

static uint32_t ArmISA::lowFromDouble ( double  val )

inlinestatic

Definition at line 246 of file vfp.hh.

References fpToBits().

static void ArmISA::lsl128 ( uint64_t *  r0, uint64_t *  r1, uint64_t  x0, uint64_t  x1, uint32_t  shift  )

inlinestatic

Definition at line 102 of file fplib.cc.

References shift.

Referenced by fp64_muladd(), and fp64_sqrt().

static uint16_t ArmISA::lsl16 ( uint16_t  x, uint32_t  shift  )

inlinestatic

Definition at line 66 of file fplib.cc.

Referenced by fp16_round_().

static uint32_t ArmISA::lsl32 ( uint32_t  x, uint32_t  shift  )

inlinestatic

Definition at line 78 of file fplib.cc.

Referenced by fp32_add(), and fp32_round_().

static uint64_t ArmISA::lsl64 ( uint64_t  x, uint32_t  shift  )

inlinestatic

Definition at line 90 of file fplib.cc.

Referenced by fp32_mul(), fp32_muladd(), fp64_add(), fp64_round_(), and FPToFixed_64().

static void ArmISA::lsr128 ( uint64_t *  r0, uint64_t *  r1, uint64_t  x0, uint64_t  x1, uint32_t  shift  )

inlinestatic

Definition at line 120 of file fplib.cc.

References shift.

Referenced by fp64_div(), fp64_muladd(), and fp64_sqrt().

static uint16_t ArmISA::lsr16 ( uint16_t  x, uint32_t  shift  )

inlinestatic

Definition at line 72 of file fplib.cc.

Referenced by fp16_round_().

static uint32_t ArmISA::lsr32 ( uint32_t  x, uint32_t  shift  )

inlinestatic

Definition at line 84 of file fplib.cc.

Referenced by fp32_add(), and fp32_round_().

static uint64_t ArmISA::lsr64 ( uint64_t  x, uint32_t  shift  )

inlinestatic

Definition at line 96 of file fplib.cc.

Referenced by fp32_mul(), fp32_muladd(), fp64_add(), fp64_round_(), and FPToFixed_64().

static double ArmISA::makeDouble ( uint32_t  low, uint32_t  high  )

inlinestatic

Definition at line 239 of file vfp.hh.

References bitsToFp().

static IntRegIndex ArmISA::makeSP ( IntRegIndex  reg )

inlinestatic

Definition at line 501 of file intregs.hh.

References INTREG_SPX, INTREG_X31, and X86ISA::reg.

Referenced by ArmISA::PairMemOp::PairMemOp(), ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp64::VstMultOp64(), and ArmISA::VstSingleOp64::VstSingleOp64().

static IntRegIndex ArmISA::makeZero ( IntRegIndex  reg )

inlinestatic

Definition at line 509 of file intregs.hh.

References INTREG_X31, INTREG_ZERO, and X86ISA::reg.

bool ArmISA::mcrMrc14TrapToHyp	(	const MiscRegIndex	miscReg,
		HCR	hcr,
		CPSR	cpsr,
		SCR	scr,
		HDCR	hdcr,
		HSTR	hstr,
		HCPTR	hcptr,
		uint32_t	iss
	)

Definition at line 477 of file utility.cc.

References inform, inSecureState(), mcrMrcIssExtract(), MISCREG_DBGDRAR, MISCREG_DBGDSAR, MISCREG_DBGOSDLR, MISCREG_DBGOSLAR, MISCREG_DBGOSLSR, MISCREG_DBGPRCR, MISCREG_JIDR, MISCREG_JMCR, MISCREG_JOSCR, MISCREG_TEECR, MISCREG_TEEHBR, MODE_HYP, opc2, rt, and unflattenMiscReg().

bool ArmISA::mcrMrc15TrapToHyp	(	const MiscRegIndex	miscReg,
		HCR	hcr,
		CPSR	cpsr,
		SCR	scr,
		HDCR	hdcr,
		HSTR	hstr,
		HCPTR	hcptr,
		uint32_t	iss
	)

Definition at line 356 of file utility.cc.

References inSecureState(), mcrMrcIssExtract(), MISCREG_ACTLR, MISCREG_ADFSR, MISCREG_AIDR, MISCREG_AIFSR, MISCREG_CCSIDR, MISCREG_CLIDR, MISCREG_CONTEXTIDR, MISCREG_CPACR, MISCREG_CSSELR, MISCREG_CTR, MISCREG_DACR, MISCREG_DCCIMVAC, MISCREG_DCCISW, MISCREG_DCCMVAC, MISCREG_DCCMVAU, MISCREG_DCCSW, MISCREG_DCIMVAC, MISCREG_DCISW, MISCREG_DFAR, MISCREG_DFSR, MISCREG_DTLBIALL, MISCREG_DTLBIASID, MISCREG_DTLBIMVA, MISCREG_ICIALLU, MISCREG_ICIALLUIS, MISCREG_ICIMVAU, MISCREG_ID_AFR0, MISCREG_ID_DFR0, MISCREG_ID_ISAR0, MISCREG_ID_ISAR1, MISCREG_ID_ISAR2, MISCREG_ID_ISAR3, MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, MISCREG_ID_MMFR0, MISCREG_ID_MMFR1, MISCREG_ID_MMFR2, MISCREG_ID_MMFR3, MISCREG_ID_PFR0, MISCREG_ID_PFR1, MISCREG_IFAR, MISCREG_IFSR, MISCREG_ITLBIALL, MISCREG_ITLBIASID, MISCREG_ITLBIMVA, MISCREG_MAIR0, MISCREG_MAIR1, MISCREG_NMRR, MISCREG_PMCR, MISCREG_PRRR, MISCREG_REVIDR, MISCREG_SCTLR, MISCREG_TCMTR, MISCREG_TLBIALL, MISCREG_TLBIALLIS, MISCREG_TLBIASID, MISCREG_TLBIASIDIS, MISCREG_TLBIMVA, MISCREG_TLBIMVAA, MISCREG_TLBIMVAAIS, MISCREG_TLBIMVAIS, MISCREG_TLBTR, MISCREG_TTBCR, MISCREG_TTBR0, MISCREG_TTBR1, MODE_HYP, opc2, rt, and unflattenMiscReg().

Referenced by McrMrcMiscInst::execute().

static uint32_t ArmISA::mcrMrcIssBuild ( bool  isRead, uint32_t  crm, IntRegIndex  rt, uint32_t  crn, uint32_t  opc1, uint32_t  opc2  )

inlinestatic

Definition at line 209 of file utility.hh.

static void ArmISA::mcrMrcIssExtract ( uint32_t  iss, bool &  isRead, uint32_t &  crm, IntRegIndex &  rt, uint32_t &  crn, uint32_t &  opc1, uint32_t &  opc2  )

inlinestatic

Definition at line 221 of file utility.hh.

Referenced by mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), and mcrrMrrc15TrapToHyp().

bool ArmISA::mcrrMrrc15TrapToHyp	(	const MiscRegIndex	miscReg,
		CPSR	cpsr,
		SCR	scr,
		HSTR	hstr,
		HCR	hcr,
		uint32_t	iss
	)

Definition at line 527 of file utility.cc.

References inSecureState(), mcrMrcIssExtract(), MISCREG_ADFSR, MISCREG_AIFSR, MISCREG_CONTEXTIDR, MISCREG_DACR, MISCREG_DFAR, MISCREG_DFSR, MISCREG_IFAR, MISCREG_IFSR, MISCREG_MAIR0, MISCREG_MAIR1, MISCREG_NMRR, MISCREG_PRRR, MISCREG_SCTLR, MISCREG_TTBCR, MISCREG_TTBR0, MISCREG_TTBR1, MODE_HYP, opc2, rt, and unflattenMiscReg().

static uint32_t ArmISA::mcrrMrrcIssBuild ( bool  isRead, uint32_t  crm, IntRegIndex  rt, IntRegIndex  rt2, uint32_t  opc1  )

inlinestatic

Definition at line 233 of file utility.hh.

static int ArmISA::modeConv ( FPSCR  fpscr )

static

Definition at line 1514 of file fplib.cc.

Referenced by fplibAdd(), fplibCompare(), fplibCompareEQ(), fplibCompareGE(), fplibCompareGT(), fplibConvert(), fplibDiv(), fplibFPToFixed(), fplibMax(), fplibMin(), fplibMul(), fplibMulAdd(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), fplibSqrt(), and fplibSub().

static uint32_t ArmISA::modified_imm ( uint8_t  ctrlImm, uint8_t  dataImm  )

inlinestatic

Definition at line 59 of file pred_inst.hh.

static uint32_t ArmISA::msrMrs64IssBuild ( bool  isRead, uint32_t  op0, uint32_t  op1, uint32_t  crn, uint32_t  crm, uint32_t  op2, IntRegIndex  rt  )

inlinestatic

Definition at line 244 of file utility.hh.

bool ArmISA::msrMrs64TrapToHyp	(	const MiscRegIndex	miscReg,
		ExceptionLevel	el,
		bool	isRead,
		CPTR	cptr,
		HCR	hcr,
		bool *	isVfpNeon
	)

Definition at line 594 of file utility.cc.

References EL1, MISCREG_ACTLR_EL1, MISCREG_AFSR0_EL1, MISCREG_AFSR1_EL1, MISCREG_AIDR_EL1, MISCREG_AMAIR_EL1, MISCREG_CCSIDR_EL1, MISCREG_CLIDR_EL1, MISCREG_CONTEXTIDR_EL1, MISCREG_CPACR_EL1, MISCREG_CSSELR_EL1, MISCREG_CTR_EL0, MISCREG_DC_CISW_Xt, MISCREG_DC_CIVAC_Xt, MISCREG_DC_CSW_Xt, MISCREG_DC_CVAC_Xt, MISCREG_DC_CVAU_Xt, MISCREG_DC_ISW_Xt, MISCREG_DC_IVAC_Xt, MISCREG_ESR_EL1, MISCREG_FAR_EL1, MISCREG_FPCR, MISCREG_FPEXC32_EL2, MISCREG_FPSR, MISCREG_IC_IVAU_Xt, MISCREG_ICIALLU, MISCREG_ICIALLUIS, MISCREG_ID_AA64AFR0_EL1, MISCREG_ID_AA64AFR1_EL1, MISCREG_ID_AA64DFR0_EL1, MISCREG_ID_AA64DFR1_EL1, MISCREG_ID_AA64ISAR0_EL1, MISCREG_ID_AA64ISAR1_EL1, MISCREG_ID_AA64MMFR0_EL1, MISCREG_ID_AA64MMFR1_EL1, MISCREG_ID_AA64PFR0_EL1, MISCREG_ID_AA64PFR1_EL1, MISCREG_ID_AFR0_EL1, MISCREG_ID_DFR0_EL1, MISCREG_ID_ISAR0_EL1, MISCREG_ID_ISAR1_EL1, MISCREG_ID_ISAR2_EL1, MISCREG_ID_ISAR3_EL1, MISCREG_ID_ISAR4_EL1, MISCREG_ID_ISAR5_EL1, MISCREG_ID_MMFR0_EL1, MISCREG_ID_MMFR1_EL1, MISCREG_ID_MMFR2_EL1, MISCREG_ID_MMFR3_EL1, MISCREG_ID_PFR0_EL1, MISCREG_ID_PFR1_EL1, MISCREG_MAIR_EL1, MISCREG_MVFR0_EL1, MISCREG_MVFR1_EL1, MISCREG_MVFR2_EL1, MISCREG_REVIDR_EL1, MISCREG_SCTLR_EL1, MISCREG_TCR_EL1, MISCREG_TLBI_ASIDE1_Xt, MISCREG_TLBI_ASIDE1IS_Xt, MISCREG_TLBI_VAAE1_Xt, MISCREG_TLBI_VAAE1IS_Xt, MISCREG_TLBI_VAALE1_Xt, MISCREG_TLBI_VAALE1IS_Xt, MISCREG_TLBI_VAE1_Xt, MISCREG_TLBI_VAE1IS_Xt, MISCREG_TLBI_VALE1_Xt, MISCREG_TLBI_VALE1IS_Xt, MISCREG_TLBI_VMALLE1, MISCREG_TLBI_VMALLE1IS, MISCREG_TTBR0_EL1, and MISCREG_TTBR1_EL1.

bool ArmISA::msrMrs64TrapToMon	(	const MiscRegIndex	miscReg,
		CPTR	cptr,
		ExceptionLevel	el,
		bool *	isVfpNeon
	)

Definition at line 724 of file utility.cc.

References EL1, EL2, MISCREG_CPACR_EL1, MISCREG_CPTR_EL2, MISCREG_FPCR, MISCREG_FPEXC32_EL2, and MISCREG_FPSR.

bool ArmISA::msrMrs64TrapToSup	(	const MiscRegIndex	miscReg,
		ExceptionLevel	el,
		CPACR	cpacr
	)

Definition at line 575 of file utility.cc.

References EL0, EL1, MISCREG_FPCR, MISCREG_FPEXC32_EL2, and MISCREG_FPSR.

static void ArmISA::mul62x62 ( uint64_t *  x0, uint64_t *  x1, uint64_t  a, uint64_t  b  )

inlinestatic

Definition at line 138 of file fplib.cc.

References MipsISA::a0, a1, X86ISA::b1, and mask.

Referenced by fp64_div(), fp64_mul(), fp64_muladd(), and fp64_sqrt().

static void ArmISA::mul64x32 ( uint64_t *  x0, uint64_t *  x1, uint64_t  a, uint32_t  b  )

inlinestatic

Definition at line 156 of file fplib.cc.

References b, t0, and t1.

Referenced by fp64_div(), and fp64_sqrt().

static unsigned int ArmISA::number_of_ones ( int32_t  val )

inlinestatic

Definition at line 52 of file macromem.hh.

References i.

Referenced by ArmISA::MacroMemOp::MacroMemOp().

static bool ArmISA::opModeIsH ( OperatingMode  mode )

inlinestatic

Definition at line 650 of file types.hh.

References MODE_EL1H, MODE_EL2H, and MODE_EL3H.

static bool ArmISA::opModeIsT ( OperatingMode  mode )

inlinestatic

Definition at line 656 of file types.hh.

References MODE_EL0T, MODE_EL1T, MODE_EL2T, and MODE_EL3T.

Referenced by ArmISA::ArmFaultVals< FastInterrupt >::offset64().

static ExceptionLevel ArmISA::opModeToEL ( OperatingMode  mode )

inlinestatic

Definition at line 663 of file types.hh.

References EL0, EL1, EL2, EL3, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, and panic.

Referenced by canReadAArch64SysReg(), canWriteAArch64SysReg(), ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), ArmISA::ISA::flattenIntIndex(), getRestoredITBits(), illegalExceptionReturn(), ArmISA::ArmFault::invoke(), isBigEndian64(), ArmISA::PMU::isFiltered(), SPAlignmentCheckEnabled(), and ArmISA::TLB::updateMiscReg().

VfpSavedState ArmISA::prepFpState

(

uint32_t

rMode

)

Definition at line 173 of file vfp.cc.

References FeAllExceptions, FeRoundDown, FeRoundNearest, FeRoundUpward, FeRoundZero, VfpRoundDown, VfpRoundNearest, VfpRoundUpward, and VfpRoundZero.

Referenced by ArmISA::FpOp::binaryOp(), ArmISA::FpOp::ternaryOp(), and ArmISA::FpOp::unaryOp().

void ArmISA::preUnflattenMiscReg

(

)

Definition at line 2074 of file miscregs.cc.

References i, MISCREG_BANKED, MISCREG_BANKED_CHILD, miscRegInfo, NUM_MISCREGS, and X86ISA::reg.

Addr ArmISA::PteAddr ( Addr  a )

inline

Definition at line 43 of file vtophys.hh.

References PteMask, and PteShift.

Addr ArmISA::purifyTaggedAddr	(	Addr	addr,
		ThreadContext *	tc,
		ExceptionLevel	el,
		TTBCR	tcr
	)

Removes the tag from tagged addresses if that mode is enabled.

Parameters

addr	The address to be purified.
tc	The thread context.
el	The controlled exception level.

Returns

The purified address.

Definition at line 279 of file utility.cc.

References addr, bits(), EL0, EL1, EL2, EL3, ArmSystem::haveSecurity(), ArmSystem::haveVirtualization(), mask, MISCREG_TCR_EL2, panic, and ThreadContext::readMiscReg().

Referenced by ArmISA::TLB::checkPermissions64(), ArmISA::TLB::getTE(), ArmISA::ArmFault::invoke64(), ArmISA::TLB::translateFs(), ArmISA::TLB::translateSe(), and ArmISA::TableWalker::walk().

Addr ArmISA::purifyTaggedAddr	(	Addr	addr,
		ThreadContext *	tc,
		ExceptionLevel	el
	)

Definition at line 310 of file utility.cc.

References addr, bits(), EL0, EL1, EL2, EL3, ArmSystem::haveSecurity(), ArmSystem::haveVirtualization(), mask, MISCREG_TCR_EL1, MISCREG_TCR_EL2, MISCREG_TCR_EL3, panic, and ThreadContext::readMiscReg().

XReg ArmISA::readVecElem ( VReg  src, int  index, int  eSize  )

inline

Read a single NEON vector element.

Definition at line 94 of file neon64_mem.hh.

References data, ArmISA::VReg::hi, and ArmISA::VReg::lo.

static double ArmISA::recipEstimate ( double  a )

static

Definition at line 830 of file vfp.cc.

References q, MipsISA::r, and s.

Referenced by fpRecipEstimate(), and unsignedRecipEstimate().

static double ArmISA::recipSqrtEstimate ( double  a )

static

Definition at line 743 of file vfp.cc.

References MipsISA::r, and s.

Referenced by fprSqrtEstimate(), and unsignedRSqrtEstimate().

static uint32_t ArmISA::rotate_imm ( uint32_t  immValue, uint32_t  rotateValue  )

inlinestatic

Definition at line 51 of file pred_inst.hh.

Referenced by ArmISA::PredImmOp::PredImmOp().

template<typename T >

static T ArmISA::roundNEven ( T  a )

inlinestatic

Definition at line 762 of file vfp.hh.

References X86ISA::val.

Addr ArmISA::roundPage

(

Addr

addr

)

Definition at line 350 of file utility.cc.

References PageBytes.

static void ArmISA::set_fpscr ( FPSCR &  fpscr, int  flags  )

static

Definition at line 1520 of file fplib.cc.

References FPLIB_DZC, FPLIB_IDC, FPLIB_IOC, FPLIB_IXC, FPLIB_OFC, and FPLIB_UFC.

Referenced by fplibCompareEQ(), fplibCompareGE(), and fplibCompareGT().

static void ArmISA::set_fpscr0 ( FPSCR &  fpscr, int  flags  )

static

Definition at line 1363 of file fplib.cc.

References FPLIB_DZC, FPLIB_IDC, FPLIB_IOC, FPLIB_IXC, FPLIB_OFC, and FPLIB_UFC.

Referenced by fplibAdd(), fplibCompare(), fplibConvert(), fplibDiv(), fplibFixedToFP(), fplibFPToFixed(), fplibMax(), fplibMin(), fplibMul(), fplibMulAdd(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), fplibSqrt(), and fplibSub().

static void ArmISA::setFPExceptions ( int  exceptions )

inlinestatic

Definition at line 258 of file vfp.hh.

References FeAllExceptions.

Referenced by vfpFpToFixed().

pmu ArmISA::setISA

(

this

)

template<class T >

static void ArmISA::setVfpMicroFlags ( VfpMicroMode  mode, T &  flags  )

inlinestatic

Definition at line 62 of file vfp.hh.

References VfpFirstMicroop, VfpLastMicroop, VfpMicroop, and VfpNotAMicroop.

Referenced by ArmISA::FpRegImmOp::FpRegImmOp(), ArmISA::FpRegRegImmOp::FpRegRegImmOp(), ArmISA::FpRegRegOp::FpRegRegOp(), ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp(), ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp(), ArmISA::FpRegRegRegOp::FpRegRegRegOp(), and ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp().

static uint64_t ArmISA::simd_modified_imm ( bool  op, uint8_t  cmode, uint8_t  data, bool &  immValid, bool  isAarch64 = false  )

inlinestatic

Definition at line 82 of file pred_inst.hh.

References bits(), data, i, and ULL.

void ArmISA::skipFunction

(

ThreadContext *

tc

)

Definition at line 131 of file utility.cc.

References ThreadContext::getCheckerCpuPtr(), inAArch64(), INTREG_X30, ThreadContext::pcState(), ThreadContext::pcStateNoRecord(), ThreadContext::readIntReg(), ReturnAddressReg, and ULL.

bool ArmISA::SPAlignmentCheckEnabled

(

ThreadContext *

tc

)

Definition at line 875 of file utility.cc.

References currOpMode(), EL0, EL1, EL2, EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, opModeToEL(), panic, ThreadContext::readMiscReg(), sa, and sa0.

void ArmISA::startupCPU ( ThreadContext *  tc, int  cpuId  )

inline

Definition at line 105 of file utility.hh.

References ThreadContext::activate().

static void ArmISA::sub128 ( uint64_t *  x0, uint64_t *  x1, uint64_t  a0, uint64_t  a1, uint64_t  b0, uint64_t  b1  )

inlinestatic

Definition at line 173 of file fplib.cc.

References MipsISA::a0.

Referenced by fp64_div(), and fp64_muladd().

ArmISA::SubBitUnion	(	puswl	,
		24	,
		20
	)

bool ArmISA::testPredicate ( uint32_t  nz, uint32_t  c, uint32_t  v, ConditionCode  code  )

inline

Definition at line 70 of file utility.hh.

References c, COND_AL, COND_CC, COND_CS, COND_EQ, COND_GE, COND_GT, COND_HI, COND_LE, COND_LS, COND_LT, COND_MI, COND_NE, COND_PL, COND_UC, COND_VC, COND_VS, n, panic, v, and z.

Addr ArmISA::truncPage

(

Addr

addr

)

Definition at line 344 of file utility.cc.

References PageBytes.

int ArmISA::unflattenMiscReg

(

int

reg

)

Definition at line 2090 of file miscregs.cc.

References X86ISA::reg.

Referenced by mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrrMrrc15TrapToHyp(), ArmISA::PMU::readMiscReg(), ArmISA::ISA::readMiscReg(), ArmISA::PMU::readMiscRegInt(), ArmISA::PMU::setMiscReg(), and ArmISA::ISA::setMiscReg().

uint32_t ArmISA::unsignedRecipEstimate

(

uint32_t

op

)

Definition at line 879 of file vfp.cc.

References bits(), bitsToFp(), fpToBits(), recipEstimate(), and ULL.

uint32_t ArmISA::unsignedRSqrtEstimate

(

uint32_t

op

)

Definition at line 804 of file vfp.cc.

References bits(), bitsToFp(), fpToBits(), recipSqrtEstimate(), and ULL.

Addr ArmISA::VAddrImpl ( Addr  a )

inline

Definition at line 90 of file isa_traits.hh.

References VAddrImplMask.

Addr ArmISA::VAddrOffset ( Addr  a )

inline

Definition at line 92 of file isa_traits.hh.

References PageOffset.

Addr ArmISA::VAddrVPN ( Addr  a )

inline

Definition at line 91 of file isa_traits.hh.

References PageShift.

uint16_t ArmISA::vcvtFpDFpH	(	FPSCR &	fpscr,
		bool	flush,
		bool	defaultNan,
		uint32_t	rMode,
		bool	ahp,
		double	op
	)

Definition at line 575 of file vfp.cc.

References fpToBits(), and vcvtFpFpH().

static uint16_t ArmISA::vcvtFpFpH ( FPSCR &  fpscr, bool  flush, bool  defaultNan, uint32_t  rMode, bool  ahp, uint64_t  opBits, bool  isDouble  )

inlinestatic

Definition at line 395 of file vfp.cc.

References bits(), mask, mode, replaceBits(), rMode, VfpRoundDown, VfpRoundNearest, and VfpRoundUpward.

Referenced by vcvtFpDFpH(), and vcvtFpSFpH().

static uint64_t ArmISA::vcvtFpHFp ( FPSCR &  fpscr, bool  defaultNan, bool  ahp, uint16_t  op, bool  isDouble  )

inlinestatic

Definition at line 583 of file vfp.cc.

References bits(), mask, and replaceBits().

Referenced by vcvtFpHFpD(), and vcvtFpHFpS().

double ArmISA::vcvtFpHFpD	(	FPSCR &	fpscr,
		bool	defaultNan,
		bool	ahp,
		uint16_t	op
	)

Definition at line 645 of file vfp.cc.

References bitsToFp(), and vcvtFpHFp().

float ArmISA::vcvtFpHFpS	(	FPSCR &	fpscr,
		bool	defaultNan,
		bool	ahp,
		uint16_t	op
	)

Definition at line 655 of file vfp.cc.

References bitsToFp(), and vcvtFpHFp().

uint16_t ArmISA::vcvtFpSFpH	(	FPSCR &	fpscr,
		bool	flush,
		bool	defaultNan,
		uint32_t	rMode,
		bool	ahp,
		float	op
	)

Definition at line 567 of file vfp.cc.

References fpToBits(), and vcvtFpFpH().

static uint64_t ArmISA::vfp_modified_imm ( uint8_t  data, bool  wide  )

inlinestatic

Definition at line 162 of file pred_inst.hh.

References bits(), and data.

template<class fpType >

static void ArmISA::vfpFlushToZero ( FPSCR &  fpscr, fpType &  op  )

inlinestatic

Definition at line 140 of file vfp.hh.

References flushToZero.

Referenced by vfpFlushToZero().

template<class fpType >

static void ArmISA::vfpFlushToZero ( FPSCR &  fpscr, fpType &  op1, fpType &  op2  )

inlinestatic

Definition at line 149 of file vfp.hh.

References vfpFlushToZero().

template<typename T >

uint64_t ArmISA::vfpFpToFixed	(	T	val,
		bool	isSigned,
		uint8_t	width,
		uint8_t	imm,
		bool	useRmode = true,
		VfpRoundingMode	roundMode = VfpRoundZero,
		bool	aarch64 = false
	)

Definition at line 265 of file vfp.hh.

References aarch64, FeAllExceptions, FeInexact, FeInvalid, FeRoundDown, FeRoundNearest, FeRoundUpward, FeRoundZero, HsailISA::fpclassify(), LL, mask, panic, setFPExceptions(), X86ISA::val, VfpRoundAway, VfpRoundDown, VfpRoundNearest, VfpRoundUpward, and VfpRoundZero.

double ArmISA::vfpSFixedToFpD	(	bool	flush,
		bool	defaultNan,
		int64_t	val,
		uint8_t	width,
		uint8_t	imm
	)

Definition at line 722 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), mask, panic, and X86ISA::scale.

float ArmISA::vfpSFixedToFpS	(	bool	flush,
		bool	defaultNan,
		int64_t	val,
		uint8_t	width,
		uint8_t	imm
	)

Definition at line 683 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), mask, panic, and X86ISA::scale.

double ArmISA::vfpUFixedToFpD	(	bool	flush,
		bool	defaultNan,
		uint64_t	val,
		uint8_t	width,
		uint8_t	imm
	)

Definition at line 703 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), panic, and X86ISA::scale.

float ArmISA::vfpUFixedToFpS	(	bool	flush,
		bool	defaultNan,
		uint64_t	val,
		uint8_t	width,
		uint8_t	imm
	)

Definition at line 665 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), panic, and X86ISA::scale.

bool ArmISA::virtvalid	(	ThreadContext *	tc,
		Addr	vaddr
	)

Definition at line 108 of file vtophys.cc.

References try_translate().

Referenced by ArmISA::RemoteGDB::acc().

Addr ArmISA::vtophys ( Addr  vaddr )

inline

Definition at line 62 of file vtophys.cc.

References fatal.

Addr ArmISA::vtophys ( ThreadContext *  tc, Addr  vaddr  )

inline

Definition at line 97 of file vtophys.cc.

References panic, and try_translate().

void ArmISA::writeVecElem ( VReg *  dest, XReg  src, int  index, int  eSize  )

inline

Write a single NEON vector element leaving the others untouched.

Definition at line 60 of file neon64_mem.hh.

References ArmISA::VReg::hi, and ArmISA::VReg::lo.

template<class TC >

void ArmISA::zeroRegisters

(

TC *

tc

)

Function to insure ISA semantics about 0 registers.

Parameters

tc	The thread context.

Variable Documentation

Bitfield< 1 > ArmISA::a

Definition at line 1377 of file miscregs.hh.

Referenced by MuxingKvmGic::clearBankedDistRange(), MuxingKvmGic::clearDistRange(), IGbE::TxDescCache::completionWriteback(), MuxingKvmGic::copyBankedDistRange(), MuxingKvmGic::copyDistRange(), fp32_cvtf(), fp32_process_NaN(), fp64_cvtf(), fp64_process_NaN(), fpMax(), fpMaxNum(), fpMin(), fpMinNum(), MathExpr::MathExpr(), SNHash::operator()(), Net::operator<<(), StackDistCalc::printStack(), Trace::InstRecord::setMem(), ObjectFile::setTextBase(), StackDistCalc::verifyStackDist(), and SparcISA::TLB::writeSfsr().

Bitfield< 22 > ArmISA::a1

Definition at line 1688 of file miscregs.hh.

Referenced by mul62x62().

Bitfield<34> ArmISA::aarch64

Definition at line 86 of file types.hh.

Referenced by EndBitUnion(), and vfpFpToFixed().

Bitfield<23, 20> ArmISA::advSimdHalfPrecision

Definition at line 1670 of file miscregs.hh.

Bitfield<15, 12> ArmISA::advSimdInteger

Definition at line 1668 of file miscregs.hh.

Bitfield<11, 8> ArmISA::advSimdLoadStore

Definition at line 1667 of file miscregs.hh.

ArmISA::advSimdRegisters

Definition at line 1654 of file miscregs.hh.

Bitfield<19, 16> ArmISA::advSimdSinglePrecision

Definition at line 1669 of file miscregs.hh.

Bitfield<29> ArmISA::afe

Definition at line 1526 of file miscregs.hh.

Bitfield<26> ArmISA::ahp

Definition at line 1631 of file miscregs.hh.

Bitfield<8, 6> ArmISA::aif

Definition at line 1380 of file miscregs.hh.

Bitfield<5> ArmISA::amo

Definition at line 1477 of file miscregs.hh.

const int ArmISA::ArgumentReg0 = 0

Definition at line 97 of file registers.hh.

Referenced by ArmProcess::argsInit(), PowerLinuxProcess::getSyscallArg(), PowerProcess::getSyscallArg(), ArmProcess32::getSyscallArg(), ArmProcess64::getSyscallArg(), PowerLinuxProcess::setSyscallArg(), PowerProcess::setSyscallArg(), ArmProcess32::setSyscallArg(), and ArmProcess64::setSyscallArg().

const int ArmISA::ArgumentReg1 = 1

Definition at line 98 of file registers.hh.

Referenced by ArmProcess::argsInit().

const int ArmISA::ArgumentReg2 = 2

Definition at line 99 of file registers.hh.

Referenced by ArmProcess::argsInit().

const int ArmISA::ArgumentReg3 = 3

Definition at line 100 of file registers.hh.

Bitfield< 36 > ArmISA::as

Definition at line 1695 of file miscregs.hh.

Bitfield<31> ArmISA::asedis

Definition at line 1599 of file miscregs.hh.

ArmISA::asid

Definition at line 1790 of file miscregs.hh.

Referenced by TimingSimpleCPU::initiateMemRead(), BaseDynInst< Impl >::initiateMemRead(), BaseDynInst< Impl >::initVars(), Request::setAsid(), ArmISA::ISA::setMiscReg(), Request::setVirt(), TimingSimpleCPU::writeMem(), and BaseDynInst< Impl >::writeMem().

ArmISA::attr

Definition at line 1828 of file miscregs.hh.

Referenced by KvmDevice::getAttrPtr(), KvmKernelGicV2::getGicReg(), KvmDevice::hasAttr(), X86ISA::installSegDesc(), ArmISA::TableWalker::memAttrsAArch64(), ArmISA::TableWalker::memAttrsLPAE(), ArmISA::TLB::setAttr(), KvmDevice::setAttrPtr(), setContextSegment(), KvmKernelGicV2::setGicReg(), setKvmSegmentReg(), ArmISA::ISA::setMiscReg(), X86ISA::TLB::translate(), and X86ISA::GpuTLB::translate().

Bitfield<5> ArmISA::aw

Definition at line 1516 of file miscregs.hh.

Bitfield<7> ArmISA::b

Definition at line 1564 of file miscregs.hh.

Referenced by divCeil(), DRAMCtrl::DRAMCtrl(), execveFunc(), findRegDataType(), LRU::findVictim(), fpAdd(), fpAddD(), fpAddS(), fpDiv(), fpDivD(), fpDivS(), fpMax(), fpMaxNum(), fpMin(), fpMinNum(), fpMul(), fpMulD(), fpMulS(), fpRecps(), fpRecpsS(), fpRSqrts(), fpRSqrtsS(), fpSub(), fpSubD(), fpSubS(), PciDevice::getBAR(), BaseRemoteGDB::getbyte(), MathExpr::MathExpr(), mul64x32(), DRAMCtrl::Rank::processRefreshEvent(), DRAMCtrl::Rank::scheduleWakeUpEvent(), Network::setFromNetQueue(), Network::setToNetQueue(), and NetworkInterface::wakeup().

Bitfield<35> ArmISA::bigThumb

Definition at line 85 of file types.hh.

Bitfield<1, 0> ArmISA::bottom2

Definition at line 67 of file types.hh.

Bitfield<11, 10> ArmISA::bsu

Definition at line 1471 of file miscregs.hh.

Bitfield< 29 > ArmISA::c

Definition at line 1365 of file miscregs.hh.

Referenced by SrcClockDomain::clockPeriod(), Clocked::cyclesToTicks(), Trace::Logger::dump(), fp64_div(), fp64_sqrt(), FUPool::FUPool(), Terminal::in(), PowerISA::IntOp::makeCRField(), PowerISA::FloatOp::makeCRField(), LinearEquation::operator*=(), Terminal::out(), MathExpr::parse(), Printk(), BaseRemoteGDB::recv(), Terminal::regDataAvailCallback(), VirtIODeviceBase::registerKickCallback(), ClockDomain::registerWithClockDomain(), BaseRemoteGDB::send(), IdeDisk::setController(), Message::setMsgCounter(), testPredicate(), to_lower(), SETranslatingPortProxy::tryReadString(), SETranslatingPortProxy::tryWriteString(), DerivedClockDomain::updateClockPeriod(), and Stats::validateStatName().

const int ArmISA::CC_Reg_Base = FP_Reg_Base + NumFloatRegs

Definition at line 114 of file registers.hh.

const char* const ArmISA::ccRegName[NUM_CCREGS]

Initial value:

= {
    "nz",
    "c",
    "v",
    "ge",
    "fp",
    "zero"
}

Definition at line 55 of file ccregs.hh.

Referenced by ArmISA::ArmStaticInst::printReg().

Bitfield<32> ArmISA::cd

Definition at line 1448 of file miscregs.hh.

Bitfield<13> ArmISA::cm

Definition at line 1610 of file miscregs.hh.

ArmISA::cond

Definition at line 63 of file types.hh.

Referenced by HsailISA::CbrInstBase< TargetType >::execute(), HsailISA::CbrInstBase< TargetType >::generateDisassembly(), and ArmISA::ArmFault::setSyndrome().

Bitfield<31, 28> ArmISA::condCode

Definition at line 116 of file types.hh.

Referenced by ArmISA::ArmFault::setSyndrome().

ArmISA::cp0

Definition at line 1503 of file miscregs.hh.

Referenced by MipsISA::ISA::CP0Event::process().

Bitfield< 3, 2 > ArmISA::cp1

Definition at line 1502 of file miscregs.hh.

Bitfield< 21, 20 > ArmISA::cp10

Definition at line 1493 of file miscregs.hh.

Bitfield< 23, 22 > ArmISA::cp11

Definition at line 1492 of file miscregs.hh.

Bitfield< 25, 24 > ArmISA::cp12

Definition at line 1491 of file miscregs.hh.

Bitfield< 27, 26 > ArmISA::cp13

Definition at line 1490 of file miscregs.hh.

Bitfield<5> ArmISA::cp15ben

Definition at line 1570 of file miscregs.hh.

Bitfield< 5, 4 > ArmISA::cp2

Definition at line 1501 of file miscregs.hh.

Bitfield< 7, 6 > ArmISA::cp3

Definition at line 1500 of file miscregs.hh.

Bitfield< 9, 8 > ArmISA::cp4

Definition at line 1499 of file miscregs.hh.

Bitfield< 11, 10 > ArmISA::cp5

Definition at line 1498 of file miscregs.hh.

Bitfield< 13, 12 > ArmISA::cp6

Definition at line 1497 of file miscregs.hh.

Bitfield< 15, 14 > ArmISA::cp7

Definition at line 1496 of file miscregs.hh.

Bitfield< 17, 16 > ArmISA::cp8

Definition at line 1495 of file miscregs.hh.

Bitfield< 19, 18 > ArmISA::cp9

Definition at line 1494 of file miscregs.hh.

Bitfield<11, 8> ArmISA::cpNum

Definition at line 153 of file types.hh.

const uint32_t ArmISA::CpsrMaskQ = 0x08000000

static

Definition at line 1392 of file miscregs.hh.

Referenced by ArmISA::ISA::setMiscReg().

const bool ArmISA::CurThreadInfoImplemented = false

Definition at line 109 of file isa_traits.hh.

const int ArmISA::CurThreadInfoReg = -1

Definition at line 110 of file isa_traits.hh.

Bitfield<27,24> ArmISA::cwg

Definition at line 1817 of file miscregs.hh.

Bitfield<9> ArmISA::d

Definition at line 1375 of file miscregs.hh.

Referenced by TaggedPrefetcher::calculatePrefetch(), StridePrefetcher::calculatePrefetch(), DVFSHandler::clkPeriodAtPerfLevel(), Wavefront::computeActualWgSz(), VirtQueue::consumeDescriptor(), RefCountingPtr< MinorDynInst >::copy(), Trace::Logger::dump(), VirtQueue::dump(), DVFSHandler::DVFSHandler(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::execAtomic(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::execSt(), Process::findDriver(), BaseDynInst< Impl >::Result::get(), CheckerCPU::Result::get(), I2CBus::I2CBus(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::initiateAcc(), VirtQueue::onNotify(), Arguments::operator T(), CopyEngineReg::Reg< uint64_t >::operator()(), iGbReg::Regs::Reg< uint64_t >::operator()(), CopyEngineReg::Reg< uint64_t >::operator=(), iGbReg::Regs::Reg< uint64_t >::operator=(), AddrOperandBase::parseAddr(), DVFSHandler::perfLevel(), ComputeUnit::ReadyWorkgroup(), DistIface::RecvScheduler::resumeRecvTicks(), VoltageDomain::sanitiseVoltages(), BaseDynInst< Impl >::Result::set(), CheckerCPU::Result::set(), Trace::InstRecord::setData(), OutputDirectory::setDirectory(), Topology::shortest_path_to_node(), VirtIOConsole::TermRecvQueue::trySend(), DVFSHandler::UpdateEvent::updatePerfLevel(), DVFSHandler::voltageAtPerfLevel(), I2CBus::write(), and VGic::writeCtrl().

Bitfield<30> ArmISA::d32dis

Definition at line 1598 of file miscregs.hh.

Bitfield<9, 6> ArmISA::daif

Definition at line 1381 of file miscregs.hh.

Referenced by ArmISA::ISA::readMiscReg(), and ArmISA::ISA::setMiscReg().

Bitfield<5> ArmISA::dataRAMSetup

Definition at line 1797 of file miscregs.hh.

Bitfield<11,10> ArmISA::dataRAMSlice

Definition at line 1800 of file miscregs.hh.

Bitfield<12> ArmISA::dc

Definition at line 1470 of file miscregs.hh.

Bitfield<19,16> ArmISA::dCacheLineSize

Definition at line 1815 of file miscregs.hh.

StaticInstPtr ArmISA::decodeInst(ExtMachInst)

ArmISA::decoderFault

Definition at line 72 of file types.hh.

Bitfield<7, 4> ArmISA::defaultNaN

Definition at line 1666 of file miscregs.hh.

Bitfield<19, 16> ArmISA::divide

Definition at line 1658 of file miscregs.hh.

Bitfield<25> ArmISA::dn

Definition at line 1630 of file miscregs.hh.

Bitfield<7, 4> ArmISA::domain

Definition at line 1605 of file miscregs.hh.

Referenced by ArmISA::AbortFault< T >::getFsr().

Bitfield<11, 8> ArmISA::doublePrecision

Definition at line 1656 of file miscregs.hh.

Bitfield<16> ArmISA::ds0

Definition at line 1756 of file miscregs.hh.

Bitfield<17> ArmISA::ds1

Definition at line 1757 of file miscregs.hh.

Bitfield<19> ArmISA::dz

Definition at line 1542 of file miscregs.hh.

Bitfield<1> ArmISA::dzc

Definition at line 1615 of file miscregs.hh.

Bitfield< 9 > ArmISA::dze

Definition at line 1554 of file miscregs.hh.

Bitfield<9> ArmISA::e

Definition at line 1376 of file miscregs.hh.

Referenced by System::addFuncEventOrPanic(), System::addKernelFuncEventOrPanic(), DmaReadFifo::DmaReadFifo(), ThermalModel::doStep(), PCEventQueue::dump(), dumpDmesgEntry(), X86KvmCPU::dumpMSRs(), RubySystem::enqueueRubyEvent(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::execAtomic(), Sequencer::handleLlsc(), Sequencer::invalidateSC(), makeKvmCpuid(), Time::operator double(), SparcISA::TteTag::operator=(), AlphaISA::PageTableEntry::operator=(), SparcISA::PageTableEntry::operator=(), SparcISA::PageTableEntry::populate(), power(), VirtQueue::produceDescriptor(), pybind_init_event(), DmaReadFifo::resumeFillTiming(), SparcISA::TLB::translateData(), ArmISA::TLB::translateFunctional(), SparcISA::TLB::translateInst(), BaseRemoteGDB::trap(), and DmaReadFifo::~DmaReadFifo().

Bitfield<24> ArmISA::e0e

Definition at line 1534 of file miscregs.hh.

Referenced by isBigEndian64().

Bitfield<3> ArmISA::ea

Definition at line 1518 of file miscregs.hh.

Referenced by Net::EthAddr::EthAddr(), Minor::ExecContext::setEA(), and BaseDynInst< Impl >::setEA().

Bitfield<31> ArmISA::eae

Definition at line 1699 of file miscregs.hh.

ArmISA::ec

Definition at line 1837 of file miscregs.hh.

Bitfield<21> ArmISA::eccandParityEnable

Definition at line 1803 of file miscregs.hh.

Bitfield<25> ArmISA::ee

Definition at line 1532 of file miscregs.hh.

Referenced by isBigEndian64().

Bitfield< 3, 2 > ArmISA::el

Definition at line 1384 of file miscregs.hh.

Referenced by canWriteAArch64SysReg(), ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64(), ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), ArmISA::ISA::flattenIntIndex(), getRestoredITBits(), ArmISA::TLB::insert(), ArmISA::PMU::isFiltered(), ArmISA::ISA::setMiscReg(), and ArmISA::Interrupts::takeInt().

ArmISA::else

Initial value:

{
        highestELIs64 = true

Definition at line 236 of file isa.cc.

Bitfield<30> ArmISA::en

Definition at line 1649 of file miscregs.hh.

Referenced by Root::timeSyncEnable(), Root::timeSyncPeriod(), and Root::timeSyncSpinThreshold().

Bitfield<27, 25> ArmISA::encoding

Definition at line 95 of file types.hh.

Referenced by VncServer::setEncodings().

Bitfield< 7 > ArmISA::epd0

Definition at line 1682 of file miscregs.hh.

Bitfield< 23 > ArmISA::epd1

Definition at line 1689 of file miscregs.hh.

Bitfield<23,20> ArmISA::erg

Definition at line 1816 of file miscregs.hh.

Bitfield<12> ArmISA::ext

Definition at line 1609 of file miscregs.hh.

Referenced by Net::Ip6Hdr::extensionLength(), and Net::Ip6Hdr::proto().

Bitfield< 0 > ArmISA::f

Definition at line 1379 of file miscregs.hh.

Referenced by __nan(), BaseRemoteGDB::attach(), Debug::changeFlag(), dumpDebugFlags(), Event::Event(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::execAtomic(), PowerModel::getDynamicPower(), PowerModel::getStaticPower(), flitBuffer::getTopFlit(), BaseDynInst< Impl >::hitExternalSnoop(), main(), BaseDynInst< Impl >::memOpDone(), Linux::openSpecialFile(), BaseDynInst< Impl >::possibleLoadViolation(), ArmISA::TableWalker::processWalk(), ArmISA::TableWalker::processWalkLPAE(), ArmISA::TableWalker::processWalkWrapper(), BaseDynInst< Impl >::recordResult(), PybindSimObjectResolver::resolveSimObject(), StaticInst::setFlag(), Trace::InstRecord::setMem(), LinearSystem::solve(), BaseDynInst< Impl >::translationCompleted(), BaseDynInst< Impl >::translationStarted(), and OutputDirectory::~OutputDirectory().

Bitfield<9> ArmISA::fb

Definition at line 1472 of file miscregs.hh.

Bitfield<14, 12> ArmISA::fd

Definition at line 155 of file types.hh.

Referenced by Terminal::accept(), VncServer::accept(), EtherTapStub::attach(), createObjectFile(), KvmVM::createVCPU(), doGzipLoad(), DtbObject::findReleaseAddr(), Linux::openSpecialFile(), RubySystem::readCompressedTrace(), PseudoInst::readfile(), ElfObject::tryFile(), RubySystem::writeCompressedTrace(), and PollQueue::~PollQueue().

Bitfield<21> ArmISA::fi

Definition at line 1538 of file miscregs.hh.

Referenced by MathExprPowerModel::getStatValue().

Bitfield<2> ArmISA::fiq

Definition at line 1519 of file miscregs.hh.

ArmISA::flushToZero

Definition at line 1665 of file miscregs.hh.

Referenced by ArmISA::FpOp::binaryOp(), fixDivDest(), fixFpDFpSDest(), fixFpSFpDDest(), flushToZero(), ArmISA::FpOp::ternaryOp(), ArmISA::FpOp::unaryOp(), and vfpFlushToZero().

Bitfield<3, 0> ArmISA::fm

Definition at line 157 of file types.hh.

Bitfield<3> ArmISA::fmo

Definition at line 1479 of file miscregs.hh.

Bitfield<18, 16> ArmISA::fn

Definition at line 154 of file types.hh.

Referenced by MathExpr::eval(), and PseudoInst::writefile().

Bitfield<31,29> ArmISA::format

Definition at line 1819 of file miscregs.hh.

Referenced by Printk(), and procInfo().

const int ArmISA::FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1)

Definition at line 113 of file registers.hh.

Referenced by ArmISA::MicroMemOp::generateDisassembly(), ArmISA::FpRegRegOp::generateDisassembly(), ArmISA::FpRegImmOp::generateDisassembly(), ArmISA::FpRegRegImmOp::generateDisassembly(), ArmISA::FpRegRegRegOp::generateDisassembly(), ArmISA::FpRegRegRegCondOp::generateDisassembly(), ArmISA::FpRegRegRegRegOp::generateDisassembly(), and ArmISA::FpRegRegRegImmOp::generateDisassembly().

Bitfield<21, 20> ArmISA::fpen

Definition at line 1592 of file miscregs.hh.

Bitfield<2, 0> ArmISA::fpImm

Definition at line 158 of file types.hh.

Bitfield<3> ArmISA::fpRegImm

Definition at line 156 of file types.hh.

const uint32_t ArmISA::FpscrExcMask = 0x0000009F

static

Definition at line 1643 of file miscregs.hh.

Referenced by ArmISA::ISA::readMiscReg(), and ArmISA::ISA::setMiscReg().

Bitfield<39, 37> ArmISA::fpscrLen

Definition at line 81 of file types.hh.

const uint32_t ArmISA::FpscrQcMask = 0x08000000

static

Definition at line 1645 of file miscregs.hh.

Referenced by ArmISA::ISA::readMiscReg(), and ArmISA::ISA::setMiscReg().

Bitfield<41, 40> ArmISA::fpscrStride

Definition at line 80 of file types.hh.

const int ArmISA::FramePointerReg = 11

Definition at line 101 of file registers.hh.

Referenced by ArmISA::ArmStaticInst::printReg().

Bitfield<10> ArmISA::fsHigh

Definition at line 1607 of file miscregs.hh.

ArmISA::fsLow

Definition at line 1603 of file miscregs.hh.

Bitfield<4> ArmISA::fw

Definition at line 1517 of file miscregs.hh.

Bitfield<24> ArmISA::fz

Definition at line 1629 of file miscregs.hh.

Bitfield<19, 16> ArmISA::ge

Definition at line 1373 of file miscregs.hh.

const bool ArmISA::HasUnalignedMemAcc = true

Definition at line 107 of file isa_traits.hh.

ArmISA::haveLargeAsid64 = false

Definition at line 239 of file isa.cc.

Referenced by if().

ArmISA::haveSecurity = haveLPAE = haveVirtualization = false

Definition at line 238 of file isa.cc.

Referenced by ArmISA::ArmStaticInst::cpsrWriteByInstr(), ArmISA::ArmFault::getVector(), and if().

Bitfield<29> ArmISA::hcd

Definition at line 1451 of file miscregs.hh.

Bitfield<8> ArmISA::hce

Definition at line 1512 of file miscregs.hh.

const uint32_t ArmISA::HighVecs = 0xFFFF0000

Definition at line 104 of file isa_traits.hh.

Referenced by ArmISA::ArmFault::getVector().

Bitfield<7> ArmISA::hpme

Definition at line 1399 of file miscregs.hh.

Bitfield<4, 0> ArmISA::hpmn

Definition at line 1402 of file miscregs.hh.

Bitfield<26, 25> ArmISA::htopcode10_9

Definition at line 181 of file types.hh.

Bitfield<28, 27> ArmISA::htopcode12_11

Definition at line 180 of file types.hh.

Bitfield<20> ArmISA::htopcode4

Definition at line 195 of file types.hh.

Bitfield<21, 20> ArmISA::htopcode5_4

Definition at line 194 of file types.hh.

Bitfield<22> ArmISA::htopcode6

Definition at line 192 of file types.hh.

Bitfield<22, 21> ArmISA::htopcode6_5

Definition at line 193 of file types.hh.

Bitfield<23> ArmISA::htopcode7

Definition at line 190 of file types.hh.

Bitfield<23, 21> ArmISA::htopcode7_5

Definition at line 191 of file types.hh.

Bitfield<24> ArmISA::htopcode8

Definition at line 186 of file types.hh.

Bitfield<24, 21> ArmISA::htopcode8_5

Definition at line 189 of file types.hh.

Bitfield<24, 22> ArmISA::htopcode8_6

Definition at line 188 of file types.hh.

Bitfield<24, 23> ArmISA::htopcode8_7

Definition at line 187 of file types.hh.

Bitfield<25> ArmISA::htopcode9

Definition at line 182 of file types.hh.

Bitfield<25, 20> ArmISA::htopcode9_4

Definition at line 185 of file types.hh.

Bitfield<25, 21> ArmISA::htopcode9_5

Definition at line 184 of file types.hh.

Bitfield<25, 24> ArmISA::htopcode9_8

Definition at line 183 of file types.hh.

Bitfield<19, 16> ArmISA::htrn

Definition at line 197 of file types.hh.

Bitfield<20> ArmISA::hts

Definition at line 198 of file types.hh.

Bitfield< 12 > ArmISA::i

Definition at line 1378 of file miscregs.hh.

Referenced by MemChecker::abortWrite(), AbstractReplacementPolicy::AbstractReplacementPolicy(), ListenSocket::accept(), Terminal::accept(), TCPIface::accept(), FALRU::accessBlock(), Prefetcher::accessNonunitFilter(), Prefetcher::accessUnitFilter(), DRAMCtrl::activateBank(), Histogram::add(), Stats::HistStor::add(), CheckTable::addCheck(), PerfectSwitch::addInPort(), NetDest::addNetDest(), Switch::addOutPort(), IniFile::addSection(), Queue< WriteQueueEntry >::addToReadyList(), CacheRecorder::aggregateRecords(), CacheMemory::allocate(), NetDest::AND(), ScheduleStage::arbitrate(), AlphaProcess::argsInit(), MipsProcess::argsInit(), PowerProcess::argsInit(), SparcProcess::argsInit(), ArmProcess::argsInit(), X86ISA::X86Process::argsInit(), arrayParamIn(), arrayParamOut(), GPUCoalescer::atomicCallback(), HsailISA::AtomicInstBase< MemDataType::OperandType, AddrOperandType, NumSrcOperands, HasDst >::AtomicInstBase(), DataBlock::atomicPartial(), BaseGlobalEventTemplate< GlobalSyncEvent >::BaseGlobalEventTemplate(), BaseSetAssoc::BaseSetAssoc(), BaseSimpleCPU::BaseSimpleCPU(), BiModeBP::BiModeBP(), CxxConfigManager::bindAllPorts(), CxxConfigManager::bindObjectPorts(), bitrev(), BrigObject::BrigObject(), NetDest::broadcast(), broadcast(), Net::EthAddr::broadcast(), LTAGE::btbUpdate(), Minor::ForwardInstData::bubbleFill(), BulkBloomFilter::BulkBloomFilter(), CacheMemory::cacheAvail(), NetworkInterface::calculateVC(), Minor::LSQ::StoreBuffer::canForwardDataToLoad(), Trace::SparcNativeTrace::check(), Trace::ArmNativeTrace::check(), PacketFifo::check(), SwitchAllocator::check_for_wakeup(), PacketQueue::checkFunctional(), SerialLink::SerialLinkMasterPort::checkFunctional(), Bridge::BridgeMasterPort::checkFunctional(), Packet::checkFunctional(), AlphaISA::Interrupts::checkInterrupts(), AbstractMemory::checkLockedAddrList(), CheckTable::CheckTable(), DRAMCtrl::chooseNext(), ClDriver::ClDriver(), X86ISA::GpuTLB::cleanup(), BaseSetAssoc::cleanupRefs(), BlockBloomFilter::clear(), BulkBloomFilter::clear(), H3BloomFilter::clear(), LSB_CountingBloomFilter::clear(), MultiGrainBloomFilter::clear(), NonCountingBloomFilter::clear(), MultiBitSelBloomFilter::clear(), Histogram::clear(), NetDest::clear(), ProfileNode::clear(), StoreSet::clear(), PacketFifo::clear(), SwitchAllocator::clear_request_vector(), SparcISA::Interrupts::clearAll(), TsunamiCChip::clearDRIR(), MaltaCChip::clearIntr(), TsunamiCChip::clearITI(), SparcISA::TLB::clearUsedBits(), OutputDirectory::close(), HsailISA::CmpInstBase< DestDataType::OperandType, SrcDataType::OperandType >::CmpInstBase(), WriteMask::cmpMask(), ClDriver::codeOffToKernelName(), CoherentXBar::CoherentXBar(), SimpleNetwork::collateStats(), Switch::collateStats(), Profiler::collateStats(), Router::collateStats(), GarnetNetwork::collateStats(), DefaultCommit< Impl >::commitHead(), HsailISA::CommonInstBase< DestDataType::OperandType, SrcDataType::OperandType, 1 >::CommonInstBase(), ThreadContext::compare(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::completeAcc(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::completeAcc(), GPUCoalescer::completeHitCallback(), GPUCoalescer::completeIssue(), MemChecker::completeRead(), MemChecker::completeWrite(), BaseSetAssoc::computeStats(), ComputeUnit::ComputeUnit(), FunctionProfile::consume(), X86ISA::convX87TagsToXTags(), X86ISA::convX87XTagsToTags(), PollQueue::copy(), AlphaISA::copyIprs(), SparcISA::copyMiscRegs(), X86ISA::copyMiscRegs(), PacketFifo::copyout(), DataBlock::copyPartial(), PowerISA::copyRegs(), AlphaISA::copyRegs(), copyRegs(), SparcISA::copyRegs(), X86ISA::copyRegs(), Checker< Impl >::copyResult(), copyStringArray(), NetDest::count(), LdsState::countBankConflicts(), PersistentTable::countReadStarvingForAddress(), PersistentTable::countStarvingForAddress(), CpuLocalTimer::CpuLocalTimer(), Topology::createLinks(), GenericTimer::createTimers(), ArmISA::ArmStaticInst::cSwap(), DMASequencer::dataCallback(), LSB_CountingBloomFilter::decrement(), DefaultBTB::DefaultBTB(), DefaultFetch< Impl >::DefaultFetch(), CxxConfigManager::deleteObjects(), SparcISA::TLB::demapPage(), BaseGlobalEvent::deschedule(), StaticInst::destRegIdx(), Debug::AllFlags::disable(), Debug::SimpleFlag::disableAll(), Stats::DistPrint::DistPrint(), TsunamiPChip::dmaAddr(), DRAMCtrl::doDRAMAccess(), Stats::VectorBase< Vector, StatStor >::doInit(), Stats::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::doInit(), ObjectMatch::domatch(), PCEventQueue::doService(), ThermalModel::doStep(), SyscallDesc::doSyscall(), Histogram::doubleBinSize(), FullO3CPU< Impl >::drain(), ArmISA::TableWalker::drain(), DefaultFetch< Impl >::drainResume(), FullO3CPU< Impl >::drainResume(), LSQUnit< Impl >::drainSanityCheck(), MemDepUnit< MemDepPred, Impl >::drainSanityCheck(), DefaultFetch< Impl >::drainSanityCheck(), DRAMCtrl::DRAMCtrl(), ProfileNode::dump(), Trace::Logger::dump(), FunctionProfile::dump(), Trie< Key, Value >::Node::dump(), ArmV8KvmCPU::dump(), ActivityRecorder::dump(), PCEventQueue::dump(), DependencyGraph< DynInstPtr >::dump(), FUPool::dump(), BPredUnit::dump(), IniFile::dump(), SparcISA::TLB::dumpAll(), dumpDebugFlags(), dumpFpuCommon(), dumpKvm(), InstructionQueue< Impl >::dumpLists(), dumpMainQueue(), X86KvmCPU::dumpMSRs(), BaseDynInst< Impl >::eaSrcsReady(), ElfObject::ElfObject(), DependencyGraph< DynInstPtr >::empty(), Minor::MinorBuffer< Minor::ForwardInstData >::empty(), Debug::AllFlags::enable(), Debug::SimpleFlag::enableAll(), Net::EthAddr::EthAddr(), EtherSwitch::EtherSwitch(), Minor::Decode::evaluate(), Minor::Fetch2::evaluate(), Minor::Execute::evaluate(), eventqDump(), X86ISA::TLB::evictLRU(), ConditionRegisterState::exec(), VectorRegisterFile::exec(), Shader::exec(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::execAtomic(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::execSt(), Minor::Execute::Execute(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::execute(), execveFunc(), X86ISA::GpuTLB::exitCallback(), exitImpl(), Topology::extend_shortest_path(), FALRU::FALRU(), FaultModel::fault_prob(), FaultModel::fault_vector(), FaultModel::FaultModel(), WriteMask::fillMask(), SparcISA::TlbMap::find(), AddrRangeMap< AbstractMemory * >::find(), SimObject::find(), OutputDirectory::find(), SymbolTable::findAddress(), CacheSet< Blktype >::findBlk(), Debug::findFlag(), VGic::findHighestPendingLR(), VGic::findLRForVIRQ(), SymbolTable::findNearestAddr(), SymbolTable::findNearestSymbol(), CxxConfigManager::findObject(), CxxConfigManager::findObjectParams(), BaseXBar::findPort(), ControlFlowInfo::findPostDominators(), IniFile::findSection(), PersistentTable::findSmallest(), SymbolTable::findSymbol(), Minor::FUPipeline::findTiming(), CxxConfigManager::findTraversalOrder(), LRU::findVictim(), BaseSetAssoc::findVictim(), firstbit(), AtagCore::flags(), NetworkInterface::flitisizeMessage(), AlphaISA::TLB::flushAddr(), X86ISA::TLB::flushAll(), X86ISA::TLB::flushNonGlobal(), AlphaISA::TLB::flushProcesses(), FALRU::forEachBlk(), BaseSetAssoc::forEachBlk(), CxxConfigManager::forEachObject(), formatParamList(), Gicv2m::frameFromAddr(), SimpleNetwork::functionalRead(), RubySystem::functionalRead(), CrossbarSwitch::functionalWrite(), SimpleNetwork::functionalWrite(), NetworkInterface::functionalWrite(), flitBuffer::functionalWrite(), Switch::functionalWrite(), GarnetNetwork::functionalWrite(), RubySystem::functionalWrite(), Router::functionalWrite(), MessageBuffer::functionalWrite(), InputUnit::functionalWrite(), RubyRequest::functionalWrite(), FuncUnit::FuncUnit(), Minor::FUPipeline::FUPipeline(), FUPool::FUPool(), GarnetNetwork::GarnetNetwork(), MrsOp::generateDisassembly(), HsailISA::CommonInstBase< DestDataType::OperandType, SrcDataType::OperandType, 1 >::generateDisassembly(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::generateDisassembly(), GarnetSyntheticTraffic::generatePkt(), X86ISA::genX87Tags(), BaseDynInst< Impl >::Result::get(), CheckerCPU::Result::get(), NetworkInterface::get_vnet(), Gicv2m::getAddrRanges(), RubyPort::PioSlavePort::getAddrRanges(), NetDest::getAllDest(), PciDevice::getBAR(), CheckTable::getCheck(), Wavefront::getContext(), PowerModel::getDynamicPower(), EtherLink::getEthPort(), ArmFreebsdProcessBits::getFreebsdDesc(), BrigObject::getFunction(), LTAGE::getGHR(), AlphaISA::Interrupts::getInterrupt(), BrigObject::getKernel(), ArmLinuxProcessBits::getLinuxDesc(), LTAGE::getLoop(), Prefetcher::getLRUindex(), WriteMask::getMask(), System::getMasterId(), X86ISA::getMem(), CxxIniFile::getObjectChildren(), Prefetcher::getPrefetchEntry(), ArmKvmCPU::getRegList(), PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), AlphaISA::RemoteGDB::AlphaGdbRegCache::getRegs(), ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), IniFile::getSectionNames(), IndirectPredictor::getSetIndex(), PowerModel::getStaticPower(), BlockBloomFilter::getTotalCount(), BulkBloomFilter::getTotalCount(), H3BloomFilter::getTotalCount(), LSB_CountingBloomFilter::getTotalCount(), MultiGrainBloomFilter::getTotalCount(), NonCountingBloomFilter::getTotalCount(), MultiBitSelBloomFilter::getTotalCount(), LRUPolicy::getVictim(), WeightedLRUPolicy::getVictim(), PseudoLRUPolicy::getVictim(), Gicv2m::Gicv2m(), GPUDynInst::GPUDynInst(), X86ISA::GpuTLB::GpuTLB(), Stats::HistStor::grow_convert(), Stats::HistStor::grow_out(), Stats::HistStor::grow_up(), X86KvmCPU::handleKvmExitIO(), MultiBitSelBloomFilter::hash_bitsel(), H3BloomFilter::hash_H3(), InstructionQueue< Impl >::hasReadyInsts(), GPUCoalescer::hitCallback(), X86ISA::I82094AA::I82094AA(), X86ISA::I8259::I8259(), IdeController::IdeController(), LSB_CountingBloomFilter::increment(), IndirectPredictor::IndirectPredictor(), Stats::InfoAccess::info(), DirectoryMemory::init(), SwitchAllocator::init(), CrossbarSwitch::init(), VecRegisterState::init(), NetworkInterface::init(), GarnetNetwork::init(), AbstractController::init(), PerfectSwitch::init(), StoreSet::init(), RubyTester::init(), ComputeUnit::init(), ListOperand::init(), Stats::Vector2dBase< Vector2d, StatStor >::init(), EmbeddedPython::initAll(), X86ISA::initCPU(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::initiateAcc(), FetchUnit::initiateFetch(), AlphaISA::initIPRs(), ArmProcess32::initState(), FreebsdArmSystem::initState(), ArmProcess64::initState(), LinuxArmSystem::initState(), X86ISA::X86_64Process::initState(), ArmSystem::initState(), X86ISA::I386Process::initState(), System::initState(), BaseO3DynInst< Impl >::initVars(), InputUnit::InputUnit(), AlphaISA::TLB::insert(), SparcISA::TLB::insert(), Trie< Addr, X86ISA::TlbEntry >::insert(), ArmISA::TLB::insert(), PowerISA::TLB::insertAt(), Sequencer::insertRequest(), GPUCoalescer::insertRequest(), SparcISA::ISA::installGlobals(), SparcISA::ISA::installWindow(), SubBlock::internalMergeFrom(), SubBlock::internalMergeTo(), SparcISA::TlbMap::intersect(), NetDest::intersectionIsNotEmpty(), X86ISA::GpuTLB::invalidateAll(), X86ISA::GpuTLB::invalidateNonGlobal(), VIPERCoalescer::invL1(), VIPERCoalescer::invwbL1(), ClDriver::ioctl(), NetDest::isBroadcast(), ComputeUnit::isDone(), MemDepUnit< MemDepPred, Impl >::isDrained(), FUPool::isDrained(), DefaultFetch< Impl >::isDrained(), NetDest::isEmpty(), WriteMask::isEmpty(), NetDest::isEqual(), WriteMask::isFull(), WriteMask::isOverlap(), isPrime(), BlockBloomFilter::isSet(), BulkBloomFilter::isSet(), H3BloomFilter::isSet(), NonCountingBloomFilter::isSet(), MultiGrainBloomFilter::isSet(), MultiBitSelBloomFilter::isSet(), ComputeUnit::isSimdDone(), DMASequencer::issueNext(), GPUCoalescer::issueRequest(), NetDest::isSuperset(), KvmVM::KvmVM(), lastbit(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::LdInst(), Stats::Info::less(), LinearSystem::LinearSystem(), ListenSocket::listen(), EcoffObject::loadGlobalSymbols(), EcoffObject::loadLocalSymbols(), ElfObject::loadSomeSymbols(), CxxConfigManager::loadState(), LocalBP::LocalBP(), AlphaISA::TLB::lookup(), SparcISA::TLB::lookup(), PowerISA::TLB::lookup(), ArmISA::TLB::lookup(), lookupTraceForAddress(), LTAGE::loopUpdate(), X86ISA::IntSourcePin::lower(), VGic::lrPending(), VGic::lrValid(), LTAGE::LTAGE(), ArmISA::MacroVFPMemOp::MacroVFPMemOp(), HsailISA::Call::MagicSimBreak(), main(), SimpleNetwork::makeInternalLink(), Malta::Malta(), GPUCoalescer::mapAddrToPkt(), PersistentTable::markEntries(), System::markWorkItem(), MathExprPowerModel::MathExprPowerModel(), AtagMem::memSize(), AtagMem::memStart(), H3BloomFilter::merge(), NonCountingBloomFilter::merge(), MultiBitSelBloomFilter::merge(), DRAMCtrl::minBankPrep(), MinorCPU::MinorCPU(), MinorOpClassSet::MinorOpClassSet(), Minor::Scoreboard::minorTrace(), Minor::MinorBuffer< Minor::ForwardInstData >::minorTrace(), Minor::Execute::minorTrace(), Minor::LSQ::StoreBuffer::minorTrace(), CacheSet< Blktype >::moveToHead(), FALRU::moveToHead(), CacheSet< Blktype >::moveToTail(), Network::Network(), NetworkInterface::NetworkInterface(), NoncoherentXBar::NoncoherentXBar(), number_of_ones(), System::numRunningContexts(), HsailISA::CommonInstBase< DestDataType::OperandType, SrcDataType::OperandType, 1 >::numSrcRegOperands(), HsailISA::AtomicInstBase< MemDataType::OperandType, AddrOperandType, NumSrcOperands, HasDst >::numSrcRegOperands(), PersistentTable::okToIssueStarving(), VirtIOConsole::TermTransQueue::onNotifyDescriptor(), CowDiskImage::open(), openImpl(), VectorRegisterFile::operandsReady(), PerfectSwitch::operateMessageBuffer(), std::hash< FutexKey >::operator()(), Stats::VectorPrint::operator()(), Stats::DistPrint::operator()(), LinearEquation::operator+(), TimeBuffer< T >::wire::operator++(), TimeBuffer< T >::wire::operator--(), operator<<(), Minor::ForwardInstData::operator=(), TypedBufferArg< T >::operator[](), NetDest::OR(), WriteMask::orMask(), OutputUnit::OutputUnit(), AtagCore::pagesize(), Net::EthAddr::parse(), MathExpr::parse(), TrafficGen::parseConfig(), HexFile::parseLine(), PciDevice::PciDevice(), WriteMask::performAtomic(), PersistentTable::persistentRequestLock(), Pl111::Pl111(), popcount(), TsunamiCChip::postDRIR(), MaltaCChip::postIntr(), TsunamiCChip::postRTC(), LTAGE::predict(), Prefetcher::Prefetcher(), Stats::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy >::prepare(), Stats::Vector2dBase< Vector2d, StatStor >::prepare(), Stats::DistStor::prepare(), Stats::HistStor::prepare(), Stats::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::prepare(), preUnflattenMiscReg(), DataBlock::print(), NetDest::print(), Prefetcher::print(), CacheMemory::print(), SparcISA::TlbMap::print(), WriteMask::print(), BaseSetAssoc::print(), Packet::PrintReqState::printLabels(), MsrBase::printMsrBase(), DRAMCtrl::printQs(), printSorted(), System::printSystems(), IniFile::printUnreferenced(), Histogram::printWithMultiplier(), PowerISA::TLB::probeEntry(), CallbackQueue::process(), TLBCoalescer::IssueProbeEvent::process(), DistIface::SyncEvent::process(), BrigObject::processDirectives(), FetchUnit::processFetchReturn(), PseudoInst::pseudoInst(), PseudoLRUPolicy::PseudoLRUPolicy(), ClockedObject::pwrStateWeights(), Queue< WriteQueueEntry >::Queue(), X86ISA::IntSourcePin::raise(), MinorCPU::randomPriority(), SimpleDisk::read(), CowDiskImage::read(), VirtQueue::VirtRing< struct vring_used_elem >::read(), TraceCPU::ElasticDataGen::InputStream::read(), Sequencer::readCallback(), GPUCoalescer::readCallback(), VGic::readCtrl(), X86ISA::readMemAtomic(), VGic::readVCpu(), PixelConverter::readWord(), ComputeUnit::ReadyWorkgroup(), CacheMemory::recordCacheContents(), SerialLink::SerialLinkSlavePort::recvFunctional(), DRAMSim2::recvFunctional(), Bridge::BridgeSlavePort::recvFunctional(), ComputeUnit::DataPort::recvReqRetry(), ComputeUnit::SQCPort::recvReqRetry(), ComputeUnit::DTLBPort::recvReqRetry(), ComputeUnit::ITLBPort::recvReqRetry(), RubyPort::PioSlavePort::recvTimingReq(), TLBCoalescer::CpuSidePort::recvTimingReq(), SimpleMemory::recvTimingReq(), BaseMemProbe::regProbeListeners(), SimpleNetwork::regStats(), Sequencer::regStats(), Profiler::regStats(), Switch::regStats(), ExecStage::regStats(), GarnetNetwork::regStats(), GPUCoalescer::regStats(), CacheMemory::regStats(), InstructionQueue< Impl >::regStats(), BaseSimpleCPU::regStats(), BaseTags::regStats(), FALRU::regStats(), ClockedObject::regStats(), AbstractMemory::regStats(), ComputeUnit::regStats(), BaseCache::regStats(), BaseXBar::regStats(), SparcISA::ISA::reloadRegMap(), RangeAddrMapper::remapAddr(), PollQueue::remove(), PCEventQueue::remove(), PacketFifo::remove(), OutputDirectory::remove(), BaseRemoteGDB::removeHardBreak(), NetDest::removeNetDest(), CxxConfigManager::rename(), DRAMCtrl::reorderQueue(), CpuEvent::replaceThreadContext(), Minor::ForwardInstData::reportData(), BaseGlobalEvent::reschedule(), ReturnAddrStack::reset(), DefaultBTB::reset(), DependencyGraph< DynInstPtr >::reset(), ActivityRecorder::reset(), LocalBP::reset(), Sinic::Device::reset(), Stats::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy >::reset(), MemChecker::reset(), VirtIODeviceBase::reset(), Stats::Vector2dBase< Vector2d, StatStor >::reset(), Stats::DistStor::reset(), Stats::HistStor::reset(), InstructionQueue< Impl >::resetState(), Sequencer::resetStats(), Switch::resetStats(), AbstractController::resetStats(), Router::resetStats(), GPUCoalescer::resetStats(), NetDest::resize(), Stats::VectorBase< Vector, StatStor >::result(), Stats::VectorProxy< Stat >::result(), Stats::UnaryNode< Op >::result(), Stats::BinaryNode< Op >::result(), Stats::SumNode< Op >::result(), AtagRev::rev(), AtagCore::rootdev(), MinorCPU::roundRobinPriority(), RubyDirectedTester::RubyDirectedTester(), RubyPort::RubyPort(), RubyTester::RubyTester(), StatTest::run(), Sinic::Device::rxKick(), StackDistCalc::sanityCheckTree(), PacketQueue::schedSendTiming(), BaseGlobalEvent::schedule(), BaseGlobalEvent::scheduled(), NetworkInterface::scheduleOutputLink(), Minor::SelfStallingPipeline< ElemType, ReportTraits, BubbleTraits >::SelfStallingPipeline(), NoMaliGpu::serialize(), SymbolTable::serialize(), ArmISA::PMU::serialize(), AlphaISA::TLB::serialize(), EtherSwitch::Interface::PortFifo::serialize(), PowerISA::TLB::serialize(), CpuLocalTimer::serialize(), GenericTimer::serialize(), PacketFifo::serialize(), PciDevice::serialize(), CxxConfigManager::serialize(), Sinic::Device::serialize(), ArmISA::TLB::serialize(), Pl390::serialize(), DistIface::RecvScheduler::serialize(), serialize(), VirtIODeviceBase::serialize(), PollQueue::service(), H3BloomFilter::set(), MultiGrainBloomFilter::set(), NonCountingBloomFilter::set(), BlockBloomFilter::set(), MultiBitSelBloomFilter::set(), WaitClass::set(), BaseDynInst< Impl >::Result::set(), CheckerCPU::Result::set(), Wavefront::setContext(), OutputDirectory::setDirectory(), Logger::setLevel(), DistEtherLink::Link::setLocalInt(), WriteMask::setMask(), ArmISA::PMU::setMiscReg(), setpgidFunc(), X86ISA::Interrupts::setReg(), PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), AlphaISA::RemoteGDB::AlphaGdbRegCache::setRegs(), SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs(), ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), EtherLink::Link::setRxInt(), setThreadArea32Func(), EtherLink::Link::setTxInt(), Shader::Shader(), Topology::shortest_path_to_node(), X86ISA::I82094AA::signalInterrupt(), signbit(), simd_modified_imm(), SimpleNetwork::SimpleNetwork(), simulate(), NetDest::smallestElement(), Set::smallestElement(), Pl390::softInt(), LinearSystem::solve(), DefaultDecode< Impl >::sortInsts(), DefaultRename< Impl >::sortInsts(), DefaultIEW< Impl >::sortInsts(), DefaultDecode< Impl >::squash(), DefaultRename< Impl >::squash(), LTAGE::squash(), StaticInst::srcRegIdx(), MemChecker::startRead(), MathExprPowerModel::startup(), LinuxArmSystem::startup(), MinorCPU::startup(), ThermalModel::startup(), MemChecker::startWrite(), Minor::LSQ::StoreBuffer::step(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::StInst(), StorageMap::StorageMap(), StoreSet::StoreSet(), Stats::ConstVectorNode< T >::str(), SubBlock::SubBlock(), DefaultIEW< Impl >::takeOverFrom(), TCPIface::TCPIface(), testAndRead(), testAndReadMask(), testAndWrite(), tgkillFunc(), Trace::ArmNativeTrace::ThreadState::ThreadState(), AtomicSimpleCPU::tick(), DefaultFetch< Impl >::tick(), TimeBuffer< DecodeStruct >::TimeBuffer(), TLBCoalescer::TLBCoalescer(), DistIface::toggleSync(), Topology::Topology(), LinearEquation::toStr(), Stats::VectorBase< Vector, StatStor >::total(), Stats::VectorProxy< Stat >::total(), Stats::Vector2dBase< Vector2d, StatStor >::total(), Stats::ConstVectorNode< T >::total(), Stats::UnaryNode< Op >::total(), Stats::BinaryNode< Op >::total(), Stats::SumNode< Op >::total(), MinorCPU::totalInsts(), FullO3CPU< Impl >::totalInsts(), MinorCPU::totalOps(), FullO3CPU< Impl >::totalOps(), PseudoLRUPolicy::touch(), TournamentBP::TournamentBP(), AbstractMemory::trackLoadLocked(), TrafficGen::transition(), ElfObject::tryFile(), RubyPort::trySendRetries(), Tsunami::Tsunami(), TsunamiPChip::TsunamiPChip(), EtherBus::txDone(), PersistentTable::typeOfSmallest(), CxxConfigManager::unRename(), NoMaliGpu::unserialize(), SymbolTable::unserialize(), ArmISA::PMU::unserialize(), X86ISA::I82094AA::unserialize(), AlphaISA::TLB::unserialize(), EtherSwitch::Interface::PortFifo::unserialize(), PowerISA::TLB::unserialize(), DVFSHandler::unserialize(), CpuLocalTimer::unserialize(), GenericTimer::unserialize(), PacketFifo::unserialize(), PciDevice::unserialize(), FuncPageTable::unserialize(), PhysicalMemory::unserialize(), Sinic::Device::unserialize(), ArmISA::TLB::unserialize(), Pl390::unserialize(), DistIface::RecvScheduler::unserialize(), unserialize(), VirtIODeviceBase::unserialize(), Serializable::unserializeGlobals(), NonCountingBloomFilter::unset(), BlockBloomFilter::unset(), LTAGE::update(), Trace::X86NativeTrace::ThreadState::update(), Trace::ArmNativeTrace::ThreadState::update(), ArmISA::PMU::updateAllCounters(), ComputeUnit::updateEvents(), LTAGE::updateGHist(), LTAGE::updateHistories(), VGic::updateIntState(), ArmV8KvmCPU::updateKvmState(), updateKvmStateFPUCommon(), BaseO3DynInst< Impl >::updateMiscRegs(), TimerTable::updateNext(), TLBCoalescer::updatePhysAddresses(), VectorRegisterFile::updateResources(), Pl390::updateRunPri(), ArmV8KvmCPU::updateThreadContext(), updateThreadContextFPUCommon(), X86KvmCPU::updateThreadContextMSRs(), StackDistCalc::updateTree(), utimesFunc(), ActivityRecorder::validate(), Checker< Impl >::validateExecution(), DefaultRename< Impl >::validInsts(), DefaultIEW< Impl >::validInstsFromRename(), Stats::VectorBase< Vector, StatStor >::value(), VirtQueue::VirtQueue(), Stats::Text::visit(), ArmISA::VldMultOp::VldMultOp(), ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp::VstMultOp(), ArmISA::VstMultOp64::VstMultOp64(), ArmISA::VstSingleOp::VstSingleOp(), ArmISA::VstSingleOp64::VstSingleOp64(), MemDepUnit< MemDepPred, Impl >::wakeDependents(), MultiLevelPageTable< ISAOps >::walk(), Wavefront::Wavefront(), VIPERCoalescer::wbL1(), WeightedLRUPolicy::WeightedLRUPolicy(), CowDiskImage::write(), GpuDispatcher::write(), VirtQueue::VirtRing< struct vring_used_elem >::write(), CowDiskImage::writeback(), DefaultIEW< Impl >::writebackInsts(), Sequencer::writeCallback(), GPUCoalescer::writeCallback(), TraceCPU::ElasticDataGen::GraphNode::writeElementAsTrace(), X86ISA::writeMemAtomic(), X86ISA::writeMemTiming(), X86ISA::IntelMP::FloatingPointer::writeOut(), X86ISA::IntelMP::ConfigTable::writeOut(), X86ISA::SMBios::SMBiosTable::writeOut(), writeOutString(), X86ISA::E820Table::writeTo(), VGic::writeVCpu(), writevFunc(), PixelConverter::writeWord(), X86ISA::X86MicroopBase::X86MicroopBase(), Stats::DataWrapVec2d< Derived, Vector2dInfoProxy >::ysubname(), Stats::DataWrapVec2d< Derived, Vector2dInfoProxy >::ysubnames(), Stats::VectorBase< Vector, StatStor >::zero(), Stats::Vector2dBase< Vector2d, StatStor >::zero(), Stats::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::zero(), Stats::Formula::zero(), AbstractReplacementPolicy::~AbstractReplacementPolicy(), BaseGlobalEvent::~BaseGlobalEvent(), BrigObject::~BrigObject(), CacheMemory::~CacheMemory(), CallbackQueue::~CallbackQueue(), CheckTable::~CheckTable(), ComputeUnit::~ComputeUnit(), CowDiskImage::~CowDiskImage(), CpuEvent::~CpuEvent(), DirectoryMemory::~DirectoryMemory(), Minor::Execute::~Execute(), FUPool::~FUPool(), IniFile::~IniFile(), MemDepUnit< MemDepPred, Impl >::MemDepEntry::~MemDepEntry(), PollQueue::~PollQueue(), RubyDirectedTester::~RubyDirectedTester(), RubyTester::~RubyTester(), Minor::LSQ::SplitDataRequest::~SplitDataRequest(), TimeBuffer< DecodeStruct >::~TimeBuffer(), Stats::Vector2dBase< Vector2d, StatStor >::~Vector2dBase(), Stats::VectorBase< Vector, StatStor >::~VectorBase(), Stats::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::~VectorDistBase(), and WeightedLRUPolicy::~WeightedLRUPolicy().

ArmISA::iCacheLineSize

Definition at line 1812 of file miscregs.hh.

Bitfield<7> ArmISA::idc

Definition at line 1619 of file miscregs.hh.

Bitfield<15> ArmISA::ide

Definition at line 1625 of file miscregs.hh.

Referenced by IGbE::TxDescCache::pktComplete().

Bitfield< 25 > ArmISA::il

Definition at line 1372 of file miscregs.hh.

Bitfield<7, 0> ArmISA::imm

Definition at line 137 of file types.hh.

Referenced by PowerISA::IntImmOp::generateDisassembly(), ArmISA::MemoryImm64::generateDisassembly(), ArmISA::MemoryDImm64::generateDisassembly(), ArmISA::MemoryDImmEx64::generateDisassembly(), ArmISA::MemoryPreIndex64::generateDisassembly(), ArmISA::MemoryPostIndex64::generateDisassembly(), ArmISA::PredIntOp::generateDisassembly(), and ArmISA::MemoryLiteral64::generateDisassembly().

Bitfield<15, 0> ArmISA::imm16

Definition at line 1839 of file miscregs.hh.

Bitfield<11, 0> ArmISA::immed11_0

Definition at line 141 of file types.hh.

Bitfield<23, 0> ArmISA::immed23_0

Definition at line 151 of file types.hh.

Bitfield<7, 0> ArmISA::immed7_0

Definition at line 142 of file types.hh.

Bitfield<11, 8> ArmISA::immedHi11_8

Definition at line 144 of file types.hh.

Bitfield<3, 0> ArmISA::immedLo3_0

Definition at line 145 of file types.hh.

Bitfield<4> ArmISA::imo

Definition at line 1478 of file miscregs.hh.

uint32_t ArmISA::instBits

Definition at line 92 of file types.hh.

Bitfield<23> ArmISA::interptCtrlPresent

Definition at line 1805 of file miscregs.hh.

const IntRegMap ArmISA::IntReg64Map

Initial value:

= {
    INTREG_R0,      INTREG_R1,      INTREG_R2,      INTREG_R3,
    INTREG_R4,      INTREG_R5,      INTREG_R6,      INTREG_R7,
    INTREG_R8_USR,  INTREG_R9_USR,  INTREG_R10_USR, INTREG_R11_USR,
    INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R13_HYP,
    INTREG_R14_IRQ, INTREG_R13_IRQ, INTREG_R14_SVC, INTREG_R13_SVC,
    INTREG_R14_ABT, INTREG_R13_ABT, INTREG_R14_UND, INTREG_R13_UND,
    INTREG_R8_FIQ,  INTREG_R9_FIQ,  INTREG_R10_FIQ, INTREG_R11_FIQ,
    INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_ZERO
}

Definition at line 306 of file intregs.hh.

Referenced by ArmISA::ISA::updateRegMap(), and ArmV8KvmCPU::updateThreadContext().

const IntRegMap ArmISA::IntRegAbtMap

Initial value:

= {
    INTREG_R0_ABT,  INTREG_R1_ABT,  INTREG_R2_ABT,  INTREG_R3_ABT,
    INTREG_R4_ABT,  INTREG_R5_ABT,  INTREG_R6_ABT,  INTREG_R7_ABT,
    INTREG_R8_ABT,  INTREG_R9_ABT,  INTREG_R10_ABT, INTREG_R11_ABT,
    INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
}

Definition at line 389 of file intregs.hh.

Referenced by INTREG_ABT(), and ArmISA::ISA::updateRegMap().

const IntRegMap ArmISA::IntRegFiqMap

Initial value:

= {
    INTREG_R0_FIQ,  INTREG_R1_FIQ,  INTREG_R2_FIQ,  INTREG_R3_FIQ,
    INTREG_R4_FIQ,  INTREG_R5_FIQ,  INTREG_R6_FIQ,  INTREG_R7_FIQ,
    INTREG_R8_FIQ,  INTREG_R9_FIQ,  INTREG_R10_FIQ, INTREG_R11_FIQ,
    INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
}

Definition at line 443 of file intregs.hh.

Referenced by INTREG_FIQ(), and ArmISA::ISA::updateRegMap().

const IntRegMap ArmISA::IntRegHypMap

Initial value:

= {
    INTREG_R0_HYP,  INTREG_R1_HYP,  INTREG_R2_HYP,  INTREG_R3_HYP,
    INTREG_R4_HYP,  INTREG_R5_HYP,  INTREG_R6_HYP,  INTREG_R7_HYP,
    INTREG_R8_HYP,  INTREG_R9_HYP,  INTREG_R10_HYP, INTREG_R11_HYP,
    INTREG_R12_HYP, INTREG_R13_HYP, INTREG_R14_HYP, INTREG_R15_HYP,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
}

Definition at line 335 of file intregs.hh.

Referenced by INTREG_HYP(), and ArmISA::ISA::updateRegMap().

const IntRegMap ArmISA::IntRegIrqMap

Initial value:

= {
    INTREG_R0_IRQ,  INTREG_R1_IRQ,  INTREG_R2_IRQ,  INTREG_R3_IRQ,
    INTREG_R4_IRQ,  INTREG_R5_IRQ,  INTREG_R6_IRQ,  INTREG_R7_IRQ,
    INTREG_R8_IRQ,  INTREG_R9_IRQ,  INTREG_R10_IRQ, INTREG_R11_IRQ,
    INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
}

Definition at line 425 of file intregs.hh.

Referenced by INTREG_IRQ(), and ArmISA::ISA::updateRegMap().

const IntRegMap ArmISA::IntRegMonMap

Initial value:

= {
    INTREG_R0_MON,  INTREG_R1_MON,  INTREG_R2_MON,  INTREG_R3_MON,
    INTREG_R4_MON,  INTREG_R5_MON,  INTREG_R6_MON,  INTREG_R7_MON,
    INTREG_R8_MON,  INTREG_R9_MON,  INTREG_R10_MON, INTREG_R11_MON,
    INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
}

Definition at line 371 of file intregs.hh.

Referenced by INTREG_MON(), and ArmISA::ISA::updateRegMap().

const unsigned ArmISA::intRegsPerMode = NUM_INTREGS

static

Definition at line 461 of file intregs.hh.

Referenced by flattenIntRegModeIndex(), and intRegInMode().

const IntRegMap ArmISA::IntRegSvcMap

Initial value:

= {
    INTREG_R0_SVC,  INTREG_R1_SVC,  INTREG_R2_SVC,  INTREG_R3_SVC,
    INTREG_R4_SVC,  INTREG_R5_SVC,  INTREG_R6_SVC,  INTREG_R7_SVC,
    INTREG_R8_SVC,  INTREG_R9_SVC,  INTREG_R10_SVC, INTREG_R11_SVC,
    INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
}

Definition at line 353 of file intregs.hh.

Referenced by INTREG_SVC(), and ArmISA::ISA::updateRegMap().

const IntRegMap ArmISA::IntRegUndMap

Initial value:

= {
    INTREG_R0_UND,  INTREG_R1_UND,  INTREG_R2_UND,  INTREG_R3_UND,
    INTREG_R4_UND,  INTREG_R5_UND,  INTREG_R6_UND,  INTREG_R7_UND,
    INTREG_R8_UND,  INTREG_R9_UND,  INTREG_R10_UND, INTREG_R11_UND,
    INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
}

Definition at line 407 of file intregs.hh.

Referenced by INTREG_UND(), and ArmISA::ISA::updateRegMap().

const IntRegMap ArmISA::IntRegUsrMap

Initial value:

= {
    INTREG_R0_USR,  INTREG_R1_USR,  INTREG_R2_USR,  INTREG_R3_USR,
    INTREG_R4_USR,  INTREG_R5_USR,  INTREG_R6_USR,  INTREG_R7_USR,
    INTREG_R8_USR,  INTREG_R9_USR,  INTREG_R10_USR, INTREG_R11_USR,
    INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
}

Definition at line 317 of file intregs.hh.

Referenced by INTREG_USR(), and ArmISA::ISA::updateRegMap().

Bitfield<8> ArmISA::ioe

Definition at line 1620 of file miscregs.hh.

Bitfield< 34, 32 > ArmISA::ips

Definition at line 1694 of file miscregs.hh.

ArmISA::ir0

Definition at line 1771 of file miscregs.hh.

Bitfield<3,2> ArmISA::ir1

Definition at line 1772 of file miscregs.hh.

Bitfield<5,4> ArmISA::ir2

Definition at line 1773 of file miscregs.hh.

Bitfield<7,6> ArmISA::ir3

Definition at line 1774 of file miscregs.hh.

Bitfield<9,8> ArmISA::ir4

Definition at line 1775 of file miscregs.hh.

Bitfield<11,10> ArmISA::ir5

Definition at line 1776 of file miscregs.hh.

Bitfield<13,12> ArmISA::ir6

Definition at line 1777 of file miscregs.hh.

Bitfield<15,14> ArmISA::ir7

Definition at line 1778 of file miscregs.hh.

Bitfield< 9, 8 > ArmISA::irgn0

Definition at line 1683 of file miscregs.hh.

Bitfield< 25, 24 > ArmISA::irgn1

Definition at line 1690 of file miscregs.hh.

Bitfield<1> ArmISA::irq

Definition at line 1520 of file miscregs.hh.

Referenced by KvmVM::setIRQLine().

Bitfield<32> ArmISA::isMisc

Definition at line 90 of file types.hh.

Bitfield<26, 25> ArmISA::it1

Definition at line 1368 of file miscregs.hh.

Bitfield<15, 10> ArmISA::it2

Definition at line 1374 of file miscregs.hh.

Bitfield<7> ArmISA::itd

Definition at line 1565 of file miscregs.hh.

Referenced by getRestoredITBits().

Bitfield<55, 48> ArmISA::itstate

Definition at line 75 of file types.hh.

Referenced by EndBitUnion().

Bitfield<55, 52> ArmISA::itstateCond

Definition at line 76 of file types.hh.

Bitfield<51, 48> ArmISA::itstateMask

Definition at line 77 of file types.hh.

Bitfield<4> ArmISA::ixc

Definition at line 1618 of file miscregs.hh.

Bitfield<12> ArmISA::ixe

Definition at line 1624 of file miscregs.hh.

Bitfield<24> ArmISA::j

Definition at line 1369 of file miscregs.hh.

Referenced by AbstractReplacementPolicy::AbstractReplacementPolicy(), DRAMCtrl::activateBank(), Histogram::add(), ScheduleStage::arbitrate(), BaseSetAssoc::BaseSetAssoc(), Set::broadcast(), FALRU::check(), SwitchAllocator::check_for_wakeup(), MipsISA::ISA::clear(), SwitchAllocator::clear_request_vector(), Profiler::collateStats(), Router::collateStats(), GarnetNetwork::collateStats(), MemChecker::completeRead(), BaseSetAssoc::computeStats(), ComputeUnit::ComputeUnit(), LdsState::countBankConflicts(), Topology::createLinks(), DRAMCtrl::doDRAMAccess(), ObjectMatch::domatch(), Trace::Logger::dump(), dumpFpuCommon(), FetchUnit::exec(), FetchStage::exec(), ScheduleStage::exec(), Topology::extend_shortest_path(), FALRU::FALRU(), FetchStage::FetchStage(), Minor::FUPipeline::FUPipeline(), FUPool::FUPool(), NetDest::getAllDest(), Prefetcher::getPrefetchEntry(), SwitchAllocator::init(), FetchUnit::init(), FetchStage::init(), ScheduleStage::init(), ComputeUnit::init(), ClDriver::ioctl(), ComputeUnit::isDone(), GPUCoalescer::issueRequest(), EcoffObject::loadLocalSymbols(), ArmISA::MacroVFPMemOp::MacroVFPMemOp(), DRAMCtrl::minBankPrep(), TrafficGen::parseConfig(), NetDest::print(), CacheMemory::print(), BaseSetAssoc::print(), printSorted(), SimpleDisk::read(), TraceCPU::ElasticDataGen::InputStream::read(), Wavefront::ready(), ComputeUnit::ReadyWorkgroup(), CacheMemory::recordCacheContents(), Sequencer::regStats(), Profiler::regStats(), GPUCoalescer::regStats(), System::regStats(), BaseXBar::regStats(), Sequencer::resetStats(), Router::resetStats(), GPUCoalescer::resetStats(), InputUnit::resetStats(), ScheduleStage::ScheduleStage(), NetDest::smallestElement(), LTAGE::update(), ArmV8KvmCPU::updateKvmState(), ArmV8KvmCPU::updateThreadContext(), Stats::Text::visit(), WeightedLRUPolicy::WeightedLRUPolicy(), CacheMemory::~CacheMemory(), ComputeUnit::~ComputeUnit(), Shader::~Shader(), and System::~System().

Bitfield<15,14> ArmISA::l1IndexPolicy

Definition at line 1814 of file miscregs.hh.

Bitfield<31> ArmISA::l2rstDISABLE_monitor

Definition at line 1808 of file miscregs.hh.

Bitfield<18, 16> ArmISA::len

Definition at line 1626 of file miscregs.hh.

Referenced by GPUCoalescer::atomicCallback(), VncServer::checkProtocolVersion(), BaseRemoteGDB::cmd_clr_hw_bkpt(), BaseRemoteGDB::cmd_mem_r(), BaseRemoteGDB::cmd_mem_w(), BaseRemoteGDB::cmd_set_hw_bkpt(), AtagCmdline::cmdline(), GPUCoalescer::completeHitCallback(), GPUCoalescer::completeIssue(), createObjectFile(), Terminal::data(), DMASequencer::dataCallback(), Trace::Logger::dump(), cp::Print::end_args(), ArmISA::ArmStaticInst::extendReg64(), Net::Ip6Hdr::extensionLength(), fallocateFunc(), WriteMask::getMask(), GPUCoalescer::hitCallback(), PseudoInst::initParam(), DMASequencer::makeRequest(), Net::IpHdr::options(), Net::TcpHdr::options(), CircleBuf< char >::peek(), Printk(), cp::Print::process(), BrigObject::processDirectives(), VirtQueue::produceDescriptor(), CircleBuf< char >::read(), PseudoInst::readfile(), BaseRemoteGDB::recv(), EtherTapStub::recvReal(), ComputeUnit::DataPort::recvReqRetry(), ComputeUnit::SQCPort::recvReqRetry(), ComputeUnit::DTLBPort::recvReqRetry(), ComputeUnit::ITLBPort::recvReqRetry(), PacketFifo::reserve(), VncServer::sendError(), EtherTapStub::sendReal(), EtherTapBase::sendSimulated(), WriteMask::setMask(), KvmVM::setUserMemoryRegion(), to_lower(), DmaReadFifo::tryGet(), VirtIOConsole::TermRecvQueue::trySend(), CircleBuf< char >::write(), and PseudoInst::writefile().

Bitfield<20> ArmISA::loadOp

Definition at line 132 of file types.hh.

Bitfield< 11 > ArmISA::lpae

Definition at line 1606 of file miscregs.hh.

Bitfield<11, 8> ArmISA::ltcoproc

Definition at line 207 of file types.hh.

Bitfield<11, 8> ArmISA::ltopcode11_8

Definition at line 201 of file types.hh.

Bitfield<15> ArmISA::ltopcode15

Definition at line 200 of file types.hh.

Bitfield<4> ArmISA::ltopcode4

Definition at line 204 of file types.hh.

Bitfield<7, 4> ArmISA::ltopcode7_4

Definition at line 203 of file types.hh.

Bitfield<7, 6> ArmISA::ltopcode7_6

Definition at line 202 of file types.hh.

Bitfield<11, 8> ArmISA::ltrd

Definition at line 206 of file types.hh.

Bitfield<0> ArmISA::m

Definition at line 1577 of file miscregs.hh.

Referenced by PhysicalMemory::access(), SrcClockDomain::clockPeriod(), RealViewOsc::clockPeriod(), PhysicalMemory::createBackingStore(), MessageBuffer::delayHead(), LocalMemPipeline::exec(), GlobalMemPipeline::exec(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::execute(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::execute(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::execute(), NetworkInterface::flitisizeMessage(), PhysicalMemory::functionalAccess(), init_drain(), init_net(), init_range(), init_serialize(), HsailISA::Call::MagicAtomicNRAddGlobalU32Reg(), HsailISA::Call::MagicAtomicNRAddGroupU32Reg(), HsailISA::Call::MagicLoadGlobalU32Reg(), pybind_init_event(), pybind_init_pyobject(), pybind_init_stats(), Stats::pythonDump(), Stats::pythonReset(), MessageBuffer::reanalyzeList(), PybindSimObjectResolver::resolveSimObject(), PhysicalMemory::serialize(), DistEtherLink::TxLink::setDistInt(), DistEtherLink::RxLink::setDistInt(), ArmISA::TLB::setMMU(), ArmISA::TableWalker::setMMU(), KvmVM::setUserMemoryRegion(), Topology::shortest_path_to_node(), RealViewOsc::startup(), ComputeUnit::StartWorkgroup(), stattest_init_pybind(), PhysicalMemory::unserialize(), DerivedClockDomain::updateClockPeriod(), Gicv2m::write(), and BaseXBar::~BaseXBar().

Bitfield<15, 8> ArmISA::m5Func

Definition at line 161 of file types.hh.

const int ArmISA::MachineBytes = 4

Definition at line 102 of file isa_traits.hh.

Referenced by getArgument().

Bitfield<3, 0> ArmISA::mask

Definition at line 64 of file types.hh.

Referenced by ArmProcess::argsInit(), BiModeBP::BiModeBP(), bitRemove(), bitSelect(), SparcISA::buildPstateMask(), CopyEngine::CopyEngineChannel::channelWrite(), ArmISA::TLB::checkPermissions(), ArmISA::TLB::checkPermissions64(), ArmISA::ArmStaticInst::cpsrWriteByInstr(), GenericPciHost::decodeAddress(), SparcISA::doNormalFault(), SparcISA::doREDFault(), EndBitUnion(), HsailISA::Call::execPseudoInst(), HsailISA::LdaInst< DestDataType, AddrOperandType >::execute(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::execute(), HsailISA::Ret::execute(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::execute(), ArmISA::ArmStaticInst::extendReg64(), findParity(), findZero(), fixFpDFpSDest(), fixFpSFpDDest(), SparcISA::getHyperVector(), SparcISA::getPrivVector(), MultiBitSelBloomFilter::hash_bitsel(), H3BloomFilter::hash_H3(), DMASequencer::init(), PowerISA::PowerStaticInst::insertCRField(), PowerISA::IntRotateOp::IntRotateOp(), HsailISA::Call::MagicJoinWFBar(), HsailISA::Call::MagicMaskLower(), HsailISA::Call::MagicMaskUpper(), HsailISA::Call::MagicMostSigBroadcast(), HsailISA::Call::MagicMostSigThread(), HsailISA::Call::MagicPanic(), HsailISA::Call::MagicPrefixSum(), HsailISA::Call::MagicPrintLane(), HsailISA::Call::MagicPrintLane64(), HsailISA::Call::MagicPrintWF32(), HsailISA::Call::MagicPrintWF32ID(), HsailISA::Call::MagicPrintWF64(), HsailISA::Call::MagicPrintWFFloat(), HsailISA::Call::MagicPrintWFID64(), HsailISA::Call::MagicReduction(), HsailISA::Call::MagicWaitWFBar(), HsailISA::Call::MagicXactCasLd(), SparcISA::TLB::MakeTsbPtr(), maskHighOrderBits(), maskLowOrderBits(), mul62x62(), ArmSystem::physAddrMask(), Printk(), SparcISA::ISA::processHSTickCompare(), SparcISA::ISA::processSTickCompare(), ArmISA::TableWalker::processWalkAArch64(), purifyTaggedAddr(), IGbE::read(), ArmISA::ISA::readMiscReg(), ArmISA::ISA::readMiscRegNoEffect(), Iob::receiveDeviceInterrupt(), UFSHostDevice::requestHandler(), roundDown(), roundUp(), Iob::serialize(), SparcISA::ISA::setFSReg(), Pl011::setInterrupts(), HDLcd::setInterrupts(), ArmISA::ISA::setMiscReg(), ArmISA::ArmStaticInst::shiftReg64(), ArmISA::ArmStaticInst::spsrWriteByInstr(), ArmISA::Interrupts::takeInt(), ArmISA::ISA::tlbiVA(), TournamentBP::TournamentBP(), SparcISA::PageTableEntry::translate(), ArmISA::TLB::translateFs(), ArmISA::TLB::translateSe(), Iob::unserialize(), ArmISA::TlbEntry::updateAttributes(), vcvtFpFpH(), vcvtFpHFp(), vfpFpToFixed(), vfpSFixedToFpD(), vfpSFixedToFpS(), X86ISA::vtophys(), IGbE::write(), and Pl390::writeDistributor().

const int ArmISA::Max_Reg_Index = Misc_Reg_Base + NumMiscRegs

Definition at line 116 of file registers.hh.

const int ArmISA::MaxInstSrcRegs

Initial value:

= ArmISAInst::MaxInstDestRegs +
    ArmISAInst::MaxInstSrcRegs

Definition at line 56 of file registers.hh.

Referenced by TraceCPU::ElasticDataGen::InputStream::read(), and BaseDynInst< Impl >::renamedSrcRegIdx().

const unsigned ArmISA::MaxPhysAddrRange = 48

Definition at line 97 of file isa_traits.hh.

Referenced by ArmISA::TableWalker::checkAddrSizeFaultAArch64(), and ArmISA::TableWalker::doLongDescriptor().

Bitfield<24, 20> ArmISA::mediaOpcode

Definition at line 98 of file types.hh.

const int ArmISA::Misc_Reg_Base = CC_Reg_Base + NumCCRegs

Definition at line 115 of file registers.hh.

Bitfield<7, 4> ArmISA::miscOpcode

Definition at line 110 of file types.hh.

std::bitset< NUM_MISCREG_INFOS > ArmISA::miscRegInfo

Definition at line 131 of file miscregs.cc.

Referenced by canReadAArch64SysReg(), canReadCoprocReg(), canWriteAArch64SysReg(), canWriteCoprocReg(), ArmISA::ISA::flattenMiscIndex(), flattenMiscRegNsBanked(), ArmISA::ISA::getMiscIndices(), ArmV8KvmCPU::getSysRegMap(), preUnflattenMiscReg(), ArmISA::ISA::readMiscReg(), and ArmISA::ISA::setMiscReg().

const char* const ArmISA::miscRegName[]

Definition at line 739 of file miscregs.hh.

Referenced by ArmV8KvmCPU::dump(), ArmKvmCPU::dumpKvmStateCoProc(), ArmKvmCPU::dumpKvmStateCore(), ArmKvmCPU::dumpKvmStateVFP(), getMiscRegName(), ArmV8KvmCPU::getSysRegMap(), ArmISA::ArmStaticInst::printReg(), Minor::printRegName(), ArmISA::DummyISADevice::readMiscReg(), ArmISA::PMU::readMiscReg(), ArmISA::ISA::readMiscReg(), GenericTimer::readMiscReg(), ArmISA::PMU::readMiscRegInt(), ArmISA::DummyISADevice::setMiscReg(), ArmISA::PMU::setMiscReg(), ArmISA::ISA::setMiscReg(), GenericTimer::setMiscReg(), ArmKvmCPU::updateKvmStateCoProc(), ArmKvmCPU::updateKvmStateVFP(), ArmKvmCPU::updateTCStateCoProc(), and ArmKvmCPU::updateTCStateVFP().

Bitfield<4, 0> ArmISA::mode

Definition at line 1385 of file miscregs.hh.

Referenced by accessFunc(), chmodFunc(), OutputDirectory::create(), decodeMrsMsrBankedReg(), X86ISA::EndBitUnion(), fallocateFunc(), fchmodFunc(), flattenIntRegModeIndex(), fplibCompare(), fplibConvert(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), ArmISA::FpRegImmOp::FpRegImmOp(), ArmISA::FpRegRegImmOp::FpRegRegImmOp(), ArmISA::FpRegRegOp::FpRegRegOp(), ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp(), ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp(), ArmISA::FpRegRegRegOp::FpRegRegRegOp(), ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp(), ArmISA::RfeOp::generateDisassembly(), ArmISA::SrsOp::generateDisassembly(), X86ISA::GpuTLB::handleFuncTranslationReturn(), X86ISA::GpuTLB::handleTranslationReturn(), illegalExceptionReturn(), TimingSimpleCPU::initiateMemRead(), BaseDynInst< Impl >::initiateTranslation(), X86ISA::Walker::WalkerState::initState(), ArmISA::SupervisorCall::invoke(), ArmISA::ArmFault::invoke64(), mkdirFunc(), RawDiskImage::open(), OutputDirectory::open(), openImpl(), X86ISA::Walker::WalkerState::pageFault(), TrafficGen::parseConfig(), X86ISA::Walker::WalkerState::recvPacket(), X86ISA::I8259::serialize(), System::setMemoryMode(), ArmISA::ISA::setMiscReg(), X86ISA::Walker::WalkerState::stepWalk(), X86ISA::TLB::translate(), X86ISA::GpuTLB::translate(), AlphaISA::TLB::translateData(), X86ISA::I8259::unserialize(), vcvtFpFpH(), X86ISA::I8259::write(), and TimingSimpleCPU::writeMem().

ArmISA::n

Definition at line 1636 of file miscregs.hh.

Referenced by DVFSHandler::clkPeriodAtPerfLevel(), ThermalModel::doStep(), CxxConfigManager::findObject(), ThermalModel::getTemp(), ClDriver::ioctl(), isPowerOf2(), isPrime(), ArmISA::TableWalker::LongDescriptor::paddr(), MathExpr::parse(), ArmISA::TableWalker::pendingChange(), power(), prevPrime(), Printk(), StackDistCalc::printStack(), ArmISA::TableWalker::processWalkLPAE(), PowerISA::IntRotateOp::rotateValue(), Stats::DistBase< Distribution, DistStor >::sample(), Stats::DistProxy< Stat >::sample(), Stats::SparseHistBase< SparseHistogram, SparseHistStor >::sample(), ThermalDomain::setNode(), ThermalReference::setNode(), ThermalModel::startup(), testPredicate(), and DVFSHandler::voltageAtPerfLevel().

Bitfield<6> ArmISA::nEt

Definition at line 1515 of file miscregs.hh.

Bitfield<27> ArmISA::nmfi

Definition at line 1528 of file miscregs.hh.

const ExtMachInst ArmISA::NoopMachInst = 0x01E320F000ULL

Definition at line 100 of file isa_traits.hh.

Bitfield<24> ArmISA::nos0

Definition at line 1760 of file miscregs.hh.

Bitfield<25> ArmISA::nos1

Definition at line 1761 of file miscregs.hh.

Bitfield<26> ArmISA::nos2

Definition at line 1762 of file miscregs.hh.

Bitfield<27> ArmISA::nos3

Definition at line 1763 of file miscregs.hh.

Bitfield<28> ArmISA::nos4

Definition at line 1764 of file miscregs.hh.

Bitfield<29> ArmISA::nos5

Definition at line 1765 of file miscregs.hh.

Bitfield<30> ArmISA::nos6

Definition at line 1766 of file miscregs.hh.

Bitfield<31> ArmISA::nos7

Definition at line 1767 of file miscregs.hh.

const Addr ArmISA::NPtePage = ULL(1) << NPtePageShift

Definition at line 76 of file isa_traits.hh.

const Addr ArmISA::NPtePageShift = PageShift - PteShift

Definition at line 75 of file isa_traits.hh.

Bitfield< 9 > ArmISA::ns

Definition at line 1521 of file miscregs.hh.

Referenced by flattenMiscRegNsBanked(), illegalExceptionReturn(), and ArmISA::TLB::insert().

Bitfield<18> ArmISA::ns0

Definition at line 1758 of file miscregs.hh.

Bitfield<19> ArmISA::ns1

Definition at line 1759 of file miscregs.hh.

Bitfield<15> ArmISA::nsasedis

Definition at line 1488 of file miscregs.hh.

Bitfield<14> ArmISA::nsd32dis

Definition at line 1489 of file miscregs.hh.

Bitfield<18> ArmISA::ntwe

Definition at line 1545 of file miscregs.hh.

Bitfield<16> ArmISA::ntwi

Definition at line 1548 of file miscregs.hh.

const int ArmISA::NumArgumentRegs = 4

Definition at line 95 of file registers.hh.

Referenced by AlphaISA::getArgument(), SparcISA::getArgument(), getArgument(), X86ISA::X86_64Process::getSyscallArg(), X86ISA::I386Process::getSyscallArg(), X86ISA::X86_64Process::setSyscallArg(), and X86ISA::I386Process::setSyscallArg().

const int ArmISA::NumArgumentRegs64 = 8

Definition at line 96 of file registers.hh.

const int ArmISA::NumCCRegs = NUM_CCREGS

Definition at line 84 of file registers.hh.

Referenced by copyRegs().

Bitfield<25,24> ArmISA::numCPUs

Definition at line 1806 of file miscregs.hh.

Referenced by AlphaBackdoor::read(), and AlphaBackdoor::Access::unserialize().

const int ArmISA::NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs

Definition at line 83 of file registers.hh.

Referenced by copyRegs().

const int ArmISA::NumFloatSpecialRegs = 32

Definition at line 80 of file registers.hh.

const int ArmISA::NumFloatV7ArchRegs = 64

Definition at line 78 of file registers.hh.

Referenced by ArmISA::MacroVFPMemOp::MacroVFPMemOp(), Trace::ArmNativeTrace::ThreadState::update(), ArmISA::VldMultOp::VldMultOp(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VstMultOp::VstMultOp(), and ArmISA::VstSingleOp::VstSingleOp().

const int ArmISA::NumFloatV8ArchRegs = 128

Definition at line 79 of file registers.hh.

Referenced by ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp64::VstMultOp64(), and ArmISA::VstSingleOp64::VstSingleOp64().

const int ArmISA::NumIntArchRegs = NUM_ARCH_INTREGS

Definition at line 76 of file registers.hh.

const int ArmISA::NumIntRegs = NUM_INTREGS

Definition at line 82 of file registers.hh.

Referenced by copyRegs().

const int ArmISA::NumMiscRegs = NUM_MISCREGS

Definition at line 85 of file registers.hh.

Referenced by copyRegs(), ArmISA::ISA::readMiscRegNoEffect(), ArmISA::ISA::serialize(), ArmISA::ISA::setMiscRegNoEffect(), and ArmISA::ISA::unserialize().

ArmISA::nz

Definition at line 1364 of file miscregs.hh.

Bitfield<2> ArmISA::ofc

Definition at line 1616 of file miscregs.hh.

Bitfield<10> ArmISA::ofe

Definition at line 1622 of file miscregs.hh.

Bitfield<23, 0> ArmISA::offset

Definition at line 149 of file types.hh.

Referenced by _llseekFunc(), IniFile::Section::add(), IniFile::add(), DtbObject::addBootCmdLine(), ArmISA::VfpMacroOp::addStride(), StorageSpace::addSymbol(), TraceCPU::ElasticDataGen::adjustInitTraceOffset(), BaseXBar::calcPacketTiming(), AddrOperandBase::calcUniformBase(), VirtDescriptor::chainRead(), VirtDescriptor::chainWrite(), Packet::checkFunctional(), Cache::cmpAndSwap(), Linux::ThreadInfo::curTaskInfo(), Linux::ThreadInfo::curTaskMm(), Linux::ThreadInfo::curTaskName(), Linux::ThreadInfo::curTaskPID(), Linux::ThreadInfo::curTaskStart(), Linux::ThreadInfo::curTaskTGID(), DMASequencer::dataCallback(), GenericPciHost::decodeAddress(), AddrOperandBase::disassemble(), IdeController::EndBitUnion(), fallocateFunc(), findRegDataType(), DtbObject::findReleaseAddr(), ArmISA::MemoryReg64::generateDisassembly(), BlockBloomFilter::get_index(), SubBlock::getByte(), DataBlock::getData(), DataBlock::getDataMod(), ArmFreebsdProcessBits::SyscallTable::getDesc(), ArmLinuxProcessBits::SyscallTable::getDesc(), BaseKvmCPU::getGuestData(), handlePseudoInst(), RegAddrOperand< RegOperandType >::init(), NoRegAddrOperand::init(), LinuxArmSystem::initState(), X86System::initState(), SparcISA::ISA::installGlobals(), SparcISA::ISA::installWindow(), SubBlock::internalMergeFrom(), SubBlock::internalMergeTo(), ElfObject::loadSomeSymbols(), ArmISA::MacroVFPMemOp::MacroVFPMemOp(), DMASequencer::makeRequest(), UFSHostDevice::manageWriteTransfer(), mmapImpl(), CowDiskImage::open(), VPtr< T >::operator+(), VPtr< T >::operator+=(), Stats::Vector2dBase< Vector2d, StatStor >::operator[](), AddrOperandBase::parseAddr(), WriteMask::performAtomic(), pwrite64Func(), PciVirtIO::read(), Gicv2m::read(), VirtIOBlock::read(), GpuDispatcher::read(), IdeController::readConfig(), PciDevice::readConfig(), DRAMCtrl::recvTimingReq(), regIdxToClass(), RangeAddrMapper::remapAddr(), Net::TcpPtr::set(), Net::UdpPtr::set(), SubBlock::setByte(), split_first(), split_last(), Intel8254Timer::Counter::startup(), WriteMask::test(), MemTest::tick(), AlphaISA::TLB::translateData(), AlphaISA::TLB::translateInst(), Intel8254Timer::Counter::unserialize(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VstSingleOp::VstSingleOp(), PciVirtIO::write(), Gicv2m::write(), VirtIOBlock::write(), GpuDispatcher::write(), Intel8254Timer::Counter::write(), IdeController::writeConfig(), PciDevice::writeConfig(), NSGigE::writeConfig(), IGbE::writeConfig(), and Pl390::writeDistributor().

Bitfield<7,5> ArmISA::opc2

Definition at line 111 of file types.hh.

Referenced by ArmKvmCPU::decodeCoProcReg(), mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), and mcrrMrrc15TrapToHyp().

Bitfield<24, 21> ArmISA::opcode

Definition at line 97 of file types.hh.

Referenced by HsailISA::BrnInstBase< TargetType >::generateDisassembly(), HsailISA::CbrInstBase< TargetType >::generateDisassembly(), HsailISA::LdaInst< DestDataType, AddrOperandType >::generateDisassembly(), HsailISA::BrInstBase< TargetType >::generateDisassembly(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::generateDisassembly(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::generateDisassembly(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::generateDisassembly(), and X86ISA::Decoder::processOpcode().

Bitfield<15> ArmISA::opcode15

Definition at line 109 of file types.hh.

Bitfield<15, 12> ArmISA::opcode15_12

Definition at line 108 of file types.hh.

Bitfield<18> ArmISA::opcode18

Definition at line 107 of file types.hh.

Bitfield<19> ArmISA::opcode19

Definition at line 106 of file types.hh.

Bitfield<19, 16> ArmISA::opcode19_16

Definition at line 105 of file types.hh.

Bitfield<20> ArmISA::opcode20

Definition at line 103 of file types.hh.

Bitfield<22> ArmISA::opcode22

Definition at line 104 of file types.hh.

Bitfield<23, 20> ArmISA::opcode23_20

Definition at line 101 of file types.hh.

Bitfield<23, 21> ArmISA::opcode23_21

Definition at line 102 of file types.hh.

Bitfield<24> ArmISA::opcode24

Definition at line 99 of file types.hh.

Bitfield<24, 23> ArmISA::opcode24_23

Definition at line 100 of file types.hh.

Bitfield<4> ArmISA::opcode4

Definition at line 114 of file types.hh.

Bitfield<6> ArmISA::opcode6

Definition at line 113 of file types.hh.

Bitfield<7> ArmISA::opcode7

Definition at line 112 of file types.hh.

Bitfield<17,16> ArmISA::or0

Definition at line 1779 of file miscregs.hh.

Bitfield<19,18> ArmISA::or1

Definition at line 1780 of file miscregs.hh.

Bitfield<21,20> ArmISA::or2

Definition at line 1781 of file miscregs.hh.

Bitfield<23,22> ArmISA::or3

Definition at line 1782 of file miscregs.hh.

Bitfield<25,24> ArmISA::or4

Definition at line 1783 of file miscregs.hh.

Bitfield<27,26> ArmISA::or5

Definition at line 1784 of file miscregs.hh.

Bitfield<29,28> ArmISA::or6

Definition at line 1785 of file miscregs.hh.

Bitfield<31,30> ArmISA::or7

Definition at line 1786 of file miscregs.hh.

Bitfield< 11, 10 > ArmISA::orgn0

Definition at line 1684 of file miscregs.hh.

Bitfield< 27, 26 > ArmISA::orgn1

Definition at line 1691 of file miscregs.hh.

Bitfield<39, 12> ArmISA::pa

Definition at line 1829 of file miscregs.hh.

Referenced by ArmISA::TableWalker::LongDescriptor::nextDescAddr(), and ArmISA::TLB::translateFs().

const unsigned ArmISA::PABits = 32

Definition at line 87 of file isa_traits.hh.

const Addr ArmISA::PAddrImplMask = (ULL(1) << PABits) - 1

Definition at line 94 of file isa_traits.hh.

const Addr ArmISA::Page_Mask = ~(PageBytes - 1)

Definition at line 65 of file isa_traits.hh.

const Addr ArmISA::PageBytes = ULL(1) << PageShift

Definition at line 64 of file isa_traits.hh.

Referenced by ArmISA::RemoteGDB::acc(), ArmProcess::argsInit(), roundPage(), and truncPage().

const Addr ArmISA::PageOffset = PageBytes - 1

Definition at line 66 of file isa_traits.hh.

Referenced by VAddrOffset().

const Addr ArmISA::PageShift = 12

Definition at line 63 of file isa_traits.hh.

Referenced by ArmISA::TlbEntry::pageStart(), ArmISA::TlbEntry::updateVaddr(), and VAddrVPN().

const int ArmISA::PCReg = INTREG_PC

Definition at line 104 of file registers.hh.

Referenced by ArmISA::ArmStaticInst::printReg().

Bitfield<4> ArmISA::pd0

Definition at line 1678 of file miscregs.hh.

Bitfield<5> ArmISA::pd1

Definition at line 1679 of file miscregs.hh.

ArmISA::physAddrRange64 = 32

Definition at line 240 of file isa.cc.

Referenced by if().

Bitfield<31,8> ArmISA::procid

Definition at line 1791 of file miscregs.hh.

Bitfield< 18, 16 > ArmISA::ps

Definition at line 1701 of file miscregs.hh.

Referenced by ArmISA::TableWalker::processWalkAArch64().

Bitfield<22> ArmISA::psruser

Definition at line 130 of file types.hh.

const Addr ArmISA::PteMask = NPtePage - 1

Definition at line 77 of file isa_traits.hh.

Referenced by PteAddr().

const Addr ArmISA::PteShift = 3

Definition at line 74 of file isa_traits.hh.

Referenced by PteAddr().

Bitfield<2> ArmISA::ptw

Definition at line 1480 of file miscregs.hh.

ArmISA::pubwl

Definition at line 135 of file types.hh.

Bitfield<24, 20> ArmISA::punwl

Definition at line 159 of file types.hh.

Bitfield<27> ArmISA::q

Definition at line 1367 of file miscregs.hh.

Referenced by curEventQueue(), BaseGlobalEvent::deschedule(), StatTest::init(), GpuDispatcher::notifyWgCompl(), pybind_init_event(), PhysRegFile::readFloatReg(), recipEstimate(), and Event::setWhen().

Bitfield<27> ArmISA::qc

Definition at line 1632 of file miscregs.hh.

Bitfield<18> ArmISA::rao2

Definition at line 1547 of file miscregs.hh.

Bitfield<16> ArmISA::rao3

Definition at line 1550 of file miscregs.hh.

Bitfield<6, 3> ArmISA::rao4

Definition at line 1567 of file miscregs.hh.

Bitfield<31, 28> ArmISA::raz

Definition at line 1672 of file miscregs.hh.

Bitfield<13,4> ArmISA::raz_13_4

Definition at line 1813 of file miscregs.hh.

Bitfield<28> ArmISA::raz_28

Definition at line 1818 of file miscregs.hh.

Bitfield<15, 12> ArmISA::rd

Definition at line 119 of file types.hh.

Referenced by Printk().

const uint8_t ArmISA::recip_sqrt_estimate[256]

static

Initial value:

= {
    255, 253, 251, 249, 247, 245, 243, 242, 240, 238, 236, 234, 233, 231, 229, 228,
    226, 224, 223, 221, 219, 218, 216, 215, 213, 212, 210, 209, 207, 206, 204, 203,
    201, 200, 198, 197, 196, 194, 193, 192, 190, 189, 188, 186, 185, 184, 183, 181,
    180, 179, 178, 176, 175, 174, 173, 172, 170, 169, 168, 167, 166, 165, 164, 163,
    162, 160, 159, 158, 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146,
    145, 144, 143, 142, 141, 140, 140, 139, 138, 137, 136, 135, 134, 133, 132, 131,
    131, 130, 129, 128, 127, 126, 126, 125, 124, 123, 122, 121, 121, 120, 119, 118,
    118, 117, 116, 115, 114, 114, 113, 112, 111, 111, 110, 109, 109, 108, 107, 106,
    105, 104, 103, 101, 100,  99,  97,  96,  95,  93,  92,  91,  90,  88,  87,  86,
    85,  84,  82,  81,  80,  79,  78,  77,  76,  75,  74,  72,  71,  70,  69,  68,
    67,  66,  65,  64,  63,  62,  61,  60,  60,  59,  58,  57,  56,  55,  54,  53,
    52,  51,  51,  50,  49,  48,  47,  46,  46,  45,  44,  43,  42,  42,  41,  40,
    39,  38,  38,  37,  36,  35,  35,  34,  33,  33,  32,  31,  30,  30,  29,  28,
    28,  27,  26,  26,  25,  24,  24,  23,  22,  22,  21,  20,  20,  19,  19,  18,
    17,  17,  16,  16,  15,  14,  14,  13,  13,  12,  11,  11,  10,  10,   9,   9,
    8,   8,   7,   6,   6,   5,   5,   4,   4,   3,   3,   2,   2,   1,   1,   0
}

Definition at line 2310 of file fplib.cc.

Referenced by fplibRSqrtEstimate().

Bitfield<15, 0> ArmISA::regList

Definition at line 147 of file types.hh.

Bitfield<23, 22> ArmISA::res0_23_22

Definition at line 1370 of file miscregs.hh.

Bitfield<13, 12> ArmISA::res1_13_12_el2

Definition at line 1845 of file miscregs.hh.

Bitfield<9, 0> ArmISA::res1_9_0_el2

Definition at line 1847 of file miscregs.hh.

Bitfield<20,13> ArmISA::reserved_20_13

Definition at line 1802 of file miscregs.hh.

Bitfield<22> ArmISA::reserved_22

Definition at line 1804 of file miscregs.hh.

Bitfield<30,26> ArmISA::reserved_30_26

Definition at line 1807 of file miscregs.hh.

Bitfield<4,3> ArmISA::reserved_4_3

Definition at line 1796 of file miscregs.hh.

const int ArmISA::ReturnAddressReg = INTREG_LR

Definition at line 103 of file registers.hh.

Referenced by ArmISA::ArmStaticInst::printReg(), and skipFunction().

const int ArmISA::ReturnValueReg = 0

Definition at line 92 of file registers.hh.

const int ArmISA::ReturnValueReg1 = 1

Definition at line 93 of file registers.hh.

const int ArmISA::ReturnValueReg2 = 2

Definition at line 94 of file registers.hh.

Bitfield<19> ArmISA::rfr

Definition at line 1487 of file miscregs.hh.

Bitfield<3, 0> ArmISA::rm

Definition at line 123 of file types.hh.

Referenced by m5_fegetround().

Bitfield<23, 22> ArmISA::rMode

Definition at line 1628 of file miscregs.hh.

Referenced by vcvtFpFpH().

Bitfield<19, 16> ArmISA::rn

Definition at line 118 of file types.hh.

Referenced by ArmISA::VldMultOp::VldMultOp(), ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp::VstMultOp(), ArmISA::VstMultOp64::VstMultOp64(), ArmISA::VstSingleOp::VstSingleOp(), and ArmISA::VstSingleOp64::VstSingleOp64().

Bitfield<11, 8> ArmISA::rotate

Definition at line 139 of file types.hh.

Referenced by ArmISA::PredIntOp::generateDisassembly().

Bitfield<31, 28> ArmISA::roundingModes

Definition at line 1661 of file miscregs.hh.

Bitfield<14> ArmISA::rr

Definition at line 1553 of file miscregs.hh.

Bitfield< 11, 8 > ArmISA::rs

Definition at line 1560 of file miscregs.hh.

Referenced by Switch::addOutPort(), GarnetNetwork::collateStats(), RubyPort::MemSlavePort::hitCallback(), Sequencer::hitCallback(), IGbE::TxDescCache::pktComplete(), RubyPort::MemSlavePort::recvFunctional(), RubyPort::MemSlavePort::recvTimingReq(), and Stats::BinaryNode< Op >::size().

Bitfield<29, 28> ArmISA::rsvd

Definition at line 1596 of file miscregs.hh.

Bitfield<15, 12> ArmISA::rt

Definition at line 120 of file types.hh.

Referenced by mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), and mcrrMrrc15TrapToHyp().

Bitfield< 10 > ArmISA::rw

Definition at line 1449 of file miscregs.hh.

Referenced by Pl111::pixelConverter().

Bitfield<4> ArmISA::s

Definition at line 1738 of file miscregs.hh.

Referenced by IniFile::add(), StridePrefetcher::PCTable::allocateNewContext(), atomic_read(), atomic_write(), Stats::VectorBase< Vector, StatStor >::doInit(), Stats::VectorDistBase< VectorAverageDeviation, AvgSampleStor >::doInit(), BaseDynInst< Impl >::dump(), Stats::VectorInfo::enable(), Stats::VectorDistInfo::enable(), EndBitUnion(), ControlFlowInfo::findPostDominators(), FUPool::FUPool(), main(), ArmISA::TableWalker::memAttrs(), parseParam(), MSHR::TargetList::print(), CacheBlk::print(), Printk(), AbstractController::queueMemoryRead(), AbstractController::queueMemoryWrite(), AbstractController::queueMemoryWritePartial(), quote(), recipEstimate(), recipSqrtEstimate(), BaseXBar::recvRangeChange(), AbstractController::recvTimingResp(), EventQueue::replaceHead(), SyscallReturn::retry(), TCPIface::sendCmd(), PhysicalMemory::serialize(), Trace::InstRecord::setMem(), AbstractCacheEntry::setSetIndex(), KvmVM::setSystem(), AbstractCacheEntry::setWayIndex(), SimpleNetwork::SimpleNetwork(), split_first(), split_last(), to_bool(), BaseXBar::~BaseXBar(), StridePrefetcher::PCTable::~PCTable(), and PhysicalMemory::~PhysicalMemory().

Bitfield<3> ArmISA::sa

Definition at line 1574 of file miscregs.hh.

Referenced by SPAlignmentCheckEnabled().

Bitfield<4> ArmISA::sa0

Definition at line 1572 of file miscregs.hh.

Referenced by SPAlignmentCheckEnabled().

ArmISA::sataRAMLatency

Definition at line 1795 of file miscregs.hh.

Bitfield<7> ArmISA::scd

Definition at line 1513 of file miscregs.hh.

Bitfield<8> ArmISA::sed

Definition at line 1562 of file miscregs.hh.

ArmISA::sel

Definition at line 1823 of file miscregs.hh.

Bitfield<33> ArmISA::sevenAndFour

Definition at line 89 of file types.hh.

Bitfield<20> ArmISA::sField

Definition at line 117 of file types.hh.

Bitfield<8, 7> ArmISA::sh

Definition at line 1832 of file miscregs.hh.

Referenced by PowerISA::IntShiftOp::generateDisassembly(), PowerISA::IntRotateOp::generateDisassembly(), ArmISA::TableWalker::memAttrsAArch64(), and ArmISA::TableWalker::memAttrsLPAE().

Bitfield< 13, 12 > ArmISA::sh0

Definition at line 1685 of file miscregs.hh.

Bitfield< 29, 28 > ArmISA::sh1

Definition at line 1692 of file miscregs.hh.

Referenced by StatTest::init(), and StatTest::run().

Bitfield<6, 5> ArmISA::shift

Definition at line 122 of file types.hh.

Referenced by MipsISA::bitrev(), divideFromConf(), findCarry(), findOverflow(), fp128_normalise(), fp16_normalise(), fp32_normalise(), fp64_normalise(), MipsISA::getCondCode(), Ps2::keySymToPs2(), lsl128(), lsr128(), and X86ISA::X86MicroopBase::X86MicroopBase().

Bitfield<11, 7> ArmISA::shiftSize

Definition at line 121 of file types.hh.

Bitfield<27, 24> ArmISA::shortVectors

Definition at line 1660 of file miscregs.hh.

Bitfield<9> ArmISA::sif

Definition at line 1511 of file miscregs.hh.

Bitfield<7, 4> ArmISA::singlePrecision

Definition at line 1655 of file miscregs.hh.

Bitfield<7, 6> ArmISA::sl0

Definition at line 1740 of file miscregs.hh.

Bitfield<7> ArmISA::smd

Definition at line 1514 of file miscregs.hh.

Bitfield<0> ArmISA::sp

Definition at line 1386 of file miscregs.hh.

Referenced by RiscvProcess::argsInit(), Linux::ThreadInfo::curThreadInfo(), StorageMap::findSymbol(), Sparc32Process::flushWindows(), Sparc64Process::flushWindows(), AlphaISA::getArgument(), SparcISA::getArgument(), getArgument(), SparcISA::SpillNNormal::invoke(), SparcISA::FillNNormal::invoke(), SparcISA::TrapInstruction::invoke(), and ArmISA::ISA::setMiscReg().

Bitfield<23, 20> ArmISA::squareRoot

Definition at line 1659 of file miscregs.hh.

Bitfield<21> ArmISA::ss

Definition at line 1371 of file miscregs.hh.

Referenced by GPUCoalescer::completeHitCallback(), X86ISA::X86FaultBase::describe(), X86ISA::PageFault::describe(), PowerISA::MiscOp::generateDisassembly(), MrsOp::generateDisassembly(), ArmISA::SysDC64::generateDisassembly(), RegRegImmImmOp64::generateDisassembly(), ArmISA::DataXImmOp::generateDisassembly(), PowerISA::CondLogicOp::generateDisassembly(), ArmISA::BranchImm64::generateDisassembly(), ArmISA::Swap::generateDisassembly(), PowerISA::PowerStaticInst::generateDisassembly(), X86ISA::X86StaticInst::generateDisassembly(), ArmISA::DataXImmOnlyOp::generateDisassembly(), RegRegRegImmOp64::generateDisassembly(), ArmISA::BranchImmCond64::generateDisassembly(), PowerISA::CondMoveOp::generateDisassembly(), MsrImmOp::generateDisassembly(), PowerISA::MemDispOp::generateDisassembly(), ArmISA::BranchReg64::generateDisassembly(), ArmISA::DataXSRegOp::generateDisassembly(), PowerISA::BranchPCRel::generateDisassembly(), PowerISA::IntOp::generateDisassembly(), MsrRegOp::generateDisassembly(), ArmISA::BranchRet64::generateDisassembly(), ArmISA::DataXERegOp::generateDisassembly(), MrrcOp::generateDisassembly(), X86ISA::X86MicroopBase::generateDisassembly(), PowerISA::IntImmOp::generateDisassembly(), ArmISA::BranchEret64::generateDisassembly(), PowerISA::BranchNonPCRel::generateDisassembly(), ArmISA::DataX1RegOp::generateDisassembly(), ArmISA::RfeOp::generateDisassembly(), McrrOp::generateDisassembly(), PowerISA::IntShiftOp::generateDisassembly(), ArmISA::BranchImmReg64::generateDisassembly(), ArmISA::MemoryImm64::generateDisassembly(), ArmISA::DataX1RegImmOp::generateDisassembly(), ImmOp::generateDisassembly(), PowerISA::FloatOp::generateDisassembly(), ArmISA::MemoryDImm64::generateDisassembly(), ArmISA::DataX1Reg2ImmOp::generateDisassembly(), RegImmOp::generateDisassembly(), ArmISA::BranchImmImmReg64::generateDisassembly(), ArmISA::SrsOp::generateDisassembly(), ArmISA::DataX2RegOp::generateDisassembly(), ArmISA::MemoryDImmEx64::generateDisassembly(), PowerISA::IntRotateOp::generateDisassembly(), RegRegOp::generateDisassembly(), ArmISA::MemoryPreIndex64::generateDisassembly(), ArmISA::DataX2RegImmOp::generateDisassembly(), RegImmRegOp::generateDisassembly(), ArmISA::ArmStaticInst::generateDisassembly(), ArmISA::MemoryPostIndex64::generateDisassembly(), ArmISA::DataX3RegOp::generateDisassembly(), PowerISA::BranchPCRelCond::generateDisassembly(), RegRegRegImmOp::generateDisassembly(), ArmISA::MemoryReg64::generateDisassembly(), ArmISA::DataXCondCompImmOp::generateDisassembly(), ArmISA::MemoryRaw64::generateDisassembly(), RegRegRegRegOp::generateDisassembly(), ArmISA::PredImmOp::generateDisassembly(), PowerISA::BranchNonPCRelCond::generateDisassembly(), ArmISA::DataXCondCompRegOp::generateDisassembly(), ArmISA::MemoryEx64::generateDisassembly(), RegRegRegOp::generateDisassembly(), ArmISA::PredIntOp::generateDisassembly(), ArmISA::MemoryLiteral64::generateDisassembly(), ArmISA::DataXCondSelOp::generateDisassembly(), PowerISA::BranchRegCond::generateDisassembly(), RegRegImmOp::generateDisassembly(), ArmISA::DataImmOp::generateDisassembly(), ArmISA::MicroSetPCCPSR::generateDisassembly(), MiscRegRegImmOp::generateDisassembly(), ArmISA::DataRegOp::generateDisassembly(), ArmISA::MicroIntMov::generateDisassembly(), RegMiscRegImmOp::generateDisassembly(), ArmISA::DataRegRegOp::generateDisassembly(), ArmISA::MicroIntImmOp::generateDisassembly(), RegImmImmOp::generateDisassembly(), ArmISA::MicroIntImmXOp::generateDisassembly(), RegRegImmImmOp::generateDisassembly(), ArmISA::PredMacroOp::generateDisassembly(), ArmISA::MicroIntOp::generateDisassembly(), RegImmRegShiftOp::generateDisassembly(), ArmISA::MicroIntRegXOp::generateDisassembly(), ArmISA::MemoryOffset< Base >::generateDisassembly(), ArmISA::MicroMemOp::generateDisassembly(), ArmISA::MicroMemPairOp::generateDisassembly(), ArmISA::MemoryPreIndex< Base >::generateDisassembly(), ArmISA::MemoryPostIndex< Base >::generateDisassembly(), ArmISA::FpCondCompRegOp::generateDisassembly(), ArmISA::FpCondSelOp::generateDisassembly(), ArmISA::FpRegRegOp::generateDisassembly(), ArmISA::FpRegImmOp::generateDisassembly(), ArmISA::FpRegRegImmOp::generateDisassembly(), ArmISA::FpRegRegRegOp::generateDisassembly(), ArmISA::FpRegRegRegCondOp::generateDisassembly(), ArmISA::FpRegRegRegRegOp::generateDisassembly(), ArmISA::FpRegRegRegImmOp::generateDisassembly(), BaseKvmCPU::getAndFormatOneReg(), LdsState::getDynInstr(), Linux::DebugPrintkEvent::process(), LdsState::process(), and ThermalDomain::setSubSystem().

Bitfield<11> ArmISA::st

Definition at line 1509 of file miscregs.hh.

Referenced by __stattest(), OutputDirectory::isFile(), EcoffObject::loadLocalSymbols(), and EventQueue::name().

const int ArmISA::StackPointerReg = INTREG_SP

Definition at line 102 of file registers.hh.

Referenced by getArgument(), and ArmISA::ArmStaticInst::printReg().

Bitfield<5, 0> ArmISA::status

Definition at line 1604 of file miscregs.hh.

Referenced by MipsISA::MipsFaultBase::base(), MipsISA::Interrupts::checkInterrupts(), MipsISA::ISA::configCP(), FullO3CPU< Impl >::drainResume(), IdeController::EndBitUnion(), exitImpl(), MipsISA::forkThread(), MipsISA::Interrupts::getInterrupt(), BaseDynInst< Impl >::initVars(), MipsISA::ResetFault::invoke(), ComputeUnit::isSimdDone(), Sequencer::makeRequest(), GPUCoalescer::makeRequest(), System::numRunningContexts(), MipsISA::TlbRefillFault::offset(), VirtIOBlock::RequestQueue::onNotifyDescriptor(), IGbE::RxDescCache::pktComplete(), X86ISA::PS2Mouse::processData(), Pl050::read(), ComputeUnit::ReadyWorkgroup(), ConditionRegisterState::regBusy(), VectorRegisterFile::regBusy(), VectorRegisterFile::regNxtBusy(), Sinic::Device::rxKick(), X86ISA::PS2Mouse::serialize(), Pl050::serialize(), VirtIODeviceBase::setDeviceStatus(), MipsISA::MipsFaultBase::setExceptionState(), DrainManager::tryDrain(), X86ISA::PS2Mouse::unserialize(), Pl050::unserialize(), MipsISA::updateStatusView(), MipsISA::updateTCStatusView(), MinorCPU::wakeup(), FullO3CPU< Impl >::wakeup(), and PciVirtIO::write().

Bitfield<21, 20> ArmISA::stride

Definition at line 1627 of file miscregs.hh.

Referenced by ArmISA::VfpMacroOp::addStride(), Prefetcher::initializeStream(), makeNextStrideAddress(), ArmISA::TableWalker::LongDescriptor::nextDescAddr(), ArmISA::VfpMacroOp::nextIdxs(), Prefetcher::observeMiss(), and ComputeUnit::DTLBPort::recvTimingResp().

Bitfield<29, 0> ArmISA::subArchDefined

Definition at line 1650 of file miscregs.hh.

Bitfield<10> ArmISA::sw

Definition at line 1559 of file miscregs.hh.

Referenced by for().

Bitfield<1> ArmISA::swio

Definition at line 1481 of file miscregs.hh.

const int ArmISA::SyscallNumReg = ReturnValueReg

Definition at line 108 of file registers.hh.

const int ArmISA::SyscallPseudoReturnReg = ReturnValueReg

Definition at line 109 of file registers.hh.

const int ArmISA::SyscallSuccessReg = ReturnValueReg

Definition at line 110 of file registers.hh.

ArmISA::system = dynamic_cast<ArmSystem *>(p->system)

Definition at line 226 of file isa.cc.

Referenced by BaseSimpleCPU::checkPcEventQueue(), BaseSimpleCPU::countInst(), MinorCPU::drainResume(), TimingSimpleCPU::drainResume(), exitImpl(), if(), MinorCPU::init(), ArmLinuxProcess32::initState(), MultiLevelPageTable< ISAOps >::initState(), BaseSetAssoc::insertBlock(), FullO3CPU< Impl >::insertThread(), FullO3CPU< Impl >::instDone(), Iob::Iob(), MultiLevelPageTable< ISAOps >::isUnmapped(), BaseKvmCPU::kvmRun(), MultiLevelPageTable< ISAOps >::lookup(), MultiLevelPageTable< ISAOps >::map(), BaseSimpleCPU::preExecute(), AtomicSimpleCPU::readMem(), MultiLevelPageTable< ISAOps >::remap(), CheckerCPU::setSystem(), SimpleThread::simPalCheck(), FullO3CPU< Impl >::simPalCheck(), BaseArmKvmCPU::startup(), AtomicSimpleCPU::tick(), BaseKvmCPU::tick(), MultiLevelPageTable< ISAOps >::unmap(), Checker< Impl >::verify(), BaseKvmCPU::verifyMemoryMode(), AtomicSimpleCPU::verifyMemoryMode(), TimingSimpleCPU::verifyMemoryMode(), FullO3CPU< Impl >::verifyMemoryMode(), MultiLevelPageTable< ISAOps >::walk(), and AtomicSimpleCPU::writeMem().

Bitfield<5> ArmISA::t

Definition at line 1382 of file miscregs.hh.

Referenced by WriteQueueEntry::TargetList::checkFunctional(), MSHR::TargetList::checkFunctional(), IGbE::chkInterrupt(), MSHR::TargetList::clearDownstreamPending(), SparcISA::TLB::clearUsedBits(), HDLcd::PixelPump::dumpSettings(), Packet::findNextSenderState(), Sequencer::getFirstResponseToCompletionDelayHist(), GPUCoalescer::getFirstResponseToCompletionDelayHist(), Sequencer::getForwardRequestToFirstResponseHist(), GPUCoalescer::getForwardRequestToFirstResponseHist(), Sequencer::getHitMachLatencyHist(), Sequencer::getHitTypeLatencyHist(), Sequencer::getHitTypeMachLatencyHist(), Sequencer::getIncompleteTimes(), Sequencer::getInitialToForwardDelayHist(), GPUCoalescer::getInitialToForwardDelayHist(), Sequencer::getIssueToInitialDelayHist(), GPUCoalescer::getIssueToInitialDelayHist(), Sequencer::getMissMachLatencyHist(), GPUCoalescer::getMissMachLatencyHist(), Sequencer::getMissTypeLatencyHist(), GPUCoalescer::getMissTypeLatencyHist(), Sequencer::getMissTypeMachLatencyHist(), GPUCoalescer::getMissTypeMachLatencyHist(), Sequencer::getTypeLatencyHist(), GPUCoalescer::getTypeLatencyHist(), SparcISA::TLB::lookup(), TrafficGen::parseConfig(), SparcISA::PageTableEntry::populate(), MSHR::TargetList::populateFlags(), IGbE::postInterrupt(), WriteQueueEntry::TargetList::print(), MSHR::TargetList::print(), pybind_init_core(), pybind_init_event(), RealViewTemperatureSensor::read(), SerialLink::SerialLinkSlavePort::recvTimingReq(), SerialLink::SerialLinkMasterPort::recvTimingResp(), EventQueue::replaceHead(), MSHR::TargetList::replaceUpgrades(), Consumer::scheduleEventAbsolute(), Serializable::serializeAll(), LinearSystem::solve(), timeFunc(), SerialLink::SerialLinkSlavePort::trySendTiming(), SerialLink::SerialLinkMasterPort::trySendTiming(), BaseRemoteGDB::TrapEvent::type(), and Globals::unserialize().

Bitfield<0> ArmISA::t0

Definition at line 1443 of file miscregs.hh.

Referenced by fp32_sqrt(), fp64_muladd(), and mul64x32().

ArmISA::t0sz

Definition at line 1681 of file miscregs.hh.

Bitfield<5, 0> ArmISA::t0sz64

Definition at line 1739 of file miscregs.hh.

Bitfield<1> ArmISA::t1

Definition at line 1442 of file miscregs.hh.

Referenced by ThreadContext::compare(), fp32_sqrt(), fp64_muladd(), and mul64x32().

Bitfield<10> ArmISA::t10

Definition at line 1433 of file miscregs.hh.

Bitfield<11> ArmISA::t11

Definition at line 1432 of file miscregs.hh.

Bitfield<12> ArmISA::t12

Definition at line 1431 of file miscregs.hh.

Bitfield<13> ArmISA::t13

Definition at line 1430 of file miscregs.hh.

Bitfield<15> ArmISA::t15

Definition at line 1429 of file miscregs.hh.

Bitfield< 21, 16 > ArmISA::t1sz

Definition at line 1687 of file miscregs.hh.

Bitfield<2> ArmISA::t2

Definition at line 1441 of file miscregs.hh.

Referenced by ThreadContext::compare().

Bitfield<3> ArmISA::t3

Definition at line 1440 of file miscregs.hh.

Bitfield<4> ArmISA::t4

Definition at line 1439 of file miscregs.hh.

Bitfield<5> ArmISA::t5

Definition at line 1438 of file miscregs.hh.

Bitfield<6> ArmISA::t6

Definition at line 1437 of file miscregs.hh.

Bitfield<7> ArmISA::t7

Definition at line 1436 of file miscregs.hh.

Bitfield<8> ArmISA::t8

Definition at line 1435 of file miscregs.hh.

Bitfield<9> ArmISA::t9

Definition at line 1434 of file miscregs.hh.

Bitfield<21> ArmISA::tac

Definition at line 1460 of file miscregs.hh.

Bitfield<21> ArmISA::tacr

Definition at line 1461 of file miscregs.hh.

Bitfield<8,6> ArmISA::tagRAMLatency

Definition at line 1798 of file miscregs.hh.

Bitfield<9> ArmISA::tagRAMSetup

Definition at line 1799 of file miscregs.hh.

Bitfield<12> ArmISA::tagRAMSlice

Definition at line 1801 of file miscregs.hh.

Bitfield<15> ArmISA::tase

Definition at line 1408 of file miscregs.hh.

Bitfield< 20 > ArmISA::tbi

Definition at line 1702 of file miscregs.hh.

Bitfield< 37 > ArmISA::tbi0

Definition at line 1696 of file miscregs.hh.

Bitfield< 38 > ArmISA::tbi1

Definition at line 1697 of file miscregs.hh.

Bitfield<0> ArmISA::tcp0

Definition at line 1423 of file miscregs.hh.

Bitfield<1> ArmISA::tcp1

Definition at line 1422 of file miscregs.hh.

Bitfield<10> ArmISA::tcp10

Definition at line 1412 of file miscregs.hh.

Bitfield<11> ArmISA::tcp11

Definition at line 1411 of file miscregs.hh.

Bitfield<12> ArmISA::tcp12

Definition at line 1410 of file miscregs.hh.

Bitfield<13> ArmISA::tcp13

Definition at line 1409 of file miscregs.hh.

Bitfield<2> ArmISA::tcp2

Definition at line 1421 of file miscregs.hh.

Bitfield<3> ArmISA::tcp3

Definition at line 1420 of file miscregs.hh.

Bitfield<4> ArmISA::tcp4

Definition at line 1419 of file miscregs.hh.

Bitfield<5> ArmISA::tcp5

Definition at line 1418 of file miscregs.hh.

Bitfield<6> ArmISA::tcp6

Definition at line 1417 of file miscregs.hh.

Bitfield<7> ArmISA::tcp7

Definition at line 1416 of file miscregs.hh.

Bitfield<8> ArmISA::tcp8

Definition at line 1415 of file miscregs.hh.

Bitfield<9> ArmISA::tcp9

Definition at line 1414 of file miscregs.hh.

Bitfield<9> ArmISA::tda

Definition at line 1397 of file miscregs.hh.

Bitfield<8> ArmISA::tde

Definition at line 1398 of file miscregs.hh.

Bitfield<10> ArmISA::tdosa

Definition at line 1396 of file miscregs.hh.

Bitfield<28> ArmISA::tdz

Definition at line 1452 of file miscregs.hh.

Bitfield< 10 > ArmISA::tfp

Definition at line 1413 of file miscregs.hh.

Bitfield< 15, 14 > ArmISA::tg0

Definition at line 1686 of file miscregs.hh.

Bitfield< 31, 30 > ArmISA::tg1

Definition at line 1693 of file miscregs.hh.

Bitfield<27> ArmISA::tge

Definition at line 1454 of file miscregs.hh.

Bitfield<6> ArmISA::thee

Definition at line 1568 of file miscregs.hh.

Bitfield<36> ArmISA::thumb

Definition at line 84 of file types.hh.

Referenced by EndBitUnion().

Bitfield<15> ArmISA::tid0

Definition at line 1467 of file miscregs.hh.

Bitfield<16> ArmISA::tid1

Definition at line 1466 of file miscregs.hh.

Bitfield<17> ArmISA::tid2

Definition at line 1465 of file miscregs.hh.

Bitfield<18> ArmISA::tid3

Definition at line 1464 of file miscregs.hh.

Bitfield<20> ArmISA::tidcp

Definition at line 1462 of file miscregs.hh.

Bitfield<7, 2> ArmISA::top6

Definition at line 66 of file types.hh.

Bitfield<10, 8> ArmISA::topcode10_8

Definition at line 171 of file types.hh.

Bitfield<10, 9> ArmISA::topcode10_9

Definition at line 170 of file types.hh.

Bitfield<11, 8> ArmISA::topcode11_8

Definition at line 169 of file types.hh.

Bitfield<11, 9> ArmISA::topcode11_9

Definition at line 168 of file types.hh.

Bitfield<12, 10> ArmISA::topcode12_10

Definition at line 167 of file types.hh.

Bitfield<12, 11> ArmISA::topcode12_11

Definition at line 166 of file types.hh.

Bitfield<13, 11> ArmISA::topcode13_11

Definition at line 165 of file types.hh.

Bitfield<15, 13> ArmISA::topcode15_13

Definition at line 164 of file types.hh.

Bitfield<3, 0> ArmISA::topcode3_0

Definition at line 177 of file types.hh.

Bitfield<7> ArmISA::topcode7

Definition at line 173 of file types.hh.

Bitfield<7, 4> ArmISA::topcode7_4

Definition at line 176 of file types.hh.

Bitfield<7, 5> ArmISA::topcode7_5

Definition at line 175 of file types.hh.

Bitfield<7, 6> ArmISA::topcode7_6

Definition at line 174 of file types.hh.

Bitfield<9, 6> ArmISA::topcode9_6

Definition at line 172 of file types.hh.

const int ArmISA::TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs

Definition at line 89 of file registers.hh.

Bitfield<23> ArmISA::tpc

Definition at line 1458 of file miscregs.hh.

Bitfield<6> ArmISA::tpm

Definition at line 1400 of file miscregs.hh.

Bitfield<5> ArmISA::tpmcr

Definition at line 1401 of file miscregs.hh.

Bitfield<24> ArmISA::tpu

Definition at line 1457 of file miscregs.hh.

ArmISA::tr0

Definition at line 1748 of file miscregs.hh.

Bitfield<3,2> ArmISA::tr1

Definition at line 1749 of file miscregs.hh.

Bitfield<5,4> ArmISA::tr2

Definition at line 1750 of file miscregs.hh.

Bitfield<7,6> ArmISA::tr3

Definition at line 1751 of file miscregs.hh.

Bitfield<9,8> ArmISA::tr4

Definition at line 1752 of file miscregs.hh.

Bitfield<11,10> ArmISA::tr5

Definition at line 1753 of file miscregs.hh.

Bitfield<13,12> ArmISA::tr6

Definition at line 1754 of file miscregs.hh.

Bitfield<15,14> ArmISA::tr7

Definition at line 1755 of file miscregs.hh.

Bitfield<28> ArmISA::tre

Definition at line 1527 of file miscregs.hh.

Bitfield<30> ArmISA::trvm

Definition at line 1450 of file miscregs.hh.

Bitfield<19> ArmISA::tsc

Definition at line 1463 of file miscregs.hh.

Bitfield<22> ArmISA::tsw

Definition at line 1459 of file miscregs.hh.

Bitfield< 20 > ArmISA::tta

Definition at line 1407 of file miscregs.hh.

Bitfield<16> ArmISA::ttee

Definition at line 1428 of file miscregs.hh.

Bitfield<25> ArmISA::ttlb

Definition at line 1456 of file miscregs.hh.

Bitfield<26> ArmISA::tvm

Definition at line 1455 of file miscregs.hh.

Bitfield<14> ArmISA::twe

Definition at line 1468 of file miscregs.hh.

Bitfield< 12 > ArmISA::twi

Definition at line 1469 of file miscregs.hh.

Bitfield<22> ArmISA::u

Definition at line 1537 of file miscregs.hh.

Bitfield<26> ArmISA::uci

Definition at line 1529 of file miscregs.hh.

Bitfield<15> ArmISA::uct

Definition at line 1551 of file miscregs.hh.

Bitfield<3> ArmISA::ufc

Definition at line 1617 of file miscregs.hh.

Bitfield<11> ArmISA::ufe

Definition at line 1623 of file miscregs.hh.

Bitfield<9> ArmISA::uma

Definition at line 1561 of file miscregs.hh.

int ArmISA::unflattenResultMiscReg[NUM_MISCREGS]

If the reg is a child reg of a banked set, then the parent is the last banked one in the list.

This is messy, and the wish is to eventually have the bitmap replaced with a better data structure. the preUnflatten function initializes a lookup table to speed up the search for these banked registers.

Definition at line 2071 of file miscregs.cc.

Bitfield<23> ArmISA::up

Definition at line 129 of file types.hh.

Referenced by ArmISA::MacroVFPMemOp::MacroVFPMemOp().

const Addr ArmISA::USegBase = ULL(0x0)

Definition at line 83 of file isa_traits.hh.

const Addr ArmISA::USegEnd = ULL(0x7FFFFFFF)

Definition at line 84 of file isa_traits.hh.

Bitfield<25> ArmISA::useImm

Definition at line 96 of file types.hh.

Bitfield<20> ArmISA::uwxn

Definition at line 1540 of file miscregs.hh.

Bitfield< 28 > ArmISA::v

Definition at line 1366 of file miscregs.hh.

Referenced by IniFile::Entry::appendValue(), htop9(), htov_legacy(), ArmISA::TlbEntry::match(), PerfectSwitch::operateMessageBuffer(), p9toh(), MathExpr::parse(), DistIface::RecvScheduler::resumeRecvTicks(), Packet::set(), IniFile::Entry::setValue(), testPredicate(), and vtoh_legacy().

Bitfield<8> ArmISA::va

Definition at line 1473 of file miscregs.hh.

Referenced by AlphaISA::RemoteGDB::acc(), SparcISA::TLB::demapPage(), SparcISA::TLB::doMmuRegRead(), SparcISA::TLB::doMmuRegWrite(), GenericISA::handleGenericIprRead(), GenericISA::handleGenericIprWrite(), SparcISA::TLB::insert(), SparcISA::TLB::lookup(), ArmISA::ISA::setMiscReg(), and ArmISA::ISA::tlbiVA().

const unsigned ArmISA::VABits = 32

Definition at line 86 of file isa_traits.hh.

const Addr ArmISA::VAddrImplMask = (ULL(1) << VABits) - 1

Definition at line 88 of file isa_traits.hh.

Referenced by VAddrImpl().

const Addr ArmISA::VAddrUnImplMask = ~VAddrImplMask

Definition at line 89 of file isa_traits.hh.

Bitfield<24> ArmISA::ve

Definition at line 1533 of file miscregs.hh.

Bitfield<6> ArmISA::vf

Definition at line 1476 of file miscregs.hh.

Bitfield<15, 12> ArmISA::vfpExceptionTrapping

Definition at line 1657 of file miscregs.hh.

Bitfield<27, 24> ArmISA::vfpHalfPrecision

Definition at line 1671 of file miscregs.hh.

Bitfield<7> ArmISA::vi

Definition at line 1475 of file miscregs.hh.

Bitfield<0> ArmISA::vm

Definition at line 1482 of file miscregs.hh.

Referenced by MuxingKvmGic::MuxingKvmGic().

Bitfield<8> ArmISA::vse

Definition at line 1474 of file miscregs.hh.

Bitfield< 4 > ArmISA::width

Definition at line 1383 of file miscregs.hh.

Referenced by HsailISA::BrnInstBase< TargetType >::generateDisassembly(), HsailISA::CbrInstBase< TargetType >::generateDisassembly(), HsailISA::BrInstBase< TargetType >::generateDisassembly(), ArmISA::AbortFault< T >::getFsr(), Trie< Addr, X86ISA::TlbEntry >::insert(), HsailISA::LdInstBase< MemDataType::CType, DestDataType::OperandType, AddrOperandType >::LdInstBase(), Printk(), ArmISA::ArmStaticInst::satInt(), ArmISA::ArmStaticInst::saturateOp(), VncInput::setDirty(), ArmISA::ArmStaticInst::shiftReg64(), ArmISA::ArmStaticInst::uSatInt(), and ArmISA::ArmStaticInst::uSaturateOp().

Bitfield<11> ArmISA::wnr

Definition at line 1608 of file miscregs.hh.

Bitfield<21> ArmISA::writeback

Definition at line 131 of file types.hh.

Referenced by ArmISA::PairMemOp::PairMemOp(), IGbE::TxDescCache::pktComplete(), and IGbE::DescCache< T >::wbComplete().

Bitfield<19> ArmISA::wxn

Definition at line 1544 of file miscregs.hh.

Bitfield<23> ArmISA::xp

Definition at line 1536 of file miscregs.hh.

Bitfield< 30 > ArmISA::z

Definition at line 1558 of file miscregs.hh.

Referenced by testPredicate().

const int ArmISA::ZeroReg = INTREG_ZERO

Definition at line 106 of file registers.hh.