remote_gdb.hh File Reference

#include <string>
#include "arch/riscv/registers.hh"
#include "base/remote_gdb.hh"

Go to the source code of this file.

Classes
class	RiscvISA::RemoteGDB
class	RiscvISA::RemoteGDB::RiscvGdbRegCache

Namespaces
	RiscvISA

Variables
IntReg	gpr [NumIntArchRegs]
IntReg	pc
FloatRegBits	fpr [NumFloatRegs]
MiscReg	csr_base
uint32_t	fflags
uint32_t	frm
uint32_t	fcsr
MiscReg	csr [NumMiscRegs-ExplicitCSRs]

Variable Documentation

MiscReg csr[NumMiscRegs-ExplicitCSRs]

Definition at line 98 of file remote_gdb.hh.

MiscReg csr_base

Definition at line 94 of file remote_gdb.hh.

uint32_t fcsr

Definition at line 97 of file remote_gdb.hh.

Referenced by MipsISA::genCCVector().

uint32_t fflags

Definition at line 95 of file remote_gdb.hh.

FloatRegBits fpr[NumFloatRegs]

Definition at line 92 of file remote_gdb.hh.

uint32_t frm

Definition at line 96 of file remote_gdb.hh.

IntReg gpr[NumIntArchRegs]

Definition at line 90 of file remote_gdb.hh.

IntReg pc

Definition at line 91 of file remote_gdb.hh.

Referenced by ArmProcess::argsInit(), StridePrefetcher::calculatePrefetch(), Trace::SparcNativeTrace::check(), Check::Check(), BaseSimpleCPU::checkPcEventQueue(), DefaultCommit< Impl >::commitInsts(), AlphaISA::StackTrace::decodePrologue(), PowerISA::PCDependentDisassembly::disassemble(), SparcISA::doNormalFault(), SparcISA::doREDFault(), PCEventQueue::doService(), DefaultFetch< Impl >::doSquash(), Trace::IntelTraceRecord::dump(), FunctionProfile::dump(), BaseDynInst< Impl >::dump(), ArmKvmCPU::dumpKvmStateCore(), ArmISA::EndBitUnion(), PCEventQueue::equal_range(), DecoderFaultInst::execute(), DefaultFetch< Impl >::fetch(), DefaultFetch< Impl >::fetchCacheLine(), DefaultFetch< Impl >::finishTranslation(), LTAGE::getLoop(), SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), LTAGE::gindex(), LTAGE::gtag(), SparcProcess::handleTrap(), SimpleThread::hwrei(), BaseO3DynInst< Impl >::hwrei(), TimingSimpleCPU::initiateMemRead(), BaseDynInst< Impl >::initiateMemRead(), AlphaISA::AlphaFault::invoke(), SparcISA::SparcFaultBase::invoke(), SparcISA::PowerOnReset::invoke(), ArmISA::ArmFault::invoke(), ArmISA::Reset::invoke(), SparcISA::TrapInstruction::invoke(), ArmISA::SupervisorCall::invoke(), ArmISA::FlushPipe::invoke(), ArmISA::ArmFault::invoke64(), DefaultCommit< Impl >::isDrained(), Sequencer::issueRequest(), GPUCoalescer::issueRequest(), mmapImpl(), PCEventQueue::MapCompare::operator()(), GenericISA::operator<<(), DefaultFetch< Impl >::pipelineIcacheAccesses(), BaseSimpleCPU::postExecute(), BPredUnit::predict(), LTAGE::predict(), BaseRemoteGDB::HardBreakpoint::process(), ArmISA::ISA::readMiscReg(), DefaultFetch< Impl >::resetStage(), FunctionProfile::sample(), ArmISA::ArmStaticInst::setAIWNextPC(), ArmISA::ArmStaticInst::setIWNextPC(), ArmISA::ISA::setMiscReg(), ArmISA::ArmStaticInst::setNextPC(), Request::setPC(), SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs(), Request::setVirt(), SouthBridge::SouthBridge(), DefaultCommit< Impl >::squashAll(), DefaultIEW< Impl >::squashDueToBranch(), DefaultCommit< Impl >::squashFromSquashAfter(), DefaultCommit< Impl >::squashFromTC(), DefaultCommit< Impl >::squashFromTrap(), AlphaISA::StackTrace::trace(), Trace::ExeTracerRecord::traceInst(), LTAGE::update(), BPredUnit::update(), ArmKvmCPU::updateTCStateCore(), ArmV8KvmCPU::updateThreadContext(), TimingSimpleCPU::writeMem(), and BaseDynInst< Impl >::writeMem().