RiscvISA Namespace Reference

Namespaces
	Kernel

Classes
class	Decoder
class	RiscvFault
class	UnknownInstFault
class	UnimplementedFault
class	IllegalFrmFault
class	BreakpointFault
class	SyscallFault
class	Interrupts
class	ISA
struct	VAddr
struct	PTE
struct	TlbEntry
class	RemoteGDB
class	ProcessInfo
class	StackTrace
class	TLB

Typedefs
typedef uint_fast16_t	RegIndex
typedef uint64_t	IntReg
typedef uint64_t	FloatRegBits
typedef double	FloatReg
typedef uint8_t	CCReg
typedef uint64_t	MiscReg
typedef uint32_t	MachInst
typedef uint64_t	ExtMachInst
typedef GenericISA::UPCState < MachInst >	PCState

Enumerations
enum	ExceptionCode {   INST_ADDR_MISALIGNED = 0, INST_ACCESS = 1, INST_ILLEGAL = 2, BREAKPOINT = 3,   LOAD_ADDR_MISALIGNED = 4, LOAD_ACCESS = 5, STORE_ADDR_MISALIGNED = 6, AMO_ADDR_MISALIGNED = 6,   STORE_ACCESS = 7, AMO_ACCESS = 7, ECALL_USER = 8, ECALL_SUPER = 9,   ECALL_HYPER = 10, ECALL_MACH = 11 }
enum	InterruptCode { SOFTWARE, TIMER }
enum	MiscRegIndex {   MISCREG_USTATUS = 0x000, MISCREG_UIE = 0x004, MISCREG_UTVEC = 0x005, MISCREG_USCRATCH = 0x040,   MISCREG_UEPC = 0x041, MISCREG_UCAUSE = 0x042, MISCREG_UBADADDR = 0x043, MISCREG_UIP = 0x044,   MISCREG_FFLAGS = 0x001, MISCREG_FRM = 0x002, MISCREG_FCSR = 0x003, MISCREG_CYCLE = 0xC00,   MISCREG_TIME = 0xC01, MISCREG_INSTRET = 0xC02, MISCREG_HPMCOUNTER_BASE = 0xC03, MISCREG_CYCLEH = 0xC80,   MISCREG_TIMEH = 0xC81, MISCREG_INSTRETH = 0xC82, MISCREG_HPMCOUNTERH_BASE = 0xC83, MISCREG_SSTATUS = 0x100,   MISCREG_SEDELEG = 0x102, MISCREG_SIDELEG = 0x103, MISCREG_SIE = 0x104, MISCREG_STVEC = 0x105,   MISCREG_SSCRATCH = 0x140, MISCREG_SEPC = 0x141, MISCREG_SCAUSE = 0x142, MISCREG_SBADADDR = 0x143,   MISCREG_SIP = 0x144, MISCREG_SPTBR = 0x180, MISCREG_HSTATUS = 0x200, MISCREG_HEDELEG = 0x202,   MISCREG_HIDELEG = 0x203, MISCREG_HIE = 0x204, MISCREG_HTVEC = 0x205, MISCREG_HSCRATCH = 0x240,   MISCREG_HEPC = 0x241, MISCREG_HCAUSE = 0x242, MISCREG_HBADADDR = 0x243, MISCREG_HIP = 0x244,   MISCREG_MVENDORID = 0xF11, MISCREG_MARCHID = 0xF12, MISCREG_MIMPID = 0xF13, MISCREG_MHARTID = 0xF14,   MISCREG_MSTATUS = 0x300, MISCREG_MISA = 0x301, MISCREG_MEDELEG = 0x302, MISCREG_MIDELEG = 0x303,   MISCREG_MIE = 0x304, MISCREG_MTVEC = 0x305, MISCREG_MSCRATCH = 0x340, MISCREG_MEPC = 0x341,   MISCREG_MCAUSE = 0x342, MISCREG_MBADADDR = 0x343, MISCREG_MIP = 0x344, MISCREG_MBASE = 0x380,   MISCREG_MBOUND = 0x381, MISCREG_MIBASE = 0x382, MISCREG_MIBOUND = 0x383, MISCREG_MDBASE = 0x384,   MISCREG_MDBOUND = 0x385, MISCREG_MCYCLE = 0xB00, MISCREG_MINSTRET = 0xB02, MISCREG_MHPMCOUNTER_BASE = 0xB03,   MISCREG_MUCOUNTEREN = 0x320, MISCREG_MSCOUNTEREN = 0x321, MISCREG_MHCOUNTEREN = 0x322, MISCREG_MHPMEVENT_BASE = 0x323,   MISCREG_TSELECT = 0x7A0, MISCREG_TDATA1 = 0x7A1, MISCREG_TDATA2 = 0x7A2, MISCREG_TDATA3 = 0x7A3,   MISCREG_DCSR = 0x7B0, MISCREG_DPC = 0x7B1, MISCREG_DSCRATCH = 0x7B2 }

Functions
template<class XC >
void	handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template<class XC >
void	handleLockedRead (XC *xc, Request *req)
template<class XC >
void	handleLockedSnoopHit (XC *xc)
template<class XC >
bool	handleLockedWrite (XC *xc, Request *req, Addr cacheBlockMask)
	BitUnion32 (IndexReg) Bitfield< 31 > p
	EndBitUnion (IndexReg) BitUnion32(RandomReg) Bitfield< 30
	EndBitUnion (RandomReg) BitUnion64(EntryLoReg) Bitfield< 63
	EndBitUnion (EntryLoReg) BitUnion64(ContextReg) Bitfield< 63
	EndBitUnion (ContextReg) BitUnion32(PageMaskReg) Bitfield< 28
	EndBitUnion (PageMaskReg) BitUnion32(PageGrainReg) Bitfield< 31
	EndBitUnion (PageGrainReg) BitUnion32(WiredReg) Bitfield< 30
	EndBitUnion (WiredReg) BitUnion32(HWREnaReg) Bitfield< 31
	EndBitUnion (HWREnaReg) BitUnion64(EntryHiReg) Bitfield< 63
	EndBitUnion (EntryHiReg) BitUnion32(StatusReg) SubBitUnion(cu
	EndSubBitUnion (cu) Bitfield< 27 > rp
	SubBitUnion (im, 15, 8) Bitfield< 15 > im7
	EndSubBitUnion (im) Bitfield< 7 > kx
	EndBitUnion (StatusReg) BitUnion32(IntCtlReg) Bitfield< 31
	EndBitUnion (IntCtlReg) BitUnion32(SRSCtlReg) Bitfield< 29
	EndBitUnion (SRSCtlReg) BitUnion32(SRSMapReg) Bitfield< 31
	EndBitUnion (SRSMapReg) BitUnion32(CauseReg) Bitfield< 31 > bd
	SubBitUnion (ip, 15, 8) Bitfield< 15 > ip7
	EndSubBitUnion (ip)
	EndBitUnion (CauseReg) BitUnion32(PRIdReg) Bitfield< 31
	EndBitUnion (PRIdReg) BitUnion32(EBaseReg) Bitfield< 29
	EndBitUnion (EBaseReg) BitUnion32(ConfigReg) Bitfield< 31 > m
	EndBitUnion (ConfigReg) BitUnion32(Config1Reg) Bitfield< 31 > m
	EndBitUnion (Config1Reg) BitUnion32(Config2Reg) Bitfield< 31 > m
	EndBitUnion (Config2Reg) BitUnion32(Config3Reg) Bitfield< 31 > m
	EndBitUnion (Config3Reg) BitUnion64(WatchLoReg) Bitfield< 63
	EndBitUnion (WatchLoReg) BitUnion32(WatchHiReg) Bitfield< 31 > m
	EndBitUnion (WatchHiReg) BitUnion32(PerfCntCtlReg) Bitfield< 31 > m
	EndBitUnion (PerfCntCtlReg) BitUnion32(CacheErrReg) Bitfield< 31 > er
	EndBitUnion (CacheErrReg) BitUnion32(TagLoReg) Bitfield< 31
template<typename T >
bool	isquietnan (T val)
template<>
bool	isquietnan< float > (float val)
template<>
bool	isquietnan< double > (double val)
template<typename T >
bool	issignalingnan (T val)
template<>
bool	issignalingnan< float > (float val)
template<>
bool	issignalingnan< double > (double val)
PCState	buildRetPC (const PCState &curPC, const PCState &callPC)
uint64_t	getArgument (ThreadContext *tc, int &number, uint16_t size, bool fp)
void	startupCPU (ThreadContext *tc, int cpuId)
void	copyRegs (ThreadContext *src, ThreadContext *dest)
void	skipFunction (ThreadContext *tc)
void	advancePC (PCState &pc, const StaticInstPtr &inst)
static bool	inUserMode (ThreadContext *tc)
uint64_t	getExecutingAsid (ThreadContext *tc)
void	initCPU (ThreadContext *, int cpuId)
Addr	vtophys (Addr vaddr)
Addr	vtophys (ThreadContext *tc, Addr vaddr)

Variables
const uint32_t	FloatInexact = 1 << 0
const uint32_t	FloatUnderflow = 1 << 1
const uint32_t	FloatOverflow = 1 << 2
const uint32_t	FloatDivZero = 1 << 3
const uint32_t	FloatInvalid = 1 << 4
const Addr	PageShift = 12
const Addr	PageBytes = ULL(1) << PageShift
const ExtMachInst	NoopMachInst = 0x00000013
const bool	HasUnalignedMemAcc = true
const bool	CurThreadInfoImplemented = false
const int	CurThreadInfoReg = -1
std::stack< Addr >	locked_addrs
const int	WARN_FAILURE = 10000
Bitfield< 30, 0 >	index
	random
	fill
Bitfield< 29, 6 >	pfn
Bitfield< 5, 3 >	c
Bitfield< 2 >	d
Bitfield< 1 >	v
Bitfield< 0 >	g
	pteBase
Bitfield< 22, 4 >	badVPN2
	mask
Bitfield< 12, 11 >	maskx
	aseUp
Bitfield< 29 >	elpa
Bitfield< 28 >	esp
Bitfield< 12, 8 >	aseDn
	wired
	impl
	r
Bitfield< 39, 13 >	vpn2
Bitfield< 12, 11 >	vpn2x
Bitfield< 7, 0 >	asid
Bitfield< 31 >	cu3
Bitfield< 30 >	cu2
Bitfield< 29 >	cu1
Bitfield< 28 >	cu0
Bitfield< 26 >	fr
Bitfield< 25 >	re
Bitfield< 24 >	mx
Bitfield< 23 >	px
Bitfield< 22 >	bev
Bitfield< 21 >	ts
Bitfield< 20 >	sr
Bitfield< 19 >	nmi
Bitfield< 15, 10 >	ipl
Bitfield< 14 >	im6
Bitfield< 13 >	im5
Bitfield< 12 >	im4
Bitfield< 11 >	im3
Bitfield< 10 >	im2
Bitfield< 9 >	im1
Bitfield< 8 >	im0
Bitfield< 6 >	sx
Bitfield< 5 >	ux
Bitfield< 4, 3 >	ksu
Bitfield< 4 >	um
Bitfield< 3 >	r0
Bitfield< 2 >	erl
Bitfield< 1 >	exl
Bitfield< 0 >	ie
	ipti
Bitfield< 28, 26 >	ippci
Bitfield< 9, 5 >	vs
	hss
Bitfield< 21, 18 >	eicss
Bitfield< 15, 12 >	ess
Bitfield< 9, 6 >	pss
Bitfield< 3, 0 >	css
	ssv7
Bitfield< 27, 24 >	ssv6
Bitfield< 23, 20 >	ssv5
Bitfield< 19, 16 >	ssv4
Bitfield< 15, 12 >	ssv3
Bitfield< 11, 8 >	ssv2
Bitfield< 7, 4 >	ssv1
Bitfield< 3, 0 >	ssv0
Bitfield< 30 >	ti
Bitfield< 29, 28 >	ce
Bitfield< 27 >	dc
Bitfield< 26 >	pci
Bitfield< 23 >	iv
Bitfield< 22 >	wp
Bitfield< 15, 10 >	ripl
Bitfield< 14 >	ip6
Bitfield< 13 >	ip5
Bitfield< 12 >	ip4
Bitfield< 11 >	ip3
Bitfield< 10 >	ip2
Bitfield< 9 >	ip1
Bitfield< 8 >	ip0
Bitfield< 6, 2 >	excCode
	coOp
Bitfield< 23, 16 >	coId
Bitfield< 15, 8 >	procId
Bitfield< 7, 0 >	rev
	exceptionBase
Bitfield< 9, 9 >	cpuNum
Bitfield< 30, 28 >	k23
Bitfield< 27, 25 >	ku
Bitfield< 15 >	be
Bitfield< 14, 13 >	at
Bitfield< 12, 10 >	ar
Bitfield< 9, 7 >	mt
Bitfield< 3 >	vi
Bitfield< 2, 0 >	k0
Bitfield< 30, 25 >	mmuSize
Bitfield< 24, 22 >	is
Bitfield< 21, 19 >	il
Bitfield< 18, 16 >	ia
Bitfield< 15, 13 >	ds
Bitfield< 12, 10 >	dl
Bitfield< 9, 7 >	da
Bitfield< 6 >	c2
Bitfield< 5 >	md
Bitfield< 4 >	pc
Bitfield< 3 >	wr
Bitfield< 2 >	ca
Bitfield< 1 >	ep
Bitfield< 0 >	fp
Bitfield< 30, 28 >	tu
Bitfield< 23, 20 >	tl
Bitfield< 19, 16 >	ta
Bitfield< 15, 12 >	su
Bitfield< 11, 8 >	ss
Bitfield< 7, 4 >	sl
Bitfield< 3, 0 >	sa
Bitfield< 10 >	dspp
Bitfield< 7 >	lpa
Bitfield< 6 >	veic
Bitfield< 5 >	vint
Bitfield< 4 >	sp
Bitfield< 1 >	sm
	vaddr
Bitfield< 2 >	i
Bitfield< 0 >	w
Bitfield< 10, 5 >	event
Bitfield< 3 >	u
Bitfield< 2 >	s
Bitfield< 1 >	k
Bitfield< 30 >	ec
Bitfield< 29 >	ed
Bitfield< 28 >	et
Bitfield< 27 >	es
Bitfield< 26 >	ee
Bitfield< 25 >	eb
	pTagLo
Bitfield< 7, 6 >	pState
Bitfield< 5 >	l
Bitfield< 0 >	p
const int	MaxMiscDestRegs = 1
const int	NumIntArchRegs = 32
const int	NumMicroIntRegs = 1
const int	NumIntRegs = NumIntArchRegs + NumMicroIntRegs
const int	NumFloatRegs = 32
const int	NumCCRegs = 0
const int	NumMiscRegs = 4096
const int	FP_Reg_Base = NumIntRegs
const int	CC_Reg_Base = FP_Reg_Base + NumFloatRegs
const int	Misc_Reg_Base = CC_Reg_Base + NumCCRegs
const int	Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
const int	ZeroReg = 0
const int	ReturnAddrReg = 1
const int	StackPointerReg = 2
const int	GlobalPointerReg = 3
const int	ThreadPointerReg = 4
const int	FramePointerReg = 8
const int	ReturnValueRegs [] = {10, 11}
const int	ReturnValueReg = ReturnValueRegs[0]
const int	ArgumentRegs [] = {10, 11, 12, 13, 14, 15, 16, 17}
const int	AMOTempReg = 32
const char *const	RegisterNames []
const int	SyscallNumReg = ArgumentRegs[7]
const int	SyscallArgumentRegs []
const int	SyscallPseudoReturnReg = ReturnValueRegs[0]
const int	NumHpmcounter = 29
const int	NumHpmcounterh = 29
const int	NumMhpmcounter = 29
const int	NumMhpmevent = 29
class RiscvISA::ProcessInfo	__attribute__

Typedef Documentation

typedef uint8_t RiscvISA::CCReg

Definition at line 67 of file registers.hh.

typedef uint64_t RiscvISA::ExtMachInst

Definition at line 54 of file types.hh.

typedef double RiscvISA::FloatReg

Definition at line 66 of file registers.hh.

typedef uint64_t RiscvISA::FloatRegBits

Definition at line 65 of file registers.hh.

typedef uint64_t RiscvISA::IntReg

Definition at line 64 of file registers.hh.

typedef uint32_t RiscvISA::MachInst

Definition at line 53 of file types.hh.

typedef uint64_t RiscvISA::MiscReg

Definition at line 68 of file registers.hh.

typedef GenericISA::UPCState<MachInst> RiscvISA::PCState

Definition at line 56 of file types.hh.

typedef uint_fast16_t RiscvISA::RegIndex

Definition at line 63 of file registers.hh.

Enumeration Type Documentation

enum RiscvISA::ExceptionCode

Enumerator
INST_ADDR_MISALIGNED
INST_ACCESS
INST_ILLEGAL
BREAKPOINT
LOAD_ADDR_MISALIGNED
LOAD_ACCESS
STORE_ADDR_MISALIGNED
AMO_ADDR_MISALIGNED
STORE_ACCESS
AMO_ACCESS
ECALL_USER
ECALL_SUPER
ECALL_HYPER
ECALL_MACH

Definition at line 49 of file faults.hh.

enum RiscvISA::InterruptCode

Enumerator
SOFTWARE
TIMER

Definition at line 66 of file faults.hh.

enum RiscvISA::MiscRegIndex

Enumerator
MISCREG_USTATUS
MISCREG_UIE
MISCREG_UTVEC
MISCREG_USCRATCH
MISCREG_UEPC
MISCREG_UCAUSE
MISCREG_UBADADDR
MISCREG_UIP
MISCREG_FFLAGS
MISCREG_FRM
MISCREG_FCSR
MISCREG_CYCLE
MISCREG_TIME
MISCREG_INSTRET
MISCREG_HPMCOUNTER_BASE
MISCREG_CYCLEH
MISCREG_TIMEH
MISCREG_INSTRETH
MISCREG_HPMCOUNTERH_BASE
MISCREG_SSTATUS
MISCREG_SEDELEG
MISCREG_SIDELEG
MISCREG_SIE
MISCREG_STVEC
MISCREG_SSCRATCH
MISCREG_SEPC
MISCREG_SCAUSE
MISCREG_SBADADDR
MISCREG_SIP
MISCREG_SPTBR
MISCREG_HSTATUS
MISCREG_HEDELEG
MISCREG_HIDELEG
MISCREG_HIE
MISCREG_HTVEC
MISCREG_HSCRATCH
MISCREG_HEPC
MISCREG_HCAUSE
MISCREG_HBADADDR
MISCREG_HIP
MISCREG_MVENDORID
MISCREG_MARCHID
MISCREG_MIMPID
MISCREG_MHARTID
MISCREG_MSTATUS
MISCREG_MISA
MISCREG_MEDELEG
MISCREG_MIDELEG
MISCREG_MIE
MISCREG_MTVEC
MISCREG_MSCRATCH
MISCREG_MEPC
MISCREG_MCAUSE
MISCREG_MBADADDR
MISCREG_MIP
MISCREG_MBASE
MISCREG_MBOUND
MISCREG_MIBASE
MISCREG_MIBOUND
MISCREG_MDBASE
MISCREG_MDBOUND
MISCREG_MCYCLE
MISCREG_MINSTRET
MISCREG_MHPMCOUNTER_BASE
MISCREG_MUCOUNTEREN
MISCREG_MSCOUNTEREN
MISCREG_MHCOUNTEREN
MISCREG_MHPMEVENT_BASE
MISCREG_TSELECT
MISCREG_TDATA1
MISCREG_TDATA2
MISCREG_TDATA3
MISCREG_DCSR
MISCREG_DPC
MISCREG_DSCRATCH

Definition at line 113 of file registers.hh.

Function Documentation

void RiscvISA::advancePC ( PCState &  pc, const StaticInstPtr &  inst  )

inline

Definition at line 136 of file utility.hh.

References StaticInst::advancePC().

Referenced by RiscvISA::RiscvFault::invoke().

RiscvISA::BitUnion32

(

IndexReg

)

PCState RiscvISA::buildRetPC ( const PCState &  curPC, const PCState &  callPC  )

inline

Definition at line 100 of file utility.hh.

References GenericISA::SimplePCState< MachInst >::advance(), GenericISA::SimplePCState< MachInst >::npc(), and GenericISA::SimplePCState< MachInst >::pc().

void RiscvISA::copyRegs ( ThreadContext *  src, ThreadContext *  dest  )

inline

Definition at line 119 of file utility.hh.

References i, NumIntRegs, ThreadContext::pcState(), ThreadContext::readIntReg(), and ThreadContext::setIntReg().

RiscvISA::EndBitUnion

(

IndexReg

)

RiscvISA::EndBitUnion

(

RandomReg

)

RiscvISA::EndBitUnion

(

EntryLoReg

)

RiscvISA::EndBitUnion

(

ContextReg

)

RiscvISA::EndBitUnion

(

PageMaskReg

)

RiscvISA::EndBitUnion

(

PageGrainReg

)

RiscvISA::EndBitUnion

(

WiredReg

)

RiscvISA::EndBitUnion

(

HWREnaReg

)

RiscvISA::EndBitUnion

(

EntryHiReg

)

RiscvISA::EndBitUnion

(

StatusReg

)

RiscvISA::EndBitUnion

(

IntCtlReg

)

RiscvISA::EndBitUnion

(

SRSCtlReg

)

RiscvISA::EndBitUnion

(

SRSMapReg

)

RiscvISA::EndBitUnion

(

CauseReg

)

RiscvISA::EndBitUnion

(

PRIdReg

)

RiscvISA::EndBitUnion

(

EBaseReg

)

RiscvISA::EndBitUnion

(

ConfigReg

)

RiscvISA::EndBitUnion

(

Config1Reg

)

RiscvISA::EndBitUnion

(

Config2Reg

)

RiscvISA::EndBitUnion

(

Config3Reg

)

RiscvISA::EndBitUnion

(

WatchLoReg

)

RiscvISA::EndBitUnion

(

WatchHiReg

)

RiscvISA::EndBitUnion

(

PerfCntCtlReg

)

RiscvISA::EndBitUnion

(

CacheErrReg

)

RiscvISA::EndSubBitUnion

(

cu

)

RiscvISA::EndSubBitUnion

(

im

)

RiscvISA::EndSubBitUnion

(

ip

)

uint64_t RiscvISA::getArgument ( ThreadContext *  tc, int &  number, uint16_t  size, bool  fp  )

inline

Definition at line 109 of file utility.hh.

uint64_t RiscvISA::getExecutingAsid ( ThreadContext *  tc )

inline

Definition at line 148 of file utility.hh.

template<class XC >

void RiscvISA::handleLockedRead ( XC *  xc, Request *  req  )

inline

Definition at line 85 of file locked_mem.hh.

References Request::contextId(), DPRINTF, Request::getPaddr(), and locked_addrs.

template<class XC >

void RiscvISA::handleLockedSnoop ( XC *  xc, PacketPtr  pkt, Addr  cacheBlockMask  )

inline

Definition at line 73 of file locked_mem.hh.

References DPRINTF, Packet::getAddr(), and locked_addrs.

template<class XC >

void RiscvISA::handleLockedSnoopHit ( XC *  xc )

inline

Definition at line 93 of file locked_mem.hh.

template<class XC >

bool RiscvISA::handleLockedWrite ( XC *  xc, Request *  req, Addr  cacheBlockMask  )

inline

Definition at line 97 of file locked_mem.hh.

References Request::contextId(), curTick(), DPRINTF, Request::getPaddr(), Request::isUncacheable(), locked_addrs, Request::setExtraData(), warn, and WARN_FAILURE.

void RiscvISA::initCPU ( ThreadContext *  , int  cpuId  )

inline

Definition at line 154 of file utility.hh.

References panic.

static bool RiscvISA::inUserMode ( ThreadContext *  tc )

inlinestatic

Definition at line 142 of file utility.hh.

template<typename T >

bool RiscvISA::isquietnan ( T  val )

inline

Definition at line 60 of file utility.hh.

template<>

bool RiscvISA::isquietnan< double > ( double  val )

inline

Definition at line 73 of file utility.hh.

References X86ISA::val.

template<>

bool RiscvISA::isquietnan< float > ( float  val )

inline

Definition at line 66 of file utility.hh.

References X86ISA::val.

template<typename T >

bool RiscvISA::issignalingnan ( T  val )

inline

Definition at line 80 of file utility.hh.

template<>

bool RiscvISA::issignalingnan< double > ( double  val )

inline

Definition at line 93 of file utility.hh.

References X86ISA::val.

template<>

bool RiscvISA::issignalingnan< float > ( float  val )

inline

Definition at line 86 of file utility.hh.

References X86ISA::val.

void RiscvISA::skipFunction ( ThreadContext *  tc )

inline

Definition at line 130 of file utility.hh.

References panic.

void RiscvISA::startupCPU ( ThreadContext *  tc, int  cpuId  )

inline

Definition at line 114 of file utility.hh.

RiscvISA::SubBitUnion	(	im	,
		15	,
		8
	)

RiscvISA::SubBitUnion	(	ip	,
		15	,
		8
	)

Addr RiscvISA::vtophys ( Addr  vaddr )

inline

Definition at line 49 of file vtophys.hh.

References fatal, and vaddr.

Referenced by vtophys().

Addr RiscvISA::vtophys ( ThreadContext *  tc, Addr  vaddr  )

inline

Definition at line 56 of file vtophys.hh.

References fatal, and vtophys().

Variable Documentation

class RiscvISA::ProcessInfo RiscvISA::__attribute__

const int RiscvISA::AMOTempReg = 32

Definition at line 93 of file registers.hh.

Bitfield<12, 10> RiscvISA::ar

Definition at line 224 of file pra_constants.hh.

const int RiscvISA::ArgumentRegs[] = {10, 11, 12, 13, 14, 15, 16, 17}

Definition at line 92 of file registers.hh.

Bitfield<12, 8> RiscvISA::aseDn

Definition at line 82 of file pra_constants.hh.

RiscvISA::aseUp

Definition at line 78 of file pra_constants.hh.

Bitfield< 23, 16 > RiscvISA::asid

Definition at line 101 of file pra_constants.hh.

Bitfield<14, 13> RiscvISA::at

Definition at line 223 of file pra_constants.hh.

Bitfield<22, 4> RiscvISA::badVPN2

Definition at line 66 of file pra_constants.hh.

Bitfield<15> RiscvISA::be

Definition at line 222 of file pra_constants.hh.

Bitfield<22> RiscvISA::bev

Definition at line 116 of file pra_constants.hh.

Bitfield<5, 3> RiscvISA::c

Definition at line 58 of file pra_constants.hh.

Bitfield<6> RiscvISA::c2

Definition at line 240 of file pra_constants.hh.

Bitfield<2> RiscvISA::ca

Definition at line 244 of file pra_constants.hh.

const int RiscvISA::CC_Reg_Base = FP_Reg_Base + NumFloatRegs

Definition at line 79 of file registers.hh.

Bitfield<29, 28> RiscvISA::ce

Definition at line 179 of file pra_constants.hh.

Bitfield<23, 16> RiscvISA::coId

Definition at line 204 of file pra_constants.hh.

RiscvISA::coOp

Definition at line 203 of file pra_constants.hh.

Bitfield<9, 9> RiscvISA::cpuNum

Definition at line 214 of file pra_constants.hh.

Bitfield<3, 0> RiscvISA::css

Definition at line 162 of file pra_constants.hh.

Bitfield<28> RiscvISA::cu0

Definition at line 109 of file pra_constants.hh.

Bitfield<29> RiscvISA::cu1

Definition at line 108 of file pra_constants.hh.

Bitfield<30> RiscvISA::cu2

Definition at line 107 of file pra_constants.hh.

Bitfield<31> RiscvISA::cu3

Definition at line 105 of file pra_constants.hh.

const bool RiscvISA::CurThreadInfoImplemented = false

Definition at line 71 of file isa_traits.hh.

const int RiscvISA::CurThreadInfoReg = -1

Definition at line 72 of file isa_traits.hh.

Bitfield<2> RiscvISA::d

Definition at line 59 of file pra_constants.hh.

Bitfield<9, 7> RiscvISA::da

Definition at line 239 of file pra_constants.hh.

Bitfield<27> RiscvISA::dc

Definition at line 180 of file pra_constants.hh.

Bitfield<12, 10> RiscvISA::dl

Definition at line 238 of file pra_constants.hh.

Bitfield<15, 13> RiscvISA::ds

Definition at line 237 of file pra_constants.hh.

Bitfield<10> RiscvISA::dspp

Definition at line 264 of file pra_constants.hh.

Bitfield<25> RiscvISA::eb

Definition at line 314 of file pra_constants.hh.

Bitfield<30> RiscvISA::ec

Definition at line 309 of file pra_constants.hh.

Bitfield<29> RiscvISA::ed

Definition at line 310 of file pra_constants.hh.

Bitfield<26> RiscvISA::ee

Definition at line 313 of file pra_constants.hh.

Bitfield<21, 18> RiscvISA::eicss

Definition at line 156 of file pra_constants.hh.

Bitfield<29> RiscvISA::elpa

Definition at line 79 of file pra_constants.hh.

Bitfield<1> RiscvISA::ep

Definition at line 245 of file pra_constants.hh.

Bitfield<2> RiscvISA::erl

Definition at line 139 of file pra_constants.hh.

Bitfield<27> RiscvISA::es

Definition at line 312 of file pra_constants.hh.

Bitfield<28> RiscvISA::esp

Definition at line 80 of file pra_constants.hh.

Bitfield<15, 12> RiscvISA::ess

Definition at line 158 of file pra_constants.hh.

Bitfield<28> RiscvISA::et

Definition at line 311 of file pra_constants.hh.

Bitfield<10, 5> RiscvISA::event

Definition at line 299 of file pra_constants.hh.

Bitfield<6, 2> RiscvISA::excCode

Definition at line 198 of file pra_constants.hh.

RiscvISA::exceptionBase

Definition at line 212 of file pra_constants.hh.

Bitfield< 0 > RiscvISA::exl

Definition at line 140 of file pra_constants.hh.

Bitfield< 61, 40 > RiscvISA::fill

Definition at line 56 of file pra_constants.hh.

const uint32_t RiscvISA::FloatDivZero = 1 << 3

Definition at line 46 of file faults.hh.

const uint32_t RiscvISA::FloatInexact = 1 << 0

Definition at line 43 of file faults.hh.

const uint32_t RiscvISA::FloatInvalid = 1 << 4

Definition at line 47 of file faults.hh.

const uint32_t RiscvISA::FloatOverflow = 1 << 2

Definition at line 45 of file faults.hh.

const uint32_t RiscvISA::FloatUnderflow = 1 << 1

Definition at line 44 of file faults.hh.

Bitfield<0> RiscvISA::fp

Definition at line 246 of file pra_constants.hh.

const int RiscvISA::FP_Reg_Base = NumIntRegs

Definition at line 78 of file registers.hh.

Bitfield<26> RiscvISA::fr

Definition at line 112 of file pra_constants.hh.

const int RiscvISA::FramePointerReg = 8

Definition at line 89 of file registers.hh.

Bitfield< 30 > RiscvISA::g

Definition at line 61 of file pra_constants.hh.

const int RiscvISA::GlobalPointerReg = 3

Definition at line 87 of file registers.hh.

const bool RiscvISA::HasUnalignedMemAcc = true

Definition at line 69 of file isa_traits.hh.

RiscvISA::hss

Definition at line 154 of file pra_constants.hh.

Bitfield< 2 > RiscvISA::i

Definition at line 278 of file pra_constants.hh.

Referenced by copyRegs(), RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), RiscvISA::TLB::insertAt(), RiscvISA::ISA::ISA(), RiscvISA::TLB::lookup(), RiscvISA::TLB::probeEntry(), RiscvISA::TLB::serialize(), RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs(), and RiscvISA::TLB::unserialize().

Bitfield<18, 16> RiscvISA::ia

Definition at line 236 of file pra_constants.hh.

Bitfield< 4 > RiscvISA::ie

Definition at line 141 of file pra_constants.hh.

Bitfield<21, 19> RiscvISA::il

Definition at line 235 of file pra_constants.hh.

Bitfield<8> RiscvISA::im0

Definition at line 131 of file pra_constants.hh.

Bitfield<9> RiscvISA::im1

Definition at line 130 of file pra_constants.hh.

Bitfield<10> RiscvISA::im2

Definition at line 129 of file pra_constants.hh.

Bitfield<11> RiscvISA::im3

Definition at line 128 of file pra_constants.hh.

Bitfield<12> RiscvISA::im4

Definition at line 127 of file pra_constants.hh.

Bitfield<13> RiscvISA::im5

Definition at line 126 of file pra_constants.hh.

Bitfield<14> RiscvISA::im6

Definition at line 125 of file pra_constants.hh.

Bitfield< 4, 3 > RiscvISA::impl

Definition at line 92 of file pra_constants.hh.

Bitfield< 22, 0 > RiscvISA::index

Definition at line 46 of file pra_constants.hh.

Bitfield<8> RiscvISA::ip0

Definition at line 195 of file pra_constants.hh.

Bitfield<9> RiscvISA::ip1

Definition at line 194 of file pra_constants.hh.

Bitfield<10> RiscvISA::ip2

Definition at line 193 of file pra_constants.hh.

Bitfield<11> RiscvISA::ip3

Definition at line 192 of file pra_constants.hh.

Bitfield<12> RiscvISA::ip4

Definition at line 191 of file pra_constants.hh.

Bitfield<13> RiscvISA::ip5

Definition at line 190 of file pra_constants.hh.

Bitfield<14> RiscvISA::ip6

Definition at line 189 of file pra_constants.hh.

Bitfield<15, 10> RiscvISA::ipl

Definition at line 122 of file pra_constants.hh.

Bitfield<28, 26> RiscvISA::ippci

Definition at line 146 of file pra_constants.hh.

RiscvISA::ipti

Definition at line 145 of file pra_constants.hh.

Bitfield<24, 22> RiscvISA::is

Definition at line 234 of file pra_constants.hh.

Bitfield<23> RiscvISA::iv

Definition at line 183 of file pra_constants.hh.

Bitfield<1> RiscvISA::k

Definition at line 303 of file pra_constants.hh.

Bitfield<2, 0> RiscvISA::k0

Definition at line 228 of file pra_constants.hh.

Bitfield<30, 28> RiscvISA::k23

Definition at line 219 of file pra_constants.hh.

Bitfield<4, 3> RiscvISA::ksu

Definition at line 136 of file pra_constants.hh.

Bitfield<27, 25> RiscvISA::ku

Definition at line 220 of file pra_constants.hh.

Bitfield<5> RiscvISA::l

Definition at line 322 of file pra_constants.hh.

std::stack< Addr > RiscvISA::locked_addrs

Definition at line 10 of file locked_mem.cc.

Referenced by handleLockedRead(), handleLockedSnoop(), handleLockedWrite(), and PhysicalMemory::serialize().

Bitfield<7> RiscvISA::lpa

Definition at line 266 of file pra_constants.hh.

Bitfield< 11, 3 > RiscvISA::mask

Definition at line 72 of file pra_constants.hh.

Bitfield<12, 11> RiscvISA::maskx

Definition at line 73 of file pra_constants.hh.

const int RiscvISA::Max_Reg_Index = Misc_Reg_Base + NumMiscRegs

Definition at line 81 of file registers.hh.

const int RiscvISA::MaxMiscDestRegs = 1

Definition at line 61 of file registers.hh.

Bitfield<5> RiscvISA::md

Definition at line 241 of file pra_constants.hh.

const int RiscvISA::Misc_Reg_Base = CC_Reg_Base + NumCCRegs

Definition at line 80 of file registers.hh.

Bitfield<30, 25> RiscvISA::mmuSize

Definition at line 233 of file pra_constants.hh.

Bitfield< 2 > RiscvISA::mt

Definition at line 225 of file pra_constants.hh.

Bitfield<24> RiscvISA::mx

Definition at line 114 of file pra_constants.hh.

Bitfield<19> RiscvISA::nmi

Definition at line 119 of file pra_constants.hh.

const ExtMachInst RiscvISA::NoopMachInst = 0x00000013

Definition at line 66 of file isa_traits.hh.

const int RiscvISA::NumCCRegs = 0

Definition at line 74 of file registers.hh.

const int RiscvISA::NumFloatRegs = 32

Definition at line 73 of file registers.hh.

Referenced by RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), and RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs().

const int RiscvISA::NumHpmcounter = 29

Definition at line 109 of file registers.hh.

Referenced by RiscvISA::ISA::ISA().

const int RiscvISA::NumHpmcounterh = 29

Definition at line 110 of file registers.hh.

Referenced by RiscvISA::ISA::ISA().

const int RiscvISA::NumIntArchRegs = 32

Definition at line 70 of file registers.hh.

Referenced by RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), and RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs().

const int RiscvISA::NumIntRegs = NumIntArchRegs + NumMicroIntRegs

Definition at line 72 of file registers.hh.

Referenced by copyRegs().

const int RiscvISA::NumMhpmcounter = 29

Definition at line 111 of file registers.hh.

Referenced by RiscvISA::ISA::ISA().

const int RiscvISA::NumMhpmevent = 29

Definition at line 112 of file registers.hh.

Referenced by RiscvISA::ISA::ISA().

const int RiscvISA::NumMicroIntRegs = 1

Definition at line 71 of file registers.hh.

const int RiscvISA::NumMiscRegs = 4096

Definition at line 75 of file registers.hh.

Referenced by RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), RiscvISA::ISA::ISA(), and RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs().

Bitfield<0> RiscvISA::p

Definition at line 325 of file pra_constants.hh.

Referenced by RiscvISA::TLB::translateData(), and RiscvISA::TLB::translateInst().

const Addr RiscvISA::PageBytes = ULL(1) << PageShift

Definition at line 64 of file isa_traits.hh.

const Addr RiscvISA::PageShift = 12

Definition at line 63 of file isa_traits.hh.

Bitfield<4> RiscvISA::pc

Definition at line 242 of file pra_constants.hh.

Bitfield<26> RiscvISA::pci

Definition at line 181 of file pra_constants.hh.

Bitfield<29, 6> RiscvISA::pfn

Definition at line 57 of file pra_constants.hh.

Bitfield<15, 8> RiscvISA::procId

Definition at line 205 of file pra_constants.hh.

Bitfield<9, 6> RiscvISA::pss

Definition at line 160 of file pra_constants.hh.

Bitfield<7, 6> RiscvISA::pState

Definition at line 321 of file pra_constants.hh.

RiscvISA::pTagLo

Definition at line 320 of file pra_constants.hh.

RiscvISA::pteBase

Definition at line 65 of file pra_constants.hh.

Bitfield<23> RiscvISA::px

Definition at line 115 of file pra_constants.hh.

Bitfield< 1 > RiscvISA::r

Definition at line 97 of file pra_constants.hh.

Referenced by RiscvISA::RemoteGDB::RiscvGdbRegCache::data(), RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs(), and RiscvISA::RemoteGDB::RiscvGdbRegCache::size().

Bitfield<3> RiscvISA::r0

Definition at line 138 of file pra_constants.hh.

RiscvISA::random

Definition at line 52 of file pra_constants.hh.

Bitfield<25> RiscvISA::re

Definition at line 113 of file pra_constants.hh.

const char* const RiscvISA::RegisterNames[]

Initial value:

= {"zero", "ra", "sp", "gp",
    "tp", "t0", "t1", "t2",
    "s0", "s1", "a0", "a1",
    "a2", "a3", "a4", "a5",
    "a6", "a7", "s2", "s3",
    "s4", "s5", "s6", "s7",
    "s8", "s9", "s10", "s11",
    "t3", "t4", "t5", "t6"}

Definition at line 95 of file registers.hh.

const int RiscvISA::ReturnAddrReg = 1

Definition at line 85 of file registers.hh.

const int RiscvISA::ReturnValueReg = ReturnValueRegs[0]

Definition at line 91 of file registers.hh.

const int RiscvISA::ReturnValueRegs[] = {10, 11}

Definition at line 90 of file registers.hh.

Bitfield<7, 0> RiscvISA::rev

Definition at line 206 of file pra_constants.hh.

Bitfield<15, 10> RiscvISA::ripl

Definition at line 186 of file pra_constants.hh.

Bitfield<2> RiscvISA::s

Definition at line 302 of file pra_constants.hh.

Bitfield<3, 0> RiscvISA::sa

Definition at line 258 of file pra_constants.hh.

Bitfield<7, 4> RiscvISA::sl

Definition at line 257 of file pra_constants.hh.

Bitfield<1> RiscvISA::sm

Definition at line 272 of file pra_constants.hh.

Bitfield<4> RiscvISA::sp

Definition at line 269 of file pra_constants.hh.

Bitfield<20> RiscvISA::sr

Definition at line 118 of file pra_constants.hh.

Bitfield<11, 8> RiscvISA::ss

Definition at line 256 of file pra_constants.hh.

Referenced by RiscvISA::ISA::ISA().

Bitfield<3, 0> RiscvISA::ssv0

Definition at line 173 of file pra_constants.hh.

Bitfield<7, 4> RiscvISA::ssv1

Definition at line 172 of file pra_constants.hh.

Bitfield<11, 8> RiscvISA::ssv2

Definition at line 171 of file pra_constants.hh.

Bitfield<15, 12> RiscvISA::ssv3

Definition at line 170 of file pra_constants.hh.

Bitfield<19, 16> RiscvISA::ssv4

Definition at line 169 of file pra_constants.hh.

Bitfield<23, 20> RiscvISA::ssv5

Definition at line 168 of file pra_constants.hh.

Bitfield<27, 24> RiscvISA::ssv6

Definition at line 167 of file pra_constants.hh.

RiscvISA::ssv7

Definition at line 166 of file pra_constants.hh.

const int RiscvISA::StackPointerReg = 2

Definition at line 86 of file registers.hh.

Bitfield<15, 12> RiscvISA::su

Definition at line 255 of file pra_constants.hh.

Bitfield<6> RiscvISA::sx

Definition at line 134 of file pra_constants.hh.

const int RiscvISA::SyscallArgumentRegs[]

Initial value:

= {ArgumentRegs[0], ArgumentRegs[1],
    ArgumentRegs[2], ArgumentRegs[3]}

Definition at line 105 of file registers.hh.

Referenced by RiscvProcess::getSyscallArg(), and RiscvProcess::setSyscallArg().

const int RiscvISA::SyscallNumReg = ArgumentRegs[7]

Definition at line 104 of file registers.hh.

Referenced by RiscvISA::SyscallFault::invoke_se().

const int RiscvISA::SyscallPseudoReturnReg = ReturnValueRegs[0]

Definition at line 107 of file registers.hh.

Bitfield<19, 16> RiscvISA::ta

Definition at line 254 of file pra_constants.hh.

const int RiscvISA::ThreadPointerReg = 4

Definition at line 88 of file registers.hh.

Bitfield<30> RiscvISA::ti

Definition at line 178 of file pra_constants.hh.

Bitfield< 0 > RiscvISA::tl

Definition at line 253 of file pra_constants.hh.

Bitfield< 27, 24 > RiscvISA::ts

Definition at line 117 of file pra_constants.hh.

Bitfield<30, 28> RiscvISA::tu

Definition at line 251 of file pra_constants.hh.

Bitfield<3> RiscvISA::u

Definition at line 301 of file pra_constants.hh.

Bitfield<4> RiscvISA::um

Definition at line 137 of file pra_constants.hh.

Bitfield<5> RiscvISA::ux

Definition at line 135 of file pra_constants.hh.

Bitfield<1> RiscvISA::v

Definition at line 60 of file pra_constants.hh.

RiscvISA::vaddr

Definition at line 277 of file pra_constants.hh.

Referenced by vtophys().

Bitfield<6> RiscvISA::veic

Definition at line 267 of file pra_constants.hh.

Bitfield<3> RiscvISA::vi

Definition at line 227 of file pra_constants.hh.

Bitfield<5> RiscvISA::vint

Definition at line 268 of file pra_constants.hh.

Bitfield<39, 13> RiscvISA::vpn2

Definition at line 99 of file pra_constants.hh.

Bitfield<12, 11> RiscvISA::vpn2x

Definition at line 100 of file pra_constants.hh.

Bitfield<9, 5> RiscvISA::vs

Definition at line 148 of file pra_constants.hh.

Bitfield< 30 > RiscvISA::w

Definition at line 280 of file pra_constants.hh.

const int RiscvISA::WARN_FAILURE = 10000

Definition at line 66 of file locked_mem.hh.

Referenced by handleLockedWrite().

RiscvISA::wired

Definition at line 88 of file pra_constants.hh.

Bitfield<22> RiscvISA::wp

Definition at line 184 of file pra_constants.hh.

Bitfield<3> RiscvISA::wr

Definition at line 243 of file pra_constants.hh.

const int RiscvISA::ZeroReg = 0

Definition at line 84 of file registers.hh.