Base, ISA-independent static instruction class. More...

#include <static_inst.hh>

Inheritance diagram for StaticInst:

Public Types
enum	{ MaxInstSrcRegs = TheISA::MaxInstSrcRegs, MaxInstDestRegs = TheISA::MaxInstDestRegs }

typedef TheISA::ExtMachInst	ExtMachInst
	Binary extended machine instruction type. More...

typedef TheISA::RegIndex	RegIndex
	Logical register index type. More...

Public Member Functions
int8_t	numCCDestRegs () const
	Number of coprocesor destination regs. More...

void	setFirstMicroop ()

void	setLastMicroop ()

void	setDelayedCommit ()

void	setFlag (Flags f)

OpClass	opClass () const
	Operation class. Used to select appropriate function unit in issue. More...

RegIndex	destRegIdx (int i) const
	Return logical index (architectural reg num) of i'th destination reg. More...

RegIndex	srcRegIdx (int i) const
	Return logical index (architectural reg num) of i'th source reg. More...

virtual const StaticInstPtr &	eaCompInst () const
	Memory references only: returns "fake" instruction representing the effective address part of the memory operation. More...

virtual const StaticInstPtr &	memAccInst () const
	Memory references only: returns "fake" instruction representing the memory access part of the memory operation. More...

virtual	~StaticInst ()

virtual Fault	execute (ExecContext xc, Trace::InstRecord traceData) const =0

virtual Fault	eaComp (ExecContext xc, Trace::InstRecord traceData) const

virtual Fault	initiateAcc (ExecContext xc, Trace::InstRecord traceData) const

virtual Fault	completeAcc (Packet pkt, ExecContext xc, Trace::InstRecord *traceData) const

virtual void	advancePC (TheISA::PCState &pcState) const =0

virtual StaticInstPtr	fetchMicroop (MicroPC upc) const
	Return the microop that goes with a particular micropc. More...

virtual TheISA::PCState	branchTarget (const TheISA::PCState &pc) const
	Return the target address for a PC-relative branch. More...

virtual TheISA::PCState	branchTarget (ThreadContext *tc) const
	Return the target address for an indirect branch (jump). More...

bool	hasBranchTarget (const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) const
	Return true if the instruction is a control transfer, and if so, return the target address as well. More...

virtual const std::string &	disassemble (Addr pc, const SymbolTable *symtab=0) const
	Return string representation of disassembled instruction. More...

void	printFlags (std::ostream &outs, const std::string &separator) const
	Print a separator separated list of this instruction's set flag names on the given stream. More...

std::string	getName ()
	Return name of machine instruction. More...

Register information.
The sum of numFPDestRegs() and numIntDestRegs() equals numDestRegs(). The former two functions are used to track physical register usage for machines with separate int & FP reg files.
int8_t	numSrcRegs () const
	Number of source registers. More...

int8_t	numDestRegs () const
	Number of destination registers. More...

int8_t	numFPDestRegs () const
	Number of floating-point destination regs. More...

int8_t	numIntDestRegs () const
	Number of integer destination regs. More...

Flag accessors.
These functions are used to access the values of the various instruction property flags. See StaticInst::Flags for descriptions of the individual flags.
bool	isNop () const

bool	isMemRef () const

bool	isLoad () const

bool	isStore () const

bool	isStoreConditional () const

bool	isInstPrefetch () const

bool	isDataPrefetch () const

bool	isPrefetch () const

bool	isInteger () const

bool	isFloating () const

bool	isCC () const

bool	isControl () const

bool	isCall () const

bool	isReturn () const

bool	isDirectCtrl () const

bool	isIndirectCtrl () const

bool	isCondCtrl () const

bool	isUncondCtrl () const

bool	isCondDelaySlot () const

bool	isThreadSync () const

bool	isSerializing () const

bool	isSerializeBefore () const

bool	isSerializeAfter () const

bool	isSquashAfter () const

bool	isMemBarrier () const

bool	isWriteBarrier () const

bool	isNonSpeculative () const

bool	isQuiesce () const

bool	isIprAccess () const

bool	isUnverifiable () const

bool	isSyscall () const

bool	isMacroop () const

bool	isMicroop () const

bool	isDelayedCommit () const

bool	isLastMicroop () const

bool	isFirstMicroop () const

bool	isMicroBranch () const

Public Member Functions inherited from RefCounted
	RefCounted ()
	We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More...

virtual	~RefCounted ()
	We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More...

void	incref ()
	Increment the reference count. More...

void	decref ()
	Decrement the reference count and destroy the object if all references are gone. More...

Public Attributes
const ExtMachInst	machInst
	The binary machine instruction. More...

Static Public Attributes
static StaticInstPtr	nullStaticInstPtr
	Pointer to a statically allocated "null" instruction object. More...

Protected Member Functions
virtual std::string	generateDisassembly (Addr pc, const SymbolTable *symtab) const =0
	Internal function to generate disassembly string. More...

	StaticInst (const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
	Constructor. More...

Protected Attributes
std::bitset< Num_Flags >	flags
	Flag values for this instruction. More...

OpClass	_opClass
	See opClass(). More...

int8_t	_numSrcRegs
	See numSrcRegs(). More...

int8_t	_numDestRegs
	See numDestRegs(). More...

RegIndex	_destRegIdx [MaxInstDestRegs]
	See destRegIdx(). More...

RegIndex	_srcRegIdx [MaxInstSrcRegs]
	See srcRegIdx(). More...

const char *	mnemonic
	Base mnemonic (e.g., "add"). More...

std::string *	cachedDisassembly
	String representation of disassembly (lazily evaluated via disassemble()). More...


int8_t	_numFPDestRegs
	The following are used to track physical register usage for machines with separate int & FP reg files. More...

int8_t	_numIntDestRegs

int8_t	_numCCDestRegs

Detailed Description

Base, ISA-independent static instruction class.

The main component of this class is the vector of flags and the associated methods for reading them. Any object that can rely solely on these flags can process instructions without being recompiled for multiple ISAs.

Definition at line 68 of file static_inst.hh.

Member Typedef Documentation

typedef TheISA::ExtMachInst StaticInst::ExtMachInst

Binary extended machine instruction type.

Definition at line 72 of file static_inst.hh.

typedef TheISA::RegIndex StaticInst::RegIndex

Logical register index type.

Definition at line 74 of file static_inst.hh.

Member Enumeration Documentation

anonymous enum

Enumerator
MaxInstSrcRegs
MaxInstDestRegs

Definition at line 76 of file static_inst.hh.

Constructor & Destructor Documentation

StaticInst::StaticInst	(	const char *	_mnemonic,
		ExtMachInst	_machInst,
		OpClass	__opClass
	)

inlineprotected

Constructor.

It's important to initialize everything here to a sane default, since the decoder generally only overrides the fields that are meaningful for the particular instruction.

Definition at line 252 of file static_inst.hh.

StaticInst::~StaticInst ( )

virtual

Definition at line 42 of file static_inst.cc.

Member Function Documentation

virtual void StaticInst::advancePC ( TheISA::PCState & pcState ) const

pure virtual

Referenced by SparcISA::advancePC(), X86ISA::advancePC(), RiscvISA::advancePC(), Minor::Decode::evaluate(), ArmISA::SupervisorCall::invoke(), and ArmISA::FlushPipe::invoke().

TheISA::PCState StaticInst::branchTarget ( const TheISA::PCState & pc ) const

virtual

Return the target address for a PC-relative branch.

Invalid if not a PC-relative branch (i.e. isDirectCtrl() should be true).

Definition at line 73 of file static_inst.cc.

References panic.

Referenced by BaseDynInst< Impl >::branchTarget().

TheISA::PCState StaticInst::branchTarget ( ThreadContext * tc ) const

virtual

Return the target address for an indirect branch (jump).

The register value is read from the supplied thread context, so the result is valid only if the thread context is about to execute the branch in question. Invalid if not an indirect branch (i.e. isIndirectCtrl() should be true).

Reimplemented in PowerISA::BranchRegCond.

Definition at line 81 of file static_inst.cc.

References panic.

virtual Fault StaticInst::completeAcc	(	Packet *	pkt,
		ExecContext *	xc,
		Trace::InstRecord *	traceData
	)		const

inlinevirtual

Definition at line 275 of file static_inst.hh.

References panic.

Referenced by TimingSimpleCPU::completeDataAccess().

RegIndex StaticInst::destRegIdx ( int i ) const

inline

Return logical index (architectural reg num) of i'th destination reg.

Only the entries from 0 through numDestRegs()-1 are valid.

Definition at line 188 of file static_inst.hh.

References _destRegIdx, and ArmISA::i.

Referenced by BaseDynInst< Impl >::destRegIdx(), BaseO3DynInst< Impl >::forwardOldRegs(), Minor::Scoreboard::markupInstDests(), Minor::MinorDynInst::minorTraceInst(), MsrBase::printMsrBase(), SimpleExecContext::setCCRegOperand(), CheckerCPU::setCCRegOperand(), Minor::ExecContext::setCCRegOperand(), Minor::ExecContext::setFloatRegOperand(), SimpleExecContext::setFloatRegOperand(), CheckerCPU::setFloatRegOperand(), Minor::ExecContext::setFloatRegOperandBits(), SimpleExecContext::setFloatRegOperandBits(), CheckerCPU::setFloatRegOperandBits(), Minor::ExecContext::setIntRegOperand(), SimpleExecContext::setIntRegOperand(), CheckerCPU::setIntRegOperand(), BaseO3DynInst< Impl >::setMiscRegOperand(), Minor::ExecContext::setMiscRegOperand(), SimpleExecContext::setMiscRegOperand(), and CheckerCPU::setMiscRegOperand().

const string & StaticInst::disassemble	(	Addr	pc,
		const SymbolTable *	symtab = `0`
	)		const

virtual

Return string representation of disassembled instruction.

The default version of this function will call the internal virtual generateDisassembly() function to get the string, then cache it in cachedDisassembly. If the disassembly should not be cached, this function should be overridden directly.

Reimplemented in PowerISA::PCDependentDisassembly.

Definition at line 89 of file static_inst.cc.

Referenced by Minor::Scoreboard::canInstIssue(), Minor::FUPipeline::findTiming(), Minor::MinorDynInst::minorTraceInst(), and Trace::ExeTracerRecord::traceInst().

virtual Fault StaticInst::eaComp	(	ExecContext *	xc,
		Trace::InstRecord *	traceData
	)		const

inlinevirtual

Definition at line 263 of file static_inst.hh.

References panic.

virtual const StaticInstPtr& StaticInst::eaCompInst ( ) const

inlinevirtual

Memory references only: returns "fake" instruction representing the effective address part of the memory operation.

Used to obtain the dependence info (numSrcRegs and srcRegIdx[]) for just the EA computation.

Definition at line 206 of file static_inst.hh.

References nullStaticInstPtr.

Referenced by BaseO3DynInst< Impl >::calcEA().

virtual Fault StaticInst::execute	(	ExecContext *	xc,
		Trace::InstRecord *	traceData
	)		const

pure virtual

Implemented in McrMrcMiscInst, WarnUnimplemented, FailUnimplemented, and DecoderFaultInst.

Referenced by BaseO3DynInst< Impl >::calcEA(), TimingSimpleCPU::completeIfetch(), BaseO3DynInst< Impl >::memAccess(), and AtomicSimpleCPU::tick().

StaticInstPtr StaticInst::fetchMicroop ( MicroPC upc ) const

virtual

Return the microop that goes with a particular micropc.

This should only be defined/used in macroops which will contain microops

Reimplemented in ArmISA::PredMacroOp, ArmISA::Memory, ArmISA::SrsOp, ArmISA::RfeOp, ArmISA::Memory64, and X86ISA::MacroopBase.

Definition at line 66 of file static_inst.cc.

References panic.

Referenced by Minor::Decode::evaluate(), DefaultFetch< Impl >::fetch(), BaseSimpleCPU::preExecute(), and Checker< Impl >::verify().

virtual std::string StaticInst::generateDisassembly	(	Addr	pc,
		const SymbolTable *	symtab
	)		const

protectedpure virtual

Internal function to generate disassembly string.

Implemented in ArmISA::FpRegRegRegImmOp, ArmISA::FpRegRegRegRegOp, ArmISA::FpRegRegRegCondOp, ArmISA::FpRegRegRegOp, ArmISA::FpRegRegImmOp, ArmISA::FpRegImmOp, ArmISA::FpRegRegOp, ArmISA::FpCondSelOp, ArmISA::FpCondCompRegOp, ArmISA::MicroMemPairOp, ArmISA::MicroMemOp, ArmISA::MicroIntRegXOp, UnknownOp, RegImmRegShiftOp, ArmISA::MicroIntOp, ArmISA::PredMacroOp, RegRegImmImmOp, ArmISA::MicroIntImmXOp, RegImmImmOp, ArmISA::MicroIntImmOp, ArmISA::DataRegRegOp, RegMiscRegImmOp, ArmISA::MicroIntMov, ArmISA::DataRegOp, MiscRegRegImmOp, ArmISA::MicroSetPCCPSR, ArmISA::DataImmOp, RegRegImmOp, ArmISA::DataXCondSelOp, PowerISA::BranchRegCond, ArmISA::MemoryLiteral64, ArmISA::PredIntOp, RegRegRegOp, ArmISA::MemoryEx64, ArmISA::DataXCondCompRegOp, PowerISA::BranchNonPCRelCond, ArmISA::PredImmOp, RegRegRegRegOp, ArmISA::MemoryRaw64, ArmISA::DataXCondCompImmOp, ArmISA::MemoryReg64, RegRegRegImmOp, PowerISA::BranchPCRelCond, ArmISA::DataX3RegOp, ArmISA::MemoryPostIndex64, ArmISA::ArmStaticInst, RegImmRegOp, ArmISA::DataX2RegImmOp, ArmISA::MemoryPreIndex64, RegRegOp, PowerISA::IntRotateOp, ArmISA::DataX2RegOp, ArmISA::MemoryDImmEx64, ArmISA::SrsOp, ArmISA::BranchImmImmReg64, RegImmOp, ArmISA::DataX1Reg2ImmOp, ArmISA::MemoryDImm64, X86ISA::LdStSplitOp, PowerISA::FloatOp, ImmOp, ArmISA::DataX1RegImmOp, ArmISA::MemoryImm64, ArmISA::BranchImmReg64, McrMrcMiscInst, PowerISA::IntShiftOp, McrrOp, X86ISA::MediaOpImm, ArmISA::RfeOp, ArmISA::DataX1RegOp, PowerISA::BranchNonPCRel, X86ISA::RegOpImm, X86ISA::LdStOp, ArmISA::BranchEret64, PowerISA::IntImmOp, WarnUnimplemented, X86ISA::X86MicroopBase, MrrcOp, ArmISA::DataXERegOp, X86ISA::MediaOpReg, ArmISA::BranchRet64, X86ISA::RegOp, MsrRegOp, PowerISA::BranchPCRel, PowerISA::IntOp, ArmISA::BranchReg64, ArmISA::DataXSRegOp, UnknownOp64, X86ISA::MacroopBase, FailUnimplemented, PowerISA::MemDispOp, MsrImmOp, PowerISA::CondMoveOp, X86ISA::FpOp, ArmISA::BranchImmCond64, RegRegRegImmOp64, ArmISA::DataXImmOnlyOp, X86ISA::X86StaticInst, PowerISA::PowerStaticInst, PowerISA::MemOp, ArmISA::BranchImm64, ArmISA::Swap, DecoderFaultInst, ArmISA::DataXImmOp, RegRegImmImmOp64, PowerISA::CondLogicOp, ArmISA::SysDC64, MrsOp, and PowerISA::MiscOp.

std::string StaticInst::getName ( )

inline

Return name of machine instruction.

Definition at line 329 of file static_inst.hh.

References mnemonic.

Referenced by Minor::operator<<(), and BaseSimpleCPU::preExecute().

bool StaticInst::hasBranchTarget	(	const TheISA::PCState &	pc,
		ThreadContext *	tc,
		TheISA::PCState &	tgt
	)		const

Return true if the instruction is a control transfer, and if so, return the target address as well.

Definition at line 49 of file static_inst.cc.

virtual Fault StaticInst::initiateAcc	(	ExecContext *	xc,
		Trace::InstRecord *	traceData
	)		const

inlinevirtual

Definition at line 269 of file static_inst.hh.

References panic.

Referenced by TimingSimpleCPU::completeIfetch().

bool StaticInst::isCall ( ) const

inline

Definition at line 146 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isCall(), BaseSimpleCPU::postExecute(), BPredUnit::predict(), X86ISA::StackTrace::trace(), MipsISA::StackTrace::trace(), AlphaISA::StackTrace::trace(), ArmISA::StackTrace::trace(), RiscvISA::StackTrace::trace(), and PowerISA::StackTrace::trace().

bool StaticInst::isCC ( ) const

inline

Definition at line 143 of file static_inst.hh.

References flags.

bool StaticInst::isCondCtrl ( ) const

inline

Definition at line 150 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isCondCtrl(), and BaseSimpleCPU::postExecute().

bool StaticInst::isCondDelaySlot ( ) const

inline

Definition at line 152 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isCondDelaySlot().

bool StaticInst::isControl ( ) const

inline

Definition at line 145 of file static_inst.hh.

References flags.

Referenced by BaseSimpleCPU::advancePC(), BaseDynInst< Impl >::isControl(), BaseSimpleCPU::postExecute(), BaseSimpleCPU::preExecute(), and SimPoint::profile().

bool StaticInst::isDataPrefetch ( ) const

inline

Definition at line 137 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isDataPrefetch(), and isPrefetch().

bool StaticInst::isDelayedCommit ( ) const

inline

Definition at line 170 of file static_inst.hh.

References flags.

Referenced by TimingSimpleCPU::fetch(), BaseDynInst< Impl >::isDelayedCommit(), BaseSimpleCPU::swapActiveThread(), and AtomicSimpleCPU::tick().

bool StaticInst::isDirectCtrl ( ) const

inline

Definition at line 148 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isDirectCtrl(), and BPredUnit::predict().

bool StaticInst::isFirstMicroop ( ) const

inline

Definition at line 172 of file static_inst.hh.

References flags.

Referenced by TimingSimpleCPU::completeIfetch(), Trace::InstPBTraceRecord::dump(), BaseDynInst< Impl >::isFirstMicroop(), and AtomicSimpleCPU::tick().

bool StaticInst::isFloating ( ) const

inline

Definition at line 142 of file static_inst.hh.

References flags.

Referenced by ArmISA::MicroMemOp::generateDisassembly(), BaseDynInst< Impl >::isFloating(), and BaseSimpleCPU::postExecute().

bool StaticInst::isIndirectCtrl ( ) const

inline

Definition at line 149 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isIndirectCtrl().

bool StaticInst::isInstPrefetch ( ) const

inline

Definition at line 136 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isInstPrefetch(), and isPrefetch().

bool StaticInst::isInteger ( ) const

inline

Definition at line 141 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isInteger(), and BaseSimpleCPU::postExecute().

bool StaticInst::isIprAccess ( ) const

inline

Definition at line 165 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isIprAccess().

bool StaticInst::isLastMicroop ( ) const

inline

Definition at line 171 of file static_inst.hh.

References flags.

Referenced by BaseSimpleCPU::advancePC(), ArmISA::BigFpMemPostOp::BigFpMemPostOp(), ArmISA::BigFpMemPreOp::BigFpMemPreOp(), BaseSimpleCPU::countInst(), Minor::Decode::evaluate(), DefaultFetch< Impl >::fetch(), BaseDynInst< Impl >::isLastMicroop(), Minor::MinorDynInst::isLastOpInInst(), ArmISA::MacroMemOp::MacroMemOp(), ArmISA::MacroVFPMemOp::MacroVFPMemOp(), ArmISA::PairMemOp::PairMemOp(), and SimPoint::profile().

bool StaticInst::isLoad ( ) const

inline

Definition at line 133 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isLoad(), and BaseSimpleCPU::postExecute().

bool StaticInst::isMacroop ( ) const

inline

Definition at line 168 of file static_inst.hh.

References flags.

Referenced by Minor::Decode::evaluate(), DefaultFetch< Impl >::fetch(), BaseDynInst< Impl >::isMacroop(), Minor::MinorDynInst::minorTraceInst(), BaseSimpleCPU::preExecute(), and Checker< Impl >::verify().

bool StaticInst::isMemBarrier ( ) const

inline

Definition at line 161 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isMemBarrier().

bool StaticInst::isMemRef ( ) const

inline

Definition at line 132 of file static_inst.hh.

References flags.

Referenced by TimingSimpleCPU::completeIfetch(), Minor::MinorDynInst::isMemRef(), BaseDynInst< Impl >::isMemRef(), and BaseSimpleCPU::postExecute().

bool StaticInst::isMicroBranch ( ) const

inline

Definition at line 174 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isMicroBranch().

bool StaticInst::isMicroop ( ) const

inline

Definition at line 169 of file static_inst.hh.

References flags.

Referenced by Trace::ArmNativeTrace::check(), TimingSimpleCPU::completeIfetch(), BaseSimpleCPU::countInst(), Trace::InstPBTraceRecord::dump(), Minor::MinorDynInst::isLastOpInInst(), BaseDynInst< Impl >::isMicroop(), SimPoint::profile(), AtomicSimpleCPU::tick(), and Trace::ExeTracerRecord::traceInst().

bool StaticInst::isNonSpeculative ( ) const

inline

Definition at line 163 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isNonSpeculative().

bool StaticInst::isNop ( ) const

inline

Definition at line 130 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isNop().

bool StaticInst::isPrefetch ( ) const

inline

Definition at line 138 of file static_inst.hh.

References isDataPrefetch(), and isInstPrefetch().

bool StaticInst::isQuiesce ( ) const

inline

Definition at line 164 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isQuiesce().

bool StaticInst::isReturn ( ) const

inline

Definition at line 147 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isReturn(), BaseSimpleCPU::postExecute(), BPredUnit::predict(), X86ISA::StackTrace::trace(), MipsISA::StackTrace::trace(), AlphaISA::StackTrace::trace(), ArmISA::StackTrace::trace(), RiscvISA::StackTrace::trace(), and PowerISA::StackTrace::trace().

bool StaticInst::isSerializeAfter ( ) const

inline

Definition at line 159 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isSerializeAfter().

bool StaticInst::isSerializeBefore ( ) const

inline

Definition at line 158 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isSerializeBefore().

bool StaticInst::isSerializing ( ) const

inline

Definition at line 155 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isSerializing().

bool StaticInst::isSquashAfter ( ) const

inline

Definition at line 160 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isSquashAfter().

bool StaticInst::isStore ( ) const

inline

Definition at line 134 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isStore(), and BaseSimpleCPU::postExecute().

bool StaticInst::isStoreConditional ( ) const

inline

Definition at line 135 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isStoreConditional().

bool StaticInst::isSyscall ( ) const

inline

Definition at line 167 of file static_inst.hh.

References flags.

Referenced by Trace::X86NativeTrace::check(), and BaseDynInst< Impl >::isSyscall().

bool StaticInst::isThreadSync ( ) const

inline

Definition at line 154 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isThreadSync().

bool StaticInst::isUncondCtrl ( ) const

inline

Definition at line 151 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isUncondCtrl(), and BPredUnit::predict().

bool StaticInst::isUnverifiable ( ) const

inline

Definition at line 166 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isUnverifiable().

bool StaticInst::isWriteBarrier ( ) const

inline

Definition at line 162 of file static_inst.hh.

References flags.

Referenced by BaseDynInst< Impl >::isWriteBarrier().

virtual const StaticInstPtr& StaticInst::memAccInst ( ) const

inlinevirtual

Memory references only: returns "fake" instruction representing the memory access part of the memory operation.

Used to obtain the dependence info (numSrcRegs and srcRegIdx[]) for just the memory access (not the EA computation).

Definition at line 215 of file static_inst.hh.

References nullStaticInstPtr.

Referenced by BaseO3DynInst< Impl >::memAccess().

int8_t StaticInst::numCCDestRegs ( ) const

inline

Number of coprocesor destination regs.

Definition at line 121 of file static_inst.hh.

Referenced by BaseDynInst< Impl >::numCCDestRegs().

int8_t StaticInst::numDestRegs ( ) const

inline

Number of destination registers.

Definition at line 114 of file static_inst.hh.

References _numDestRegs.

Referenced by Minor::Scoreboard::clearInstDests(), Minor::Scoreboard::markupInstDests(), Minor::MinorDynInst::minorTraceInst(), BaseDynInst< Impl >::numDestRegs(), and MsrBase::printMsrBase().

int8_t StaticInst::numFPDestRegs ( ) const

inline

Number of floating-point destination regs.

Definition at line 116 of file static_inst.hh.

References _numFPDestRegs.

Referenced by BaseDynInst< Impl >::numFPDestRegs().

int8_t StaticInst::numIntDestRegs ( ) const

inline

Number of integer destination regs.

Definition at line 118 of file static_inst.hh.

References _numIntDestRegs.

Referenced by BaseDynInst< Impl >::numIntDestRegs().

int8_t StaticInst::numSrcRegs ( ) const

inline

Number of source registers.

Definition at line 112 of file static_inst.hh.

Referenced by Minor::Scoreboard::canInstIssue(), Minor::Scoreboard::execSeqNumToWaitFor(), MrsOp::generateDisassembly(), Minor::MinorDynInst::minorTraceInst(), and BaseDynInst< Impl >::numSrcRegs().

OpClass StaticInst::opClass ( ) const

inline

Operation class. Used to select appropriate function unit in issue.

Definition at line 183 of file static_inst.hh.

References _opClass.

Referenced by Minor::FUPipeline::findTiming(), Minor::MinorDynInst::isNoCostInst(), Minor::MinorDynInst::minorTraceInst(), BaseDynInst< Impl >::opClass(), BaseSimpleCPU::postExecute(), Trace::ExeTracerRecord::traceInst(), Trace::InstPBTrace::traceInst(), and Trace::InstPBTrace::traceMem().

void StaticInst::printFlags	(	std::ostream &	outs,
		const std::string &	separator
	)		const

Print a separator separated list of this instruction's set flag names on the given stream.

Definition at line 98 of file static_inst.cc.

Referenced by Minor::MinorDynInst::minorTraceInst(), and Trace::ExeTracerRecord::traceInst().

void StaticInst::setDelayedCommit ( )

inline

Definition at line 179 of file static_inst.hh.

References flags.

Referenced by ArmISA::MacroVFPMemOp::MacroVFPMemOp(), ArmISA::VldMultOp::VldMultOp(), ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp::VstMultOp(), ArmISA::VstMultOp64::VstMultOp64(), ArmISA::VstSingleOp::VstSingleOp(), and ArmISA::VstSingleOp64::VstSingleOp64().

void StaticInst::setFirstMicroop ( )

inline

Definition at line 177 of file static_inst.hh.

References flags.

Referenced by ArmISA::BigFpMemImmOp::BigFpMemImmOp(), ArmISA::BigFpMemLitOp::BigFpMemLitOp(), ArmISA::BigFpMemPostOp::BigFpMemPostOp(), ArmISA::BigFpMemPreOp::BigFpMemPreOp(), ArmISA::BigFpMemRegOp::BigFpMemRegOp(), ArmISA::MacroMemOp::MacroMemOp(), ArmISA::PairMemOp::PairMemOp(), ArmISA::VldMultOp::VldMultOp(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VstMultOp::VstMultOp(), and ArmISA::VstSingleOp::VstSingleOp().

void StaticInst::setFlag ( Flags f )

inline

Definition at line 180 of file static_inst.hh.

References ArmISA::f, and flags.

Referenced by ArmISA::MacroMemOp::MacroMemOp().

void StaticInst::setLastMicroop ( )

inline

Definition at line 178 of file static_inst.hh.

References flags.

Referenced by ArmISA::BigFpMemLitOp::BigFpMemLitOp(), ArmISA::MacroMemOp::MacroMemOp(), ArmISA::MacroVFPMemOp::MacroVFPMemOp(), ArmISA::PairMemOp::PairMemOp(), ArmISA::VldMultOp::VldMultOp(), ArmISA::VldMultOp64::VldMultOp64(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VldSingleOp64::VldSingleOp64(), ArmISA::VstMultOp::VstMultOp(), ArmISA::VstMultOp64::VstMultOp64(), ArmISA::VstSingleOp::VstSingleOp(), and ArmISA::VstSingleOp64::VstSingleOp64().

RegIndex StaticInst::srcRegIdx ( int i ) const

inline

Return logical index (architectural reg num) of i'th source reg.

Only the entries from 0 through numSrcRegs()-1 are valid.

Definition at line 192 of file static_inst.hh.

References _srcRegIdx, and ArmISA::i.

Referenced by Minor::Scoreboard::canInstIssue(), TimingExprSrcReg::eval(), Minor::Scoreboard::execSeqNumToWaitFor(), MrsOp::generateDisassembly(), Minor::MinorDynInst::minorTraceInst(), SimpleExecContext::readCCRegOperand(), CheckerCPU::readCCRegOperand(), Minor::ExecContext::readCCRegOperand(), Minor::ExecContext::readFloatRegOperand(), SimpleExecContext::readFloatRegOperand(), CheckerCPU::readFloatRegOperand(), Minor::ExecContext::readFloatRegOperandBits(), SimpleExecContext::readFloatRegOperandBits(), CheckerCPU::readFloatRegOperandBits(), Minor::ExecContext::readIntRegOperand(), SimpleExecContext::readIntRegOperand(), CheckerCPU::readIntRegOperand(), BaseO3DynInst< Impl >::readMiscRegOperand(), Minor::ExecContext::readMiscRegOperand(), SimpleExecContext::readMiscRegOperand(), CheckerCPU::readMiscRegOperand(), and BaseDynInst< Impl >::srcRegIdx().

Member Data Documentation

RegIndex StaticInst::_destRegIdx[MaxInstDestRegs]

protected

See destRegIdx().

Definition at line 223 of file static_inst.hh.

Referenced by destRegIdx(), PowerISA::MiscOp::generateDisassembly(), PowerISA::MemDispOp::generateDisassembly(), PowerISA::FloatOp::generateDisassembly(), X86ISA::X86StaticInst::merge(), and X86ISA::X86StaticInst::printDestReg().

int8_t StaticInst::_numCCDestRegs

protected

Definition at line 100 of file static_inst.hh.

int8_t StaticInst::_numDestRegs

protected

See numDestRegs().

Definition at line 93 of file static_inst.hh.

Referenced by PowerISA::MiscOp::generateDisassembly(), PowerISA::MemDispOp::generateDisassembly(), PowerISA::FloatOp::generateDisassembly(), numDestRegs(), and X86ISA::X86StaticInst::printDestReg().

int8_t StaticInst::_numFPDestRegs

protected

The following are used to track physical register usage for machines with separate int & FP reg files.

Definition at line 98 of file static_inst.hh.

Referenced by numFPDestRegs().

int8_t StaticInst::_numIntDestRegs

protected

Definition at line 99 of file static_inst.hh.

Referenced by numIntDestRegs().

int8_t StaticInst::_numSrcRegs

protected

See numSrcRegs().

Definition at line 90 of file static_inst.hh.

Referenced by PowerISA::BranchRegCond::branchTarget(), PowerISA::MiscOp::generateDisassembly(), PowerISA::FloatOp::generateDisassembly(), and X86ISA::X86StaticInst::printSrcReg().

OpClass StaticInst::_opClass

protected

See opClass().

Definition at line 87 of file static_inst.hh.

Referenced by opClass().

RegIndex StaticInst::_srcRegIdx[MaxInstSrcRegs]

protected

See srcRegIdx().

Definition at line 225 of file static_inst.hh.

Referenced by PowerISA::BranchRegCond::branchTarget(), PowerISA::MiscOp::generateDisassembly(), PowerISA::MemDispOp::generateDisassembly(), PowerISA::FloatOp::generateDisassembly(), X86ISA::X86StaticInst::pick(), X86ISA::X86StaticInst::printSrcReg(), X86ISA::X86StaticInst::signedPick(), and srcRegIdx().

std::string* StaticInst::cachedDisassembly

mutableprotected

String representation of disassembly (lazily evaluated via disassemble()).

Definition at line 239 of file static_inst.hh.

Referenced by PowerISA::PCDependentDisassembly::disassemble().

std::bitset<Num_Flags> StaticInst::flags

protected

Flag values for this instruction.

Definition at line 84 of file static_inst.hh.

Referenced by ArmISA::MightBeMicro64::advancePC(), ArmISA::MightBeMicro::advancePC(), ArmISA::MicroOp::advancePC(), ArmISA::MicroOpX::advancePC(), X86ISA::X86MicroopBase::advancePC(), ArmISA::PredMicroop::advancePC(), ArmISA::FpOp::advancePC(), X86ISA::X86MicroopBase::checkCondition(), DecoderFaultInst::DecoderFaultInst(), FailUnimplemented::FailUnimplemented(), ArmISA::FpRegImmOp::FpRegImmOp(), ArmISA::FpRegRegImmOp::FpRegRegImmOp(), ArmISA::FpRegRegOp::FpRegRegOp(), ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp(), ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp(), ArmISA::FpRegRegRegOp::FpRegRegRegOp(), ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp(), PowerISA::MemDispOp::generateDisassembly(), X86ISA::LdStOp::generateDisassembly(), X86ISA::LdStSplitOp::generateDisassembly(), X86ISA::RegOpBase::genFlags(), isCall(), isCC(), isCondCtrl(), isCondDelaySlot(), isControl(), isDataPrefetch(), isDelayedCommit(), isDirectCtrl(), isFirstMicroop(), isFloating(), isIndirectCtrl(), isInstPrefetch(), isInteger(), isIprAccess(), isLastMicroop(), isLoad(), isMacroop(), isMemBarrier(), isMemRef(), isMicroBranch(), isMicroop(), isNonSpeculative(), isNop(), isQuiesce(), isReturn(), isSerializeAfter(), isSerializeBefore(), isSerializing(), isSquashAfter(), isStore(), isStoreConditional(), isSyscall(), isThreadSync(), isUncondCtrl(), isUnverifiable(), isWriteBarrier(), X86ISA::MacroopBase::MacroopBase(), McrMrcMiscInst::McrMrcMiscInst(), ArmISA::PredMacroOp::PredMacroOp(), ArmISA::PredMicroop::PredMicroop(), setDelayedCommit(), setFirstMicroop(), setFlag(), setLastMicroop(), WarnUnimplemented::WarnUnimplemented(), and X86ISA::X86MicroopBase::X86MicroopBase().

const ExtMachInst StaticInst::machInst

The binary machine instruction.

Definition at line 218 of file static_inst.hh.

Referenced by ArmISA::ArmStaticInst::advSIMDFPAccessTrap64(), ArmISA::ArmStaticInst::ArmStaticInst(), ArmISA::BranchImmCond::BranchImmCond(), ArmISA::BranchRegCond::BranchRegCond(), ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), GenericISA::BasicDecodeCache::decode(), ArmISA::ArmStaticInst::disabledFault(), DecoderFaultInst::execute(), FailUnimplemented::execute(), McrMrcMiscInst::execute(), Minor::FUPipeline::findTiming(), UnknownOp64::generateDisassembly(), ArmISA::PredImmOp::generateDisassembly(), ArmISA::PredIntOp::generateDisassembly(), UnknownOp::generateDisassembly(), X86ISA::MacroopBase::getExtMachInst(), AlphaISA::DtbFault::invoke(), X86ISA::InvalidOpcode::invoke(), RiscvISA::UnknownInstFault::invoke_se(), Minor::MinorDynInst::minorTraceInst(), ArmISA::VfpMacroOp::nextIdxs(), ArmISA::PredOp::PredOp(), BaseSimpleCPU::preExecute(), ArmISA::ArmStaticInst::printMnemonic(), Trace::InstPBTrace::traceInst(), ArmISA::VldMultOp::VldMultOp(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VstMultOp::VstMultOp(), and ArmISA::VstSingleOp::VstSingleOp().

const char* StaticInst::mnemonic

protected

Base mnemonic (e.g., "add").

Used by generateDisassembly() methods. Also useful to readily identify instructions from within the debugger when cachedDisassembly has not been initialized.

Definition at line 233 of file static_inst.hh.

StaticInstPtr StaticInst::nullStaticInstPtr

static

Pointer to a statically allocated "null" instruction object.

Used to give eaCompInst() and memAccInst() something to return when called on non-memory instructions.

Definition at line 197 of file static_inst.hh.

Referenced by BaseSimpleCPU::advancePC(), Checker< Impl >::advancePC(), eaCompInst(), Checker< Impl >::handlePendingInt(), memAccInst(), and Checker< Impl >::verify().

The documentation for this class was generated from the following files:

cpu/static_inst.hh
cpu/static_inst.cc

Public Types

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Static Public Attributes

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Protected Attributes

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