42 #include "arch/registers.hh"
44 #include "debug/MinorScoreboard.hh"
45 #include "debug/MinorTiming.hh"
63 scoreboard_index =
reg;
121 unsigned int num_dests = staticInst->
numDestRegs();
124 for (
unsigned int dest_index = 0; dest_index < num_dests;
128 staticInst->
destRegIdx(dest_index), thread_context);
132 if (mark_unpredictable)
135 inst->flatDestRegIdx[dest_index] =
reg;
146 DPRINTF(MinorScoreboard,
"Marking up inst: %s"
147 " regIndex: %d final numResults: %d returnCycle: %d\n",
166 unsigned int num_srcs = staticInst->
numSrcRegs();
168 for (
unsigned int src_index = 0; src_index < num_srcs; src_index++) {
171 unsigned short int index;
179 DPRINTF(MinorScoreboard,
"Inst: %s depends on execSeqNum: %d\n",
192 unsigned int num_dests = staticInst->
numDestRegs();
195 for (
unsigned int dest_index = 0; dest_index < num_dests;
213 DPRINTF(MinorScoreboard,
"Clearing inst: %s"
214 " regIndex: %d final numResults: %d\n",
231 unsigned int num_srcs = staticInst->
numSrcRegs();
236 unsigned int num_relative_latencies = 0;
242 if (src_reg_relative_latencies &&
243 src_reg_relative_latencies->size() != 0)
245 num_relative_latencies = src_reg_relative_latencies->size();
246 default_relative_latency = (*src_reg_relative_latencies)
247 [num_relative_latencies-1];
251 unsigned int src_index = 0;
252 while (src_index < num_srcs &&
257 unsigned short int index;
261 cant_forward_from_fu_indices &&
262 index < cant_forward_from_fu_indices->size() &&
263 (*cant_forward_from_fu_indices)[
index];
266 (src_index >= num_relative_latencies ?
267 default_relative_latency :
268 (*src_reg_relative_latencies)[src_index]));
270 if (
returnCycle[index] > (now + relative_latency) ||
279 if (
DTRACE(MinorTiming)) {
280 if (ret && num_srcs > num_relative_latencies &&
281 num_relative_latencies != 0)
283 DPRINTF(MinorTiming,
"Warning, inst: %s timing extra decode has"
284 " more src. regs: %d than relative latencies: %d\n",
285 staticInst->
disassemble(0), num_srcs, num_relative_latencies);
295 std::ostringstream result_stream;
297 bool printed_element =
false;
302 unsigned short int num_unpredictable_results =
305 if (!(num_results == 0 && num_unpredictable_results ==
Cycles(0))) {
307 result_stream <<
',';
309 result_stream <<
'(' << i <<
','
310 << num_results <<
'/'
311 << num_unpredictable_results <<
'/'
315 printed_element =
true;
std::vector< Index > numUnpredictableResults
Count of the number of results which can't be predicted.
Cycles is a wrapper class for representing cycle counts, i.e.
virtual const std::string & disassemble(Addr pc, const SymbolTable *symtab=0) const
Return string representation of disassembled instruction.
unsigned short int Index
Type to use when indexing numResults.
RegClass
Enumerate the classes of registers.
RegIndex destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
ThreadContext is the external interface to all thread state for anything outside of the CPU...
virtual int flattenFloatIndex(int reg)=0
static TheISA::RegIndex flattenRegIndex(TheISA::RegIndex reg, ThreadContext *thread_context)
Flatten a RegIndex, irrespective of what reg type it's pointing to.
void minorTrace() const
MinorTraceIF interface.
std::vector< int > fuIndices
Index of the FU generating this result.
std::vector< InstSeqNum > writingInst
The execute sequence number of the most recent inst to generate this register value.
void clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable)
Clear down the dependencies for this instruction.
void markupInstDests(MinorDynInstPtr inst, Cycles retire_time, ThreadContext *thread_context, bool mark_unpredictable)
Mark up an instruction's effects by incrementing numResults counts.
A simple instruction scoreboard for tracking dependencies in Execute.
bool canInstIssue(MinorDynInstPtr inst, const std::vector< Cycles > *src_reg_relative_latencies, const std::vector< bool > *cant_forward_from_fu_indices, Cycles now, ThreadContext *thread_context)
Can this instruction be issued.
InstSeqNum execSeqNumToWaitFor(MinorDynInstPtr inst, ThreadContext *thread_context)
Returns the exec sequence number of the most recent inst on which the given inst depends.
virtual int flattenIntIndex(int reg)=0
RegIndex srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
int8_t numSrcRegs() const
Number of source registers.
virtual int flattenCCIndex(int reg)=0
std::vector< Index > numResults
Count of the number of in-flight instructions that have results for each register.
bool findIndex(RegIndex reg, Index &scoreboard_index)
Sets scoreboard_index to the index into numResults of the given register index.
#define MINORTRACE(...)
DPRINTFN for MinorTrace reporting.
TheISA::RegIndex RegIndex
Type to use for thread context registers.
RegClass regIdxToClass(TheISA::RegIndex reg_idx, TheISA::RegIndex *rel_reg_idx=NULL)
Map a 'unified' architectural register index to its register class.
std::vector< Cycles > returnCycle
The estimated cycle number that the result will be presented.
const unsigned numRegs
The number of registers in the Scoreboard.
int8_t numDestRegs() const
Number of destination registers.