Minor contains all the definitions within the MinorCPU apart from the CPU class itself. More...

Classes
class	MinorActivityRecorder
	ActivityRecorder with a Ticked interface. More...

class	ReportIF
	Interface class for data with reporting/tracing facilities. More...

class	BubbleIF
	Interface class for data with 'bubble' values. More...

class	ReportTraitsAdaptor
	...ReportTraits are trait classes with the same functionality as ReportIF, but with elements explicitly passed into the report... More...

class	ReportTraitsPtrAdaptor
	A similar adaptor but for elements held by pointer ElemType should implement ReportIF. More...

class	NoBubbleTraits
	... More...

class	BubbleTraitsAdaptor
	Pass on call to the element. More...

class	BubbleTraitsPtrAdaptor
	Pass on call to the element where the element is a pointer. More...

class	MinorBuffer
	TimeBuffer with MinorTrace and Named interfaces. More...

class	Latch
	Wraps a MinorBuffer with Input/Output interfaces to ensure that units within the model can only see the right end of buffers between them. More...

class	SelfStallingPipeline
	A pipeline simulating class that will stall (not advance when advance() is called) if a non-bubble value lies at the far end of the pipeline. More...

class	Reservable
	Base class for space reservation requestable objects. More...

class	Queue
	Wrapper for a queue type to act as a pipeline stage input queue. More...

class	InputBuffer
	Like a Queue but with a restricted interface and a setTail function which, when the queue is empty, just takes a reference to the pushed item as the single element. More...

class	Decode

class	InstId
	Id for lines and instructions. More...

class	MinorDynInst
	Dynamic instruction for Minor. More...

class	ExecContext
	ExecContext bears the exec_context interface for Minor. More...

class	Execute
	Execute stage. More...

class	Fetch1
	A stage responsible for fetching "lines" from memory and passing them to Fetch2. More...

class	Fetch2
	This stage receives lines of data from Fetch1, separates them into instructions and passes them to Decode. More...

class	QueuedInst
	Container class to box instructions in the FUs to make those queues have correct bubble behaviour when stepped. More...

class	FUPipeline
	A functional unit configured from a MinorFU object. More...

class	LSQ

class	BranchData
	Forward data betwen Execute and Fetch1 carrying change-of-address/stream information. More...

class	ForwardLineData
	Line fetch data in the forward direction. More...

class	ForwardInstData
	Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appropriate to the configured stage widths. More...

class	Pipeline
	The constructed pipeline. More...

class	Scoreboard
	A scoreboard of register dependencies including, for each register: The number of in-flight instructions which will generate a result for this register. More...

class	MinorStats
	Currently unused stats class. More...

Typedefs
typedef SimpleThread	MinorThread
	Minor will use the SimpleThread state for now. More...

typedef RefCountingPtr < MinorDynInst >	MinorDynInstPtr
	MinorDynInsts are currently reference counted. More...

typedef SelfStallingPipeline < QueuedInst, ReportTraitsAdaptor < QueuedInst > >	FUPipelineBase
	Functional units have pipelines which stall when an inst gets to their ends allowing Execute::commit to pick up timing-completed insts when it feels like it. More...

Functions
std::ostream &	operator<< (std::ostream &os, const InstId &id)
	Print this id in the usual slash-separated format expected by MinorTrace. More...

std::ostream &	operator<< (std::ostream &os, const MinorDynInst &inst)
	Print a short reference to this instruction. More...

static void	printRegName (std::ostream &os, TheISA::RegIndex reg)
	Print a register in the form r<n>, f<n>, m<n>(<name>), z for integer, float, misc and zero registers given an 'architectural register number'. More...

unsigned int	cyclicIndexInc (unsigned int index, unsigned int cycle_size)
	Increment a cyclic buffer index for indices [0, cycle_size-1]. More...

unsigned int	cyclicIndexDec (unsigned int index, unsigned int cycle_size)
	Decrement a cyclic buffer index for indices [0, cycle_size-1]. More...

std::ostream &	operator<< (std::ostream &os, Execute::DrainState state)

std::ostream &	operator<< (std::ostream &os, Fetch1::IcacheState state)

std::ostream &	operator<< (std::ostream &os, Fetch1::FetchState state)

static Addr	addrBlockOffset (Addr addr, unsigned int block_size)
	Returns the offset of addr into an aligned a block of size block_size. More...

static bool	transferNeedsBurst (Addr addr, unsigned int size, unsigned int block_size)
	Returns true if the given [addr . More...

std::ostream &	operator<< (std::ostream &os, LSQ::AddrRangeCoverage coverage)

std::ostream &	operator<< (std::ostream &os, LSQ::LSQRequest::LSQRequestState state)

PacketPtr	makePacketForRequest (Request &request, bool isLoad, Packet::SenderState *sender_state=NULL, PacketDataPtr data=NULL)
	Make a suitable packet for the given request. More...

std::ostream &	operator<< (std::ostream &os, LSQ::MemoryState state)

std::ostream &	operator<< (std::ostream &os, BranchData::Reason reason)
	Print a branch reason enum. More...

std::ostream &	operator<< (std::ostream &os, const BranchData &branch)
	Print BranchData contents in a format suitable for DPRINTF comments, not for MinorTrace. More...

static TheISA::RegIndex	flattenRegIndex (TheISA::RegIndex reg, ThreadContext *thread_context)
	Flatten a RegIndex, irrespective of what reg type it's pointing to. More...

Variables
const unsigned int	MAX_FORWARD_INSTS = 16
	Maximum number of instructions that can be carried by the pipeline. More...

Detailed Description

Minor contains all the definitions within the MinorCPU apart from the CPU class itself.

Typedef Documentation

typedef SelfStallingPipeline<QueuedInst, ReportTraitsAdaptor<QueuedInst> > Minor::FUPipelineBase

Functional units have pipelines which stall when an inst gets to their ends allowing Execute::commit to pick up timing-completed insts when it feels like it.

Definition at line 221 of file func_unit.hh.

typedef RefCountingPtr<MinorDynInst> Minor::MinorDynInstPtr

MinorDynInsts are currently reference counted.

Definition at line 63 of file dyn_inst.hh.

typedef SimpleThread Minor::MinorThread

Minor will use the SimpleThread state for now.

Definition at line 60 of file cpu.hh.

Function Documentation

static Addr Minor::addrBlockOffset	(	Addr	addr,
		unsigned int	block_size
	)

static

Returns the offset of addr into an aligned a block of size block_size.

Definition at line 59 of file lsq.cc.

Referenced by Minor::LSQ::SplitDataRequest::makeFragmentRequests(), and transferNeedsBurst().

unsigned int Minor::cyclicIndexDec	(	unsigned int	index,
		unsigned int	cycle_size
	)

inline

Decrement a cyclic buffer index for indices [0, cycle_size-1].

Definition at line 512 of file execute.cc.

unsigned int Minor::cyclicIndexInc	(	unsigned int	index,
		unsigned int	cycle_size
	)

inline

Increment a cyclic buffer index for indices [0, cycle_size-1].

Definition at line 500 of file execute.cc.

static TheISA::RegIndex Minor::flattenRegIndex	(	TheISA::RegIndex	reg,
		ThreadContext *	thread_context
	)

static

Flatten a RegIndex, irrespective of what reg type it's pointing to.

Definition at line 87 of file scoreboard.cc.

References CCRegClass, ThreadContext::flattenCCIndex(), ThreadContext::flattenFloatIndex(), ThreadContext::flattenIntIndex(), FloatRegClass, IntRegClass, MiscRegClass, X86ISA::reg, and regIdxToClass().

Referenced by Minor::Scoreboard::canInstIssue(), Minor::Scoreboard::execSeqNumToWaitFor(), and Minor::Scoreboard::markupInstDests().

PacketPtr Minor::makePacketForRequest	(	Request &	request,
		bool	isLoad,
		Packet::SenderState *	sender_state = `NULL`,
		PacketDataPtr	data = `NULL`
	)

Make a suitable packet for the given request.

If the request is a store, data will be the payload data. If sender_state is NULL, it won't be pushed into the packet as senderState

Definition at line 1555 of file lsq.cc.

References Packet::allocate(), Packet::createRead(), Packet::createWrite(), Packet::dataDynamic(), and Packet::pushSenderState().

Referenced by Minor::LSQ::SplitDataRequest::makeFragmentPackets(), and Minor::LSQ::LSQRequest::makePacket().

std::ostream & Minor::operator<<	(	std::ostream &	os,
		BranchData::Reason	reason
	)

Print a branch reason enum.

Definition at line 46 of file pipe_data.cc.

References Minor::BranchData::BadlyPredictedBranch, Minor::BranchData::BadlyPredictedBranchTarget, Minor::BranchData::BranchPrediction, Minor::BranchData::CorrectlyPredictedBranch, Minor::BranchData::HaltFetch, Minor::BranchData::Interrupt, Minor::BranchData::NoBranch, X86ISA::os, Minor::BranchData::SuspendThread, and Minor::BranchData::UnpredictedBranch.

std::ostream & Minor::operator<<	(	std::ostream &	os,
		const InstId &	id
	)

Print this id in the usual slash-separated format expected by MinorTrace.

Definition at line 63 of file dyn_inst.cc.

References X86ISA::os.

std::ostream & Minor::operator<<	(	std::ostream &	os,
		const MinorDynInst &	inst
	)

Print a short reference to this instruction.

Print a summary of the instruction.

'-' for a bubble and a series of '/' separated sequence numbers for other instructions. The sequence numbers will be in the order: stream, prediction, line, fetch, exec with exec absent if it is 0. This is used by MinorTrace.

Definition at line 116 of file dyn_inst.cc.

References Minor::MinorDynInst::fault, StaticInst::getName(), Minor::MinorDynInst::id, Minor::MinorDynInst::isFault(), X86ISA::os, Minor::MinorDynInst::pc, and Minor::MinorDynInst::staticInst.

std::ostream & Minor::operator<<	(	std::ostream &	os,
		const BranchData &	branch
	)

Print BranchData contents in a format suitable for DPRINTF comments, not for MinorTrace.

Definition at line 153 of file pipe_data.cc.

References Minor::BranchData::inst, Minor::BranchData::newPredictionSeqNum, Minor::BranchData::newStreamSeqNum, X86ISA::os, Minor::BranchData::reason, and Minor::BranchData::target.

std::ostream& Minor::operator<<	(	std::ostream &	os,
		LSQ::AddrRangeCoverage	coverage
	)

Definition at line 154 of file lsq.cc.

References Minor::LSQ::FullAddrRangeCoverage, Minor::LSQ::NoAddrRangeCoverage, X86ISA::os, and Minor::LSQ::PartialAddrRangeCoverage.

std::ostream& Minor::operator<<	(	std::ostream &	os,
		LSQ::LSQRequest::LSQRequestState	state
	)

Definition at line 174 of file lsq.cc.

References Minor::LSQ::LSQRequest::Complete, Minor::LSQ::LSQRequest::Failed, Minor::LSQ::LSQRequest::InTranslation, Minor::LSQ::LSQRequest::NotIssued, X86ISA::os, Minor::LSQ::LSQRequest::RequestIssuing, Minor::LSQ::LSQRequest::RequestNeedsRetry, Minor::LSQ::state, Minor::LSQ::LSQRequest::StoreBufferIssuing, Minor::LSQ::LSQRequest::StoreBufferNeedsRetry, Minor::LSQ::LSQRequest::StoreInStoreBuffer, Minor::LSQ::LSQRequest::StoreToStoreBuffer, and Minor::LSQ::LSQRequest::Translated.

std::ostream& Minor::operator<<	(	std::ostream &	os,
		Fetch1::IcacheState	state
	)

Definition at line 211 of file fetch1.cc.

References Minor::Fetch1::IcacheNeedsRetry, Minor::Fetch1::IcacheRunning, and X86ISA::os.

std::ostream& Minor::operator<<	(	std::ostream &	os,
		Fetch1::FetchState	state
	)

Definition at line 468 of file fetch1.cc.

References Minor::Fetch1::FetchHalted, Minor::Fetch1::FetchRunning, Minor::Fetch1::FetchWaitingForPC, and X86ISA::os.

std::ostream& Minor::operator<<	(	std::ostream &	os,
		LSQ::MemoryState	state
	)

Definition at line 1605 of file lsq.cc.

References Minor::LSQ::MemoryNeedsRetry, Minor::LSQ::MemoryRunning, X86ISA::os, and Minor::LSQ::state.

std::ostream& Minor::operator<<	(	std::ostream &	os,
		Execute::DrainState	state
	)

Definition at line 1764 of file execute.cc.

References Minor::Execute::DrainAllInsts, Minor::Execute::DrainCurrentInst, Minor::Execute::DrainHaltFetch, Minor::Execute::NotDraining, and X86ISA::os.

static void Minor::printRegName	(	std::ostream &	os,
		TheISA::RegIndex	reg
	)

static

Print a register in the form r<n>, f<n>, m<n>(<name>), z for integer, float, misc and zero registers given an 'architectural register number'.

Definition at line 136 of file dyn_inst.cc.

References AlphaISA::CC_Reg_Base, CCRegClass, FloatRegClass, AlphaISA::FP_Reg_Base, IntRegClass, AlphaISA::Misc_Reg_Base, MiscRegClass, ArmISA::miscRegName, X86ISA::reg, regIdxToClass(), and AlphaISA::ZeroReg.

Referenced by Minor::MinorDynInst::minorTraceInst().

static bool Minor::transferNeedsBurst	(	Addr	addr,
		unsigned int	size,
		unsigned int	block_size
	)

static

Returns true if the given [addr .

. addr+size-1] transfer needs to be fragmented across a block size of block_size

Definition at line 67 of file lsq.cc.

References addrBlockOffset().

Referenced by Minor::LSQ::pushRequest().

Variable Documentation

const unsigned int Minor::MAX_FORWARD_INSTS = 16

Maximum number of instructions that can be carried by the pipeline.

Definition at line 250 of file pipe_data.hh.

Referenced by Minor::ForwardInstData::resize().

Classes

Typedefs

Functions

Variables

Detailed Description

Typedef Documentation

Function Documentation

Variable Documentation