47 #ifndef __CPU_MINOR_FETCH1_HH__
48 #define __CPU_MINOR_FETCH1_HH__
383 Fetch1(
const std::string &name_,
385 MinorCPUParams ¶ms,
void processResponse(FetchRequestPtr response, ForwardLineData &line)
Convert a response to a ForwardLineData.
std::vector< Fetch1ThreadInfo > fetchInfo
MinorCPU & cpu
The enclosing cpu.
IcacheState
State of memory access for head instruction fetch.
InstSeqNum predictionSeqNum
Prediction sequence number.
const std::string & name() const
decltype(nullptr) constexpr NoFault
Top level definition of the Minor in-order CPU model.
Contains class definitions for data flowing between pipeline stages in the top-level structure portio...
void fetchLine(ThreadID tid)
Insert a line fetch into the requests.
void stepQueues()
Step requests along between requests and transfers queues.
bool tryToSend(FetchRequestPtr request)
Try to send (or resend) a memory request's next/only packet to the memory system. ...
FetchRequestState
Progress of this request through address translation and memory.
const std::string name() const
Return port name (for DPRINTF).
Queue< FetchRequestPtr, ReportTraitsPtrAdaptor< FetchRequestPtr >, NoBubbleTraits< FetchRequestPtr > > FetchQueue
std::vector< InputBuffer< ForwardLineData > > & nextStageReserve
Interface to reserve space in the next stage.
unsigned int lineSnap
Line snap size in bytes.
unsigned int numFetchesInMemorySystem
Count of the number fetches which have left the transfers queue and are in the 'wild' in the memory s...
InstId id
Identity of the line that this request will generate.
void popAndDiscard(FetchQueue &queue)
Pop a request from the given queue and correctly deallocate and discard it.
void changeStream(const BranchData &branch)
Start fetching from a new address.
void updateExpectedSeqNums(const BranchData &branch)
Update streamSeqNum and predictionSeqNum from the given branch (and assume these have changed and dis...
Line fetch data in the forward direction.
Stage cycle-by-cycle state.
bool isDiscardable() const
Is this line out of date with the current stream/prediction sequence and can it be discarded without ...
IcacheState icacheState
Retry state of icache_port.
TheISA::PCState pc
PC to fixup with line address.
Fetch1ThreadInfo(const Fetch1ThreadInfo &other)
Id for lines and instructions.
MinorCPUPort(const std::string &name_, MinorCPU &cpu_)
Fetch1(const std::string &name_, MinorCPU &cpu_, MinorCPUParams ¶ms, Latch< BranchData >::Output inp_, Latch< ForwardLineData >::Input out_, Latch< BranchData >::Output prediction_, std::vector< InputBuffer< ForwardLineData >> &next_stage_input_buffer)
Latch< BranchData >::Output inp
Input port carrying branch requests from Execute.
Wrapper for a queue type to act as a pipeline stage input queue.
ThreadContext is the external interface to all thread state for anything outside of the CPU...
void handleTLBResponse(FetchRequestPtr response)
Handle pushing a TLB response onto the right queue.
MinorCPU & cpu
Construction-assigned data members.
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
bool blocked
Blocked indication for report.
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the slave port.
void markDelayed()
BaseTLB::Translation interface.
A similar adaptor but for elements held by pointer ElemType should implement ReportIF.
FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_)
MinorCPU::MinorCPUPort & getIcachePort()
Returns the IcachePort owned by this Fetch1.
void reportData(std::ostream &os) const
Report interface.
FetchRequest * FetchRequestPtr
bool wakeupGuard
Signal to guard against sleeping first cycle of wakeup.
Latch< BranchData >::Output prediction
Input port carrying branch predictions from Fetch2.
bool isComplete() const
Is this a complete read line or fault.
FetchQueue requests
Queue of address translated requests from Fetch1.
void moveFromRequestsToTransfers(FetchRequestPtr request)
Move a request between queues.
Request request
The underlying request that this fetch represents.
Latch< ForwardLineData >::Input out
Output port carrying read lines to Fetch2.
Classes for buffer, queue and FIFO behaviour.
unsigned int numFetchesInITLB
Number of requests inside the ITLB rather than in the queues.
unsigned int numInFlightFetches()
Returns the total number of queue occupancy, in-ITLB and in-memory system fetches.
void makePacket()
Make a packet to use with the memory transaction.
A stage responsible for fetching "lines" from memory and passing them to Fetch2.
InstSeqNum streamSeqNum
Stream sequence number.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
FetchState
Cycle-by-cycle state.
A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a MemObject that sees the packet.
Fault fault
Fill in a fault if one happens during fetch, check this by picking apart the response packet...
unsigned int maxLineWidth
Maximum fetch width in bytes.
friend std::ostream & operator<<(std::ostream &os, Fetch1::FetchState state)
int16_t ThreadID
Thread index/ID type.
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
Fetch1ThreadInfo()
Consturctor to initialize all fields.
void finish(const Fault &fault_, RequestPtr request_, ThreadContext *tc, BaseTLB::Mode mode)
Interface for ITLB responses.
Declaration of the Packet class.
TheISA::PCState pc
Fetch PC value.
virtual bool recvTimingResp(PacketPtr pkt)
Memory interface.
void recvReqRetry()
Called by the slave port if sendTimingReq was called on this master port (causing recvTimingReq to be...
GenericISA::SimplePCState< MachInst > PCState
IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu)
void wakeupFetch(ThreadID tid)
Initiate fetch1 fetching.
void tryToSendToTransfers(FetchRequestPtr request)
Try and issue a fetch for a translated request at the head of the requests queue. ...
bool isDrained()
Is this stage drained? For Fetch1, draining is initiated by Execute signalling a branch with the reas...
InstSeqNum lineSeqNum
Sequence number for line fetch used for ordering lines to flush.
PacketPtr packet
FetchRequests carry packets while they're in the requests and transfers responses queues...
MinorCPU is an in-order CPU model with four fixed pipeline stages:
void evaluate()
Pass on input/buffer data to the output if you can.
FetchQueue transfers
Queue of in-memory system requests and responses.
IcachePort icachePort
IcachePort to pass to the CPU.
std::shared_ptr< FaultBase > Fault
unsigned int fetchLimit
Maximum number of fetches allowed in flight (in queues or memory)
void minorTraceResponseLine(const std::string &name, FetchRequestPtr response) const
Print the appropriate MinorLine line for a fetch response.
Fetch1 & fetch
Owning fetch unit.
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to fetch from.
virtual void recvReqRetry()