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fetch1.hh
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37  * Authors: Andrew Bardsley
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39 
47 #ifndef __CPU_MINOR_FETCH1_HH__
48 #define __CPU_MINOR_FETCH1_HH__
49 
50 #include "cpu/minor/buffers.hh"
51 #include "cpu/minor/cpu.hh"
52 #include "cpu/minor/pipe_data.hh"
53 #include "cpu/base.hh"
54 #include "mem/packet.hh"
55 
56 namespace Minor
57 {
58 
61 class Fetch1 : public Named
62 {
63  protected:
66  {
67  protected:
70 
71  public:
72  IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) :
73  MinorCPU::MinorCPUPort(name, cpu), fetch(fetch_)
74  { }
75 
76  protected:
78  { return fetch.recvTimingResp(pkt); }
79 
81  };
82 
101  class FetchRequest :
102  public BaseTLB::Translation, /* For TLB lookups */
103  public Packet::SenderState /* For packing into a Packet */
104  {
105  protected:
108 
109  public:
113  {
114  NotIssued, /* Just been made */
115  InTranslation, /* Issued to ITLB, must wait for reqply */
116  Translated, /* Translation complete */
117  RequestIssuing, /* Issued to memory, must wait for response */
118  Complete /* Complete. Either a fault, or a fetched line */
119  };
120 
122 
125 
131 
134 
137 
141 
143  void makePacket();
144 
146  void reportData(std::ostream &os) const;
147 
151  bool isDiscardable() const;
152 
154  bool isComplete() const { return state == Complete; }
155 
156  protected:
161  void markDelayed() { }
162 
166  void finish(const Fault &fault_, RequestPtr request_,
168 
169  public:
171  SenderState(),
172  fetch(fetch_),
173  state(NotIssued),
174  id(id_),
175  packet(NULL),
176  request(),
177  pc(pc_),
178  fault(NoFault)
179  { }
180 
181  ~FetchRequest();
182  };
183 
185 
186  protected:
191 
198 
201 
205 
209  unsigned int lineSnap;
210 
215  unsigned int maxLineWidth;
216 
218  unsigned int fetchLimit;
219 
220  protected:
225  {
226  FetchHalted, /* Not fetching, waiting to be woken by transition
227  to FetchWaitingForPC. The PC is not valid in this state */
228  FetchWaitingForPC, /* Not fetching, waiting for stream change.
229  This doesn't stop issued fetches from being returned and
230  processed or for branches to change the state to Running. */
231  FetchRunning /* Try to fetch, when possible */
232  };
233 
237 
241  pc(TheISA::PCState(0)),
242  streamSeqNum(InstId::firstStreamSeqNum),
243  predictionSeqNum(InstId::firstPredictionSeqNum),
244  blocked(false),
245  wakeupGuard(false)
246  { }
247 
249  state(other.state),
250  pc(other.pc),
251  streamSeqNum(other.streamSeqNum),
253  blocked(other.blocked)
254  { }
255 
257 
262 
267 
273 
275  bool blocked;
276 
279  };
280 
283 
286  {
287  IcacheRunning, /* Default. Step icache queues when possible */
288  IcacheNeedsRetry /* Request rejected, will be asked to retry */
289  };
290 
291  typedef Queue<FetchRequestPtr,
295 
298 
301 
304 
307 
316  unsigned int numFetchesInITLB;
317 
318  protected:
319  friend std::ostream &operator <<(std::ostream &os,
320  Fetch1::FetchState state);
321 
323  void changeStream(const BranchData &branch);
324 
328  void updateExpectedSeqNums(const BranchData &branch);
329 
331  void processResponse(FetchRequestPtr response,
332  ForwardLineData &line);
333 
334  friend std::ostream &operator <<(std::ostream &os,
335  IcacheState state);
336 
337 
341 
345  void fetchLine(ThreadID tid);
346 
351 
355  bool tryToSend(FetchRequestPtr request);
356 
359 
361  void stepQueues();
362 
365  void popAndDiscard(FetchQueue &queue);
366 
368  void handleTLBResponse(FetchRequestPtr response);
369 
372  unsigned int numInFlightFetches();
373 
375  void minorTraceResponseLine(const std::string &name,
376  FetchRequestPtr response) const;
377 
379  virtual bool recvTimingResp(PacketPtr pkt);
380  virtual void recvReqRetry();
381 
382  public:
383  Fetch1(const std::string &name_,
384  MinorCPU &cpu_,
385  MinorCPUParams &params,
388  Latch<BranchData>::Output prediction_,
389  std::vector<InputBuffer<ForwardLineData>> &next_stage_input_buffer);
390 
391  public:
394 
396  void evaluate();
397 
399  void wakeupFetch(ThreadID tid);
400 
401  void minorTrace() const;
402 
405  bool isDrained();
406 };
407 
408 }
409 
410 #endif /* __CPU_MINOR_FETCH1_HH__ */
ThreadID threadPriority
Definition: fetch1.hh:282
Exposable fetch port.
Definition: fetch1.hh:65
void processResponse(FetchRequestPtr response, ForwardLineData &line)
Convert a response to a ForwardLineData.
Definition: fetch1.cc:538
std::vector< Fetch1ThreadInfo > fetchInfo
Definition: fetch1.hh:281
MinorCPU & cpu
The enclosing cpu.
Definition: cpu.hh:104
IcacheState
State of memory access for head instruction fetch.
Definition: fetch1.hh:285
InstSeqNum predictionSeqNum
Prediction sequence number.
Definition: fetch1.hh:272
const std::string & name() const
Definition: trace.hh:149
decltype(nullptr) constexpr NoFault
Definition: types.hh:189
Top level definition of the Minor in-order CPU model.
Contains class definitions for data flowing between pipeline stages in the top-level structure portio...
void fetchLine(ThreadID tid)
Insert a line fetch into the requests.
Definition: fetch1.cc:148
Like a Queue but with a restricted interface and a setTail function which, when the queue is empty...
Definition: buffers.hh:563
void stepQueues()
Step requests along between requests and transfers queues.
Definition: fetch1.cc:358
Memory access queuing.
Definition: fetch1.hh:101
bool tryToSend(FetchRequestPtr request)
Try to send (or resend) a memory request's next/only packet to the memory system. ...
Definition: fetch1.cc:330
FetchRequestState
Progress of this request through address translation and memory.
Definition: fetch1.hh:112
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:99
Queue< FetchRequestPtr, ReportTraitsPtrAdaptor< FetchRequestPtr >, NoBubbleTraits< FetchRequestPtr > > FetchQueue
Definition: fetch1.hh:294
std::vector< InputBuffer< ForwardLineData > > & nextStageReserve
Interface to reserve space in the next stage.
Definition: fetch1.hh:200
unsigned int lineSnap
Line snap size in bytes.
Definition: fetch1.hh:209
unsigned int numFetchesInMemorySystem
Count of the number fetches which have left the transfers queue and are in the 'wild' in the memory s...
Definition: fetch1.hh:312
InstId id
Identity of the line that this request will generate.
Definition: fetch1.hh:124
void popAndDiscard(FetchQueue &queue)
Pop a request from the given queue and correctly deallocate and discard it.
Definition: fetch1.cc:380
void changeStream(const BranchData &branch)
Start fetching from a new address.
Definition: fetch1.cc:488
void updateExpectedSeqNums(const BranchData &branch)
Update streamSeqNum and predictionSeqNum from the given branch (and assume these have changed and dis...
Definition: fetch1.cc:520
Line fetch data in the forward direction.
Definition: pipe_data.hh:173
Stage cycle-by-cycle state.
Definition: fetch1.hh:236
bool isDiscardable() const
Is this line out of date with the current stream/prediction sequence and can it be discarded without ...
Definition: fetch1.cc:750
IcacheState icacheState
Retry state of icache_port.
Definition: fetch1.hh:303
TheISA::PCState pc
PC to fixup with line address.
Definition: fetch1.hh:136
Fetch1ThreadInfo(const Fetch1ThreadInfo &other)
Definition: fetch1.hh:248
Id for lines and instructions.
Definition: dyn_inst.hh:70
MinorCPUPort(const std::string &name_, MinorCPU &cpu_)
Definition: cpu.hh:107
Fetch1(const std::string &name_, MinorCPU &cpu_, MinorCPUParams &params, Latch< BranchData >::Output inp_, Latch< ForwardLineData >::Input out_, Latch< BranchData >::Output prediction_, std::vector< InputBuffer< ForwardLineData >> &next_stage_input_buffer)
Definition: fetch1.cc:55
Latch< BranchData >::Output inp
Input port carrying branch requests from Execute.
Definition: fetch1.hh:193
Bitfield< 4, 0 > mode
Definition: miscregs.hh:1385
Fetch1 & fetch
My owner.
Definition: fetch1.hh:69
Wrapper for a queue type to act as a pipeline stage input queue.
Definition: buffers.hh:393
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Bitfield< 17 > os
Definition: misc.hh:804
STL vector class.
Definition: stl.hh:40
void handleTLBResponse(FetchRequestPtr response)
Handle pushing a TLB response onto the right queue.
Definition: fetch1.cc:253
MinorCPU & cpu
Construction-assigned data members.
Definition: fetch1.hh:190
Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Exe...
Definition: cpu.hh:100
bool blocked
Blocked indication for report.
Definition: fetch1.hh:275
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the slave port.
Definition: fetch1.hh:77
Definition: trace.hh:140
void markDelayed()
BaseTLB::Translation interface.
Definition: fetch1.hh:161
void minorTrace() const
Definition: fetch1.cc:761
A similar adaptor but for elements held by pointer ElemType should implement ReportIF.
Definition: buffers.hh:103
FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_)
Definition: fetch1.hh:170
MinorCPU::MinorCPUPort & getIcachePort()
Returns the IcachePort owned by this Fetch1.
Definition: fetch1.hh:393
void reportData(std::ostream &os) const
Report interface.
Definition: fetch1.cc:745
FetchRequest * FetchRequestPtr
Definition: fetch1.hh:184
bool wakeupGuard
Signal to guard against sleeping first cycle of wakeup.
Definition: fetch1.hh:278
Latch< BranchData >::Output prediction
Input port carrying branch predictions from Fetch2.
Definition: fetch1.hh:197
bool isComplete() const
Is this a complete read line or fault.
Definition: fetch1.hh:154
FetchQueue requests
Queue of address translated requests from Fetch1.
Definition: fetch1.hh:297
void moveFromRequestsToTransfers(FetchRequestPtr request)
Move a request between queues.
Definition: fetch1.cc:321
uint64_t InstSeqNum
Definition: inst_seq.hh:40
Request request
The underlying request that this fetch represents.
Definition: fetch1.hh:133
Latch< ForwardLineData >::Input out
Output port carrying read lines to Fetch2.
Definition: fetch1.hh:195
Classes for buffer, queue and FIFO behaviour.
unsigned int numFetchesInITLB
Number of requests inside the ITLB rather than in the queues.
Definition: fetch1.hh:316
unsigned int numInFlightFetches()
Returns the total number of queue occupancy, in-ITLB and in-memory system fetches.
Definition: fetch1.cc:389
void makePacket()
Make a packet to use with the memory transaction.
Definition: fetch1.cc:228
A stage responsible for fetching "lines" from memory and passing them to Fetch2.
Definition: fetch1.hh:61
InstSeqNum streamSeqNum
Stream sequence number.
Definition: fetch1.hh:266
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:245
FetchState
Cycle-by-cycle state.
Definition: fetch1.hh:224
A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a MemObject that sees the packet.
Definition: packet.hh:377
Fault fault
Fill in a fault if one happens during fetch, check this by picking apart the response packet...
Definition: fetch1.hh:140
unsigned int maxLineWidth
Maximum fetch width in bytes.
Definition: fetch1.hh:215
FetchRequestState state
Definition: fetch1.hh:121
Mode
Definition: tlb.hh:61
friend std::ostream & operator<<(std::ostream &os, Fetch1::FetchState state)
Definition: fetch1.cc:468
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:171
Forward data betwen Execute and Fetch1 carrying change-of-address/stream information.
Definition: pipe_data.hh:64
Fetch1ThreadInfo()
Consturctor to initialize all fields.
Definition: fetch1.hh:239
void finish(const Fault &fault_, RequestPtr request_, ThreadContext *tc, BaseTLB::Mode mode)
Interface for ITLB responses.
Definition: fetch1.cc:240
Declaration of the Packet class.
TheISA::PCState pc
Fetch PC value.
Definition: fetch1.hh:261
virtual bool recvTimingResp(PacketPtr pkt)
Memory interface.
Definition: fetch1.cc:416
void recvReqRetry()
Called by the slave port if sendTimingReq was called on this master port (causing recvTimingReq to be...
Definition: fetch1.hh:80
GenericISA::SimplePCState< MachInst > PCState
Definition: types.hh:43
IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu)
Definition: fetch1.hh:72
void wakeupFetch(ThreadID tid)
Initiate fetch1 fetching.
Definition: fetch1.cc:713
void tryToSendToTransfers(FetchRequestPtr request)
Try and issue a fetch for a translated request at the head of the requests queue. ...
Definition: fetch1.cc:282
bool isDrained()
Is this stage drained? For Fetch1, draining is initiated by Execute signalling a branch with the reas...
Definition: fetch1.cc:727
InstSeqNum lineSeqNum
Sequence number for line fetch used for ordering lines to flush.
Definition: fetch1.hh:306
PacketPtr packet
FetchRequests carry packets while they're in the requests and transfers responses queues...
Definition: fetch1.hh:130
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:79
void evaluate()
Pass on input/buffer data to the output if you can.
Definition: fetch1.cc:572
Encapsulate wires on either input or output of the latch.
Definition: buffers.hh:243
FetchQueue transfers
Queue of in-memory system requests and responses.
Definition: fetch1.hh:300
IcachePort icachePort
IcachePort to pass to the CPU.
Definition: fetch1.hh:204
std::shared_ptr< FaultBase > Fault
Definition: types.hh:184
unsigned int fetchLimit
Maximum number of fetches allowed in flight (in queues or memory)
Definition: fetch1.hh:218
void minorTraceResponseLine(const std::string &name, FetchRequestPtr response) const
Print the appropriate MinorLine line for a fetch response.
Definition: fetch1.cc:397
Fetch1 & fetch
Owning fetch unit.
Definition: fetch1.hh:107
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to fetch from.
Definition: fetch1.cc:116
virtual void recvReqRetry()
Definition: fetch1.cc:453

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