42 #ifndef __CPU_RUBYTEST_RUBYTESTER_HH__
43 #define __CPU_RUBYTEST_RUBYTESTER_HH__
54 #include "params/RubyTester.hh"
82 {
panic(
"%s does not expect a retry\n",
name()); }
116 void print(std::ostream& out)
const;
131 virtual const char *
description()
const {
return "RubyTester tick"; }
172 #endif // __CPU_RUBYTEST_RUBYTESTER_HH__
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
void printConfig(std::ostream &out) const
int m_num_inst_data_ports
const PortID InvalidPortID
int m_num_inst_only_ports
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
MasterPort * getReadableCpuPort(int idx)
const std::string name() const
Return port name (for DPRINTF).
bool isInstOnlyCpuPort(int idx)
std::vector< Cycles > m_last_progress_vector
CheckStartEvent checkStartEvent
RubyTester(const Params *p)
void printStats(std::ostream &out) const
SenderState(Addr addr, int size)
virtual void recvReqRetry()
Called by the slave port if sendTimingReq was called on this master port (causing recvTimingReq to be...
uint64_t m_checks_completed
bool isInstDataCpuPort(int idx)
virtual BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.
RubyTester & operator=(const RubyTester &obj)
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
CheckTable * m_checkTable_ptr
MasterPort * getWritableCpuPort(int idx)
CpuPort(const std::string &_name, RubyTester *_tester, PortID _id, PortID _index)
std::vector< MasterPort * > writePorts
void print(std::ostream &out) const
A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a MemObject that sees the packet.
void hitCallback(NodeID proc, SubBlock *data)
Declaration of the Packet class.
std::ostream & operator<<(std::ostream &out, const RubyTester &obj)
The MemObject class extends the ClockedObject with accessor functions to get its master and slave por...
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
A BaseMasterPort is a protocol-agnostic master port, responsible only for the structural connection t...
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the slave port.
CheckStartEvent(RubyTester *_tester)
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
std::vector< MasterPort * > readPorts
uint64_t m_checks_to_complete
void incrementCheckCompletions()
virtual const char * description() const
Return a C string describing the event.