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Port Class Reference

Ports are used to interface memory objects to each other. More...

#include <port.hh>

Inheritance diagram for Port:
BaseMasterPort BaseSlavePort MasterPort SlavePort AddrMapper::MapperMasterPort AtomicSimpleCPU::AtomicCPUPort BaseKvmCPU::KVMCpuPort Bridge::BridgeMasterPort CoherentXBar::CoherentXBarMasterPort CoherentXBar::SnoopRespPort CommMonitor::MonitorMasterPort ComputeUnit::DataPort ComputeUnit::DTLBPort ComputeUnit::ITLBPort ComputeUnit::LDSPort ComputeUnit::SQCPort DmaPort ExternalMaster::Port FullO3CPU< Impl >::DcachePort FullO3CPU< Impl >::IcachePort GarnetSyntheticTraffic::CpuPort GpuDispatcher::TLBPort MemCheckerMonitor::MonitorMasterPort MemTest::CpuPort MinorCPU::MinorCPUPort NoncoherentXBar::NoncoherentXBarMasterPort QueuedMasterPort RubyDirectedTester::CpuPort RubyTester::CpuPort SerialLink::SerialLinkMasterPort System::SystemPort TimingSimpleCPU::TimingCPUPort TLBCoalescer::MemSidePort TraceCPU::DcachePort TraceCPU::IcachePort TrafficGen::TrafficGenPort X86ISA::GpuTLB::MemSidePort X86ISA::Walker::WalkerPort AddrMapper::MapperSlavePort Bridge::BridgeSlavePort CommMonitor::MonitorSlavePort DRAMSim2::MemoryPort ExternalSlave::Port LdsState::CuSidePort MemCheckerMonitor::MonitorSlavePort QueuedSlavePort SerialLink::SerialLinkSlavePort SimpleMemory::MemoryPort TLBCoalescer::CpuSidePort X86ISA::GpuTLB::CpuSidePort

Public Member Functions

const std::string name () const
 Return port name (for DPRINTF). More...
 
PortID getId () const
 Get the port id. More...
 

Protected Member Functions

 Port (const std::string &_name, MemObject &_owner, PortID _id)
 Abstract base class for ports. More...
 
virtual ~Port ()
 Virtual destructor due to inheritance. More...
 

Protected Attributes

const PortID id
 A numeric identifier to distinguish ports in a vector, and set to InvalidPortID in case this port is not part of a vector. More...
 
MemObjectowner
 A reference to the MemObject that owns this port. More...
 

Private Attributes

std::string portName
 Descriptive name (for DPRINTF output) More...
 

Detailed Description

Ports are used to interface memory objects to each other.

A port is either a master or a slave and the connected peer is always of the opposite role. Each port has a name, an owner, and an identifier.

Definition at line 63 of file port.hh.

Constructor & Destructor Documentation

Port::Port ( const std::string &  _name,
MemObject _owner,
PortID  _id 
)
protected

Abstract base class for ports.

Parameters
_namePort name including the owners name
_ownerThe MemObject that is the structural owner of this port
_idA port identifier for vector ports

Definition at line 54 of file port.cc.

Port::~Port ( )
protectedvirtual

Virtual destructor due to inheritance.

Reimplemented in ExternalMaster::Port, and ExternalSlave::Port.

Definition at line 59 of file port.cc.

Member Function Documentation

PortID Port::getId ( ) const
inline

Get the port id.

Definition at line 102 of file port.hh.

References id.

Referenced by SnoopFilter::portToMask().

const std::string Port::name ( ) const
inline

Member Data Documentation

const PortID Port::id
protected

A numeric identifier to distinguish ports in a vector, and set to InvalidPortID in case this port is not part of a vector.

Definition at line 77 of file port.hh.

Referenced by getId().

MemObject& Port::owner
protected

A reference to the MemObject that owns this port.

Definition at line 80 of file port.hh.

Referenced by AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), and BaseCache::CacheSlavePort::setBlocked().

std::string Port::portName
private

Descriptive name (for DPRINTF output)

Definition at line 69 of file port.hh.

Referenced by name().


The documentation for this class was generated from the following files:

Generated on Fri Jun 9 2017 13:04:17 for gem5 by doxygen 1.8.6