  X86Linux32::__attribute__ | |
| _cl_event | |
 AbstractBloomFilter | |
 BlockBloomFilter | |
| BulkBloomFilter | |
| H3BloomFilter | |
| LSB_CountingBloomFilter | |
| MultiBitSelBloomFilter | |
| MultiGrainBloomFilter | |
 NonCountingBloomFilter | |
| AbstractEntry | |
| AbstractCacheEntry | |
| X86ISA::GpuTLB::AccessInfo | This hash map will use the virtual page address as a key and will keep track of total number of accesses per page |
| BankedArray::AccessRecord | |
| AccessTraceForAddress | |
| ActivityRecorder | ActivityRecorder helper class that informs the CPU if it can switch over to being idle or not |
| Minor::MinorActivityRecorder | ActivityRecorder with a Ticked interface |
| AddressProfiler | |
| DecodeCache::AddrMap< Value > | A sparse map from an Addr to a Value, stored in page chunks |
| DecodeCache::AddrMap< RefCountingPtr > | |
| AddrRange | Encapsulates an address range, and supports a number of tests to check if two ranges intersect, if a range contains a specific address etc |
| AddrRangeMap< V > | The AddrRangeMap uses an STL map to implement an interval tree for address decoding |
| AddrRangeMap< AbstractMemory * > | |
| AddrRangeMap< PortID > | |
| AddrRangeMap< StorageElement * > | |
| AlphaAccess | |
| AlphaBackdoor::Access | |
| AlphaISA::AlphaRequestFlags | Alpha-specific memory request flags |
| AmbaDevice | |
| AmbaDmaDevice | |
| HDLcd | |
| Pl111 | |
| AmbaPioDevice | |
| AmbaFake | |
| AmbaIntDevice | |
| PL031 | |
| Pl050 | |
| Sp804 | |
| Pl011 | |
| PowerISA::AnyReg | |
| ArmISA::AnyReg | |
| AlphaISA::AnyReg | |
| SparcISA::AnyReg | |
| X86ISA::AnyReg | |
| MipsISA::AnyReg | |
| aout_exechdr | Funky Alpha 64-bit a.out header used for PAL code |
| Arguments | |
| ArmFreebsdProcessBits | |
| ArmFreebsdProcess32 | A process with emulated Arm/Freebsd syscalls |
| ArmFreebsdProcess64 | A process with emulated Arm/Freebsd syscalls |
| ArmLinuxProcessBits | |
| ArmLinuxProcess32 | A process with emulated Arm/Linux syscalls |
| ArmLinuxProcess64 | A process with emulated Arm/Linux syscalls |
| AtagHeader | |
| AtagCmdline | |
| AtagCore | |
| AtagMem | |
| AtagNone | |
| AtagRev | |
| AtagSerial | |
| ataparams | |
| AtomicOpFunctor | |
 TypedAtomicOpFunctor< T > | |
 AtomicOpAdd< T > | |
| AtomicOpAnd< T > | |
| AtomicOpCAS< T > | |
| AtomicOpDec< T > | |
| AtomicOpExch< T > | |
| AtomicOpInc< T > | |
| AtomicOpMax< T > | |
| AtomicOpMin< T > | |
| AtomicOpOr< T > | |
| AtomicOpSub< T > | |
| AtomicOpXor< T > | |
| AUXU | |
| AuxVector< IntType > | |
| Stats::AvgSampleStor | Templatized storage for distribution that calculates per tick mean and variance |
| Stats::AvgStor | Templatized storage and interface to a per-tick average stat |
| BackingStoreEntry | A single entry for the backing store |
| BaseRemoteGDB::BadClient | Exception to throw when the connection to the client is broken |
| DRAMCtrl::Bank | A basic class to track the bank state, i.e |
| BankedArray | |
| Barrier | |
| Base | |
| ArmISA::MemoryOffset< Base > | |
| ArmISA::MemoryPostIndex< Base > | |
| ArmISA::MemoryPreIndex< Base > | |
| BitfieldBackend::BitUnionOperators< Type, Base > | |
| BaseBufferArg | Base class for BufferArg and TypedBufferArg, Not intended to be used directly |
| BufferArg | BufferArg represents an untyped buffer in target user space that is passed by reference to an (emulated) system call |
| TypedBufferArg< T > | TypedBufferArg is a class template; instances of this template represent typed buffers in target user space that are passed by reference to an (emulated) system call |
| BaseCPU | |
| BaseKvmCPU | Base class for KVM based CPU models |
| ArmKvmCPU | ARM implementation of a KVM-based hardware virtualized CPU |
| BaseArmKvmCPU | |
| ArmV8KvmCPU | This is an implementation of a KVM-based ARMv8-compatible CPU |
| X86KvmCPU | X86 implementation of a KVM-based hardware virtualized CPU |
| BaseO3CPU | |
| FullO3CPU< Impl > | FullO3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages |
| FullO3CPU< O3CPUImpl > | |
| DerivO3CPU | |
| BaseSimpleCPU | |
| AtomicSimpleCPU | |
| TimingSimpleCPU | |
| CheckerCPU | CheckerCPU class |
| Checker< Impl > | Templated Checker class |
| Checker< O3CPUImpl > | |
| O3Checker | Specific non-templated derived class used for SimObject configuration |
| DummyChecker | Specific non-templated derived class used for SimObject configuration |
| MinorCPU | MinorCPU is an in-order CPU model with four fixed pipeline stages: |
| TraceCPU | The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model |
| BaseGdbRegCache | |
| AlphaISA::RemoteGDB::AlphaGdbRegCache | |
| ArmISA::RemoteGDB::AArch32GdbRegCache | |
| PowerISA::RemoteGDB::PowerGdbRegCache | |
| SparcISA::RemoteGDB::SPARCGdbRegCache | |
| BaseRemoteGDB::BaseGdbRegCache | Concrete subclasses of this abstract class represent how the register values are transmitted on the wire |
| ArmISA::RemoteGDB::AArch64GdbRegCache | |
| MipsISA::RemoteGDB::MipsGdbRegCache | |
| RiscvISA::RemoteGDB::RiscvGdbRegCache | |
| SparcISA::RemoteGDB::SPARC64GdbRegCache | |
| X86ISA::RemoteGDB::AMD64GdbRegCache | |
| X86ISA::RemoteGDB::X86GdbRegCache | |
| BaseGen | Base class for all generators, with the shared functionality and virtual functions for entering, executing and leaving the generator |
| IdleGen | The idle generator does nothing |
| LinearGen | The linear generator generates sequential requests from a start to an end address, with a fixed block size |
| RandomGen | The random generator is similar to the linear one, but does not generate sequential addresses |
| DramGen | DRAM specific generator is for issuing request with variable page hit length and bank utilization |
| DramRotGen | |
| TraceGen | The trace replay generator reads a trace file and plays back the transactions |
| BaseGicRegisters | |
| KvmKernelGicV2 | KVM in-kernel GIC abstraction |
| Pl390 | |
| MuxingKvmGic | |
| ArmISA::BaseISADevice | Base class for devices that use the MiscReg interfaces |
| ArmISA::DummyISADevice | Dummy device that prints a warning when it is accessed |
| ArmISA::PMU | Model of an ARM PMU version 3 |
| GenericTimerISA | |
| BaseKvmTimer | Timer functions to interrupt VM execution after a number of simulation ticks |
| PerfKvmTimer | PerfEvent based timer using the host's CPU cycle counter |
| PosixKvmTimer | Timer based on standard POSIX timers |
| BaseOperand | |
| AddrOperandBase | |
| NoRegAddrOperand | |
| RegAddrOperand< RegOperandType > | |
| BaseRegOperand | |
| CRegOperand | |
| DRegOperand | |
| SRegOperand | |
| FunctionRefOperand | |
| ImmOperand< T > | |
| ImmOperand< SrcCType > | |
| ImmOperand< uint32_t > | |
| LabelOperand | |
| ListOperand | |
| RegOrImmOperand< RegOperand, T > | |
| BaseRemoteGDB | |
| AlphaISA::RemoteGDB | |
| ArmISA::RemoteGDB | |
| MipsISA::RemoteGDB | |
| PowerISA::RemoteGDB | |
| RiscvISA::RemoteGDB | |
| SparcISA::RemoteGDB | |
| X86ISA::RemoteGDB | |
| BasicBlock | |
| GenericISA::BasicDecodeCache | |
| BasicSignal | |
| SimPoint::BBInfo | Basic Block information |
| LTAGE::BimodalEntry | |
| BitfieldBackend::BitfieldBase< Data > | |
| BitfieldBackend::BitfieldBase< Type > | |
| BitfieldBackend::RegularBitfieldTypes< Type >::Bitfield< first, last > | |
| BitfieldBackend::RegularBitfieldTypes< Type >::BitfieldRO< first, last > | |
| BitfieldBackend::RegularBitfieldTypes< Type >::BitfieldWO< first, last > | |
| BitfieldBackend::SignedBitfieldTypes< Type >::SignedBitfield< first, last > | |
| BitfieldBackend::SignedBitfieldTypes< Type >::SignedBitfieldRO< first, last > | |
| BitfieldBackend::SignedBitfieldTypes< Type >::SignedBitfieldWO< first, last > | |
| Bitmap | |
| VirtIOBlock::BlkRequest | VirtIO block device request as sent by guest |
| Bitmap::BmpPixel32 | |
| BiModeBP::BPHistory | |
| TournamentBP::BPHistory | The branch history information that is created upon predicting a branch |
| Minor::BranchData | Forward data betwen Execute and Fetch1 carrying change-of-address/stream information |
| LTAGE::BranchInfo | |
| Brig::BrigAluModifier | |
| Brig::BrigBase | |
| Brig::BrigData | |
| Brig::BrigDirectiveArgBlockEnd | |
| Brig::BrigDirectiveArgBlockStart | |
| Brig::BrigDirectiveComment | |
| Brig::BrigDirectiveControl | |
| Brig::BrigDirectiveExecutable | |
| Brig::BrigDirectiveExtension | |
| Brig::BrigDirectiveFbarrier | |
| Brig::BrigDirectiveLabel | |
| Brig::BrigDirectiveLoc | |
| Brig::BrigDirectiveModule | |
| Brig::BrigDirectiveNone | |
| Brig::BrigDirectivePragma | |
| Brig::BrigDirectiveVariable | |
| Brig::BrigExecutableModifier | |
| Brig::BrigInstAddr | |
| Brig::BrigInstAtomic | |
| Brig::BrigInstBase | |
| Brig::BrigInstBasic | |
| Brig::BrigInstBr | |
| Brig::BrigInstCmp | |
| Brig::BrigInstCvt | |
| Brig::BrigInstImage | |
| Brig::BrigInstLane | |
| Brig::BrigInstMem | |
| Brig::BrigInstMemFence | |
| Brig::BrigInstMod | |
| Brig::BrigInstQueryImage | |
| Brig::BrigInstQuerySampler | |
| Brig::BrigInstQueue | |
| Brig::BrigInstSeg | |
| Brig::BrigInstSegCvt | |
| Brig::BrigInstSignal | |
| Brig::BrigInstSourceType | |
| Brig::BrigMemoryModifier | |
| Brig::BrigModuleHeader | |
| Brig::BrigOperandAddress | |
| Brig::BrigOperandAlign | |
| Brig::BrigOperandCodeList | |
| Brig::BrigOperandCodeRef | |
| Brig::BrigOperandConstantBytes | |
| Brig::BrigOperandConstantImage | |
| Brig::BrigOperandConstantOperandList | |
| Brig::BrigOperandConstantSampler | |
| Brig::BrigOperandOperandList | |
| Brig::BrigOperandRegister | |
| Brig::BrigOperandString | |
| Brig::BrigOperandWavesize | |
| BrigRegOperandInfo | |
| Brig::BrigSectionHeader | |
| Brig::BrigSegCvtModifier | |
| Brig::BrigUInt64 | |
| Brig::BrigVariableModifier | |
| DefaultBTB::BTBEntry | |
| Minor::BubbleIF | Interface class for data with 'bubble' values |
| Minor::BubbleTraitsAdaptor< ElemType > | Pass on call to the element |
| Minor::BubbleTraitsPtrAdaptor< PtrType, ElemType > | Pass on call to the element where the element is a pointer |
| DRAMCtrl::BurstHelper | A burst helper helps organize and manage a packet that is larger than the DRAM burst size |
| CacheBlk | A Basic Cache block |
| FALRUBlk | A fully associative cache block |
| CacheBlkVisitor | Base class for cache block visitor, operating on the cache block base class (later subclassed for the various tag classes) |
| CacheBlkIsDirtyVisitor | Cache block visitor that determines if there are dirty blocks in a cache |
| CacheBlkVisitorWrapper | Wrap a method and present it as a cache block visitor |
| PageTableBase::cacheElement | |
| CacheMasterPort | |
| Cache::MemSidePort | The memory-side port extends the base cache master port with access functions for functional, atomic and timing snoops |
| DecodeCache::AddrMap< Value >::CachePage | |
| CacheRecorder | |
| CacheSet< Blktype > | An associative set of cache blocks |
| CacheSlavePort | |
| Cache::CpuSidePort | The CPU-side port extends the base cache slave port with access functions for functional, atomic and timing requests |
| CallArgMem | |
| Callback | Generic callback class |
| AbstractController::StatsCallback | Callback class used for collating statistics from all the controller of this type |
| AnnotateDumpCallback | |
| BaseTagsCallback | |
| BaseTagsDumpCallback | |
| ClockedObjectDumpCallback | |
| ComputeUnit::CUExitCallback | |
| CowDiskCallback | |
| DRAMCtrl::RankDumpCallback | |
| MakeCallback< T, F > | Helper template class to turn a simple class member function into a callback |
| MakeCallback< PciVirtIO,&PciVirtIO::kick > | |
| MakeCallback< Uart,&Uart::dataAvailable > | |
| MakeCallback< VirtIOConsole::VirtIOConsole::TermRecvQueue,&VirtIOConsole::VirtIOConsole::TermRecvQueue::trySend > | |
| Network::StatsCallback | Callback class used for collating statistics from all the controller of this type |
| RubyStatsCallback | |
| Stats::SimTicksReset | |
| FlashDevice::CallBackEntry | |
| CallbackQueue | |
| PixelConverter::Channel | Color channel conversion and scaling helper class |
| Check | |
| CheckpointIn | |
| CheckTable | |
| ChunkGenerator | This class takes an arbitrary memory region (address/length pair) and generates a series of appropriately (e.g |
| CircleBuf< T > | Circular buffer backed by a vector |
| CircleBuf< char > | |
| CircleBuf< value_type > | |
| VncInput::ClientCutTextMessage | |
| Clocked | Helper class for objects that need to be clocked |
| BasePixelPump | Timing generator for a pixel-based display |
| HDLcd::PixelPump | |
| ClockedObject | Extends the SimObject with a clock and accessor functions to relate ticks to the cycles of the object |
| BasePrefetcher | |
| QueuedPrefetcher | |
| StridePrefetcher | |
| TaggedPrefetcher | |
| BaseTags | A common base class of Cache tagstore objects |
| BaseSetAssoc | A BaseSetAssoc cache tag store |
| LRU | |
| RandomRepl | |
| FALRU | A fully associative LRU cache |
| BasicRouter | |
| Router | |
| Switch | |
| MemObject | Extends the ClockedObject with accessor functions to get its master and slave ports |
| AbstractController | |
| AbstractMemory | An abstract memory represents a contiguous block of physical memory, with an associated address range, and also provides basic functionality for reading and writing this memory without any timing information |
| DRAMCtrl | The DRAM controller is a single-channel memory controller capturing the most important timing constraints associated with a contemporary DRAM |
| DRAMSim2 | |
| SimpleMemory | The simple memory is a basic single-ported memory controller with a configurable throughput and latency |
| AddrMapper | An address mapper changes the packet addresses in going from the slave port side of the mapper to the master port side |
| RangeAddrMapper | Range address mapper that maps a set of original ranges to a set of remapped ranges, where a specific range is of the same size (original and remapped), only with an offset |
| ArmISA::TableWalker | |
| BaseCache | A basic cache interface |
| Cache | A template-policy based cache |
| BaseXBar | The base crossbar contains the common elements of the non-coherent and coherent crossbar |
| CoherentXBar | A coherent crossbar connects a number of (potentially) snooping masters and slaves, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses |
| NoncoherentXBar | A non-coherent crossbar connects a number of non-snooping masters and slaves, and routes the request and response packets based on the address |
| HMCController | HMC Controller, in general, is responsible for translating the host protocol (AXI for example) to serial links protocol |
| Bridge | A bridge is used to interface two different crossbars (or in general a memory-mapped master and slave), with buffering for requests and responses |
| CommMonitor | The communication monitor is a MemObject which can monitor statistics of the communication happening between two ports in the memory system |
| ComputeUnit | |
| ExternalMaster | |
| ExternalSlave | |
| GarnetSyntheticTraffic | |
| LdsState | |
| MemCheckerMonitor | Implements a MemChecker monitor, to be inserted between two ports |
| MemTest | Tests a cache coherent memory system by generating false sharing and verifying the read data against a reference updated on the completion of writes |
| PioDevice | This device is the base class which all devices senstive to an address range inherit from |
| BaseGic | |
| Pl390 | |
| BasicPioDevice | |
| A9SCU | |
| AlphaBackdoor | Memory mapped interface to the system console |
| AmbaPioDevice | |
| BadDevice | BadDevice This device just panics when accessed |
| CpuLocalTimer | |
| DumbTOD | DumbTOD simply returns some idea of time when read |
| EnergyCtrl | |
| I2CBus | |
| IsaFake | IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and rites |
| MaltaCChip | Malta CChip CSR Emulation |
| MaltaIO | Malta I/O device is a catch all for all the south bridge stuff we care to implement |
| MmDisk | |
| RealViewCtrl | |
| TsunamiCChip | Tsunami CChip CSR Emulation |
| TsunamiIO | Tsunami I/O device is a catch all for all the south bridge stuff we care to implement |
| Uart | |
| Pl011 | |
| Uart8250 | |
| X86ISA::Cmos | |
| X86ISA::I8042 | |
| X86ISA::I82094AA | |
| X86ISA::I8237 | |
| X86ISA::I8254 | |
| X86ISA::I8259 | |
| X86ISA::Interrupts | |
| X86ISA::Speaker | |
| DmaDevice | |
| AmbaDmaDevice | |
| GpuDispatcher | |
| PciDevice | PCI device, base implementation is only config space |
| CopyEngine | |
| EtherDevice | The base EtherObject class, allows for an accesor function to a simobj that returns the Port |
| EtherDevBase | Dummy class to keep the Python class hierarchy in sync with the C++ object hierarchy |
| NSGigE | NS DP83820 Ethernet device model |
| Sinic::Base | |
| Sinic::Device | |
| IGbE | |
| IdeController | Device model for an Intel PIIX4 IDE controller |
| PciVirtIO | |
| UFSHostDevice | UFS command flow state machine digraph CommandFlow{ node [fontsize=10]; IDLE -> transferHandler [ label=" transfer/task/command request " fontsize=6]; transferHandler -> command [ label=" It is a command " fontsize=6]; command -> IDLE [ label=" Command done, no further action " fontsize=6]; transferHandler -> taskStart [ label=" It is a task " fontsize=6]; taskStart -> finalUTP [ label=" Task handled, now acknowledge (UFS) " fontsize=6]; transferHandler -> transferStart [ label=" It is a transfer " fontsize=6]; transferStart -> SCSIResume [ label=" Transfer, obtain the specific command " fontsize=6]; SCSIResume -> DiskDataFlowPhase [ label=" Disk data transfer (see other graphs) " fontsize=6]; SCSIResume -> DeviceDataPhase [ label=" Device info transfer (handled in SCSIResume) " fontsize=6]; DiskDataFlowPhase -> transferDone [ label=" Transfer done, acknowledge SCSI command " fontsize=6]; DeviceDataPhase -> transferDone [ label=" Transfer done, acknowledge SCSI command " fontsize=6]; transferDone -> finalUTP [ label=" Transfer handled, now acknowledge (UFS) " fontsize=6]; finalUTP -> readDone [ label=" All handled, clear data structures " fontsize=6]; readDone -> IDLE [ label=" All handled, nothing outstanding " fontsize=6]; readDone -> transferHandler [ label=" All handled, handle next outstanding " fontsize=6]; } |
| GenericTimerMem | |
| Gicv2m | |
| Iob | |
| NoMaliGpu | |
| CustomNoMaliGpu | |
| PciHost | The PCI host describes the interface between PCI devices and a simulated system |
| GenericPciHost | Configurable generic PCI host interface |
| GenericArmPciHost | |
| TsunamiPChip | A very simple implementation of the Tsunami PCI interface chips |
| VGic | |
| RubyDirectedTester | |
| RubyPort | |
| DMASequencer | |
| GPUCoalescer | |
| VIPERCoalescer | |
| RubyPortProxy | |
| Sequencer | |
| RubyTester | |
| SerialLink | SerialLink is a simple variation of the Bridge class, with the ability to account for the latency of packet serialization |
| System | |
| AlphaSystem | |
| FreebsdAlphaSystem | |
| LinuxAlphaSystem | This class contains linux specific system code (Loading, Events) |
| ArmSystem | |
| GenericArmSystem | |
| FreebsdArmSystem | |
| LinuxArmSystem | |
| MipsSystem | |
| BareIronMipsSystem | This class contains linux specific system code (Loading, Events) |
| LinuxMipsSystem | This class contains linux specific system code (Loading, Events) |
| RiscvSystem | |
| SparcSystem | |
| X86System | |
| LinuxX86System | |
| TLBCoalescer | The TLBCoalescer is a MemObject sitting on the front side (CPUSide) of each TLB |
| TrafficGen | The traffic generator is a master module that generates stimuli for the memory system, based on a collection of simple generator behaviours that are either probabilistic or based on traces |
| X86ISA::GpuTLB | |
| X86ISA::Walker | |
| Network | |
| GarnetNetwork | |
| SimpleNetwork | |
| NetworkInterface | |
| NetworkLink | |
| CreditLink | |
| RubySystem | |
| Shader | |
| ThermalModel | A ThermalModel is the element which ties all thermal objects together and provides the thermal solver to the system |
| TickedObject | TickedObject attaches Ticked to ClockedObject and can be used as a base class where ticked operation |
| BaseRemoteGDB::CmdError | Exception to throw when an error needs to be reported to the client |
| DRAMCtrl::Command | Simple structure to hold the values needed to keep track of commands for DRAMPower |
| MemCmd::CommandInfo | Structure that defines attributes and other data associated with a Command |
| CommandReg | |
| TimeBufStruct< Impl >::commitComm | |
| Bitmap::CompleteV1Header | |
| ConditionRegisterState | |
| VirtIOBlock::Config | Block device configuration structure |
| VirtIOConsole::Config | Console configuration structure |
| VirtIO9PBase::Config | VirtIO 9p configuration structure |
| Consumer | |
| AbstractController | |
| CrossbarSwitch | |
| InputUnit | |
| NetworkInterface | |
| NetworkLink | |
| OutputUnit | |
| PerfectSwitch | |
| Router | |
| SwitchAllocator | |
| Throttle | |
| m5::stl_helpers::ContainerPrint< T > | |
| GdbCommand::Context | |
| ControlFlowInfo | |
| MipsISA::CoreSpecific | |
| GenericTimer::CoreTimers | |
| Intel8254Timer::Counter | Counter element for PIT |
| CPA | |
| CPAIgnoreSymbol | |
| X86ISA::CpuidResult | |
| CxxConfigDirectoryEntry | Config details entry for a SimObject |
| CxxConfigFileBase | Config file wrapper providing a common interface to CxxConfigManager |
| CxxIniFile | CxxConfigManager interface for using .ini files |
| CxxConfigManager | This class allows a config file to be read into gem5 (generating the appropriate SimObjects) from C++ |
| CxxConfigParams | Base for peer classes of SimObjectParams derived classes with parameter modifying member functions |
| Cycles | Cycles is a wrapper class for representing cycle counts, i.e |
| Arguments::Data | |
| DataBlock | |
| TimeBufStruct< Impl >::decodeComm | |
| RiscvISA::Decoder | |
| SparcISA::Decoder | |
| X86ISA::Decoder | |
| AlphaISA::Decoder | |
| HsailISA::Decoder | |
| ArmISA::Decoder | |
| MipsISA::Decoder | |
| PowerISA::Decoder | |
| Minor::Decode::DecodeThreadInfo | Data members after this line are cycle-to-cycle state |
| DefaultBTB | |
| DefaultCommit< Impl > | DefaultCommit handles single threaded and SMT commit |
| DefaultDecode< Impl > | DefaultDecode class handles both single threaded and SMT decode |
| DefaultDecodeDefaultRename< Impl > | Struct that defines the information passed from decode to rename |
| DefaultFetch< Impl > | DefaultFetch class handles both single threaded and SMT fetch |
| DefaultFetchDefaultDecode< Impl > | Struct that defines the information passed from fetch to decode |
| DefaultIEW< Impl > | DefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback) |
| DefaultIEWDefaultCommit< Impl > | Struct that defines the information passed from IEW to commit |
| DefaultRename< Impl > | DefaultRename handles both single threaded and SMT rename |
| DefaultRenameDefaultIEW< Impl > | Struct that defines the information passed from rename to IEW |
| Bridge::DeferredPacket | A deferred packet stores a packet along with its scheduled transmission time |
| QueuedPrefetcher::DeferredPacket | |
| PacketQueue::DeferredPacket | A deferred packet, buffered to transmit later |
| SerialLink::DeferredPacket | A deferred packet stores a packet along with its scheduled transmission time |
| SimpleMemory::DeferredPacket | A deferred packet stores a packet along with its scheduled transmission time |
| DependencyEntry< DynInstPtr > | Node in a linked list |
| DependencyGraph< DynInstPtr > | Array of linked list that maintains the dependencies between producing instructions and consuming instructions |
| std::deque< T > | STL deque class |
| std::deque< Bridge::DeferredPacket > | |
| std::deque< DmaDoneEventUPtr > | |
| std::deque< DRAMCtrl::DRAMPacket * > | |
| std::deque< DynInstPtr > | |
| std::deque< ElemType > | |
| std::deque< EventWrapper< UFSHostDevice,&UFSHostDevice::readDone > > | |
| std::deque< EventWrapper< UFSHostDevice,&UFSHostDevice::readGarbage > > | |
| std::deque< EventWrapper< UFSHostDevice,&UFSHostDevice::UFSHostDevice::taskStart > > | |
| std::deque< EventWrapper< UFSHostDevice,&UFSHostDevice::UFSHostDevice::transferStart > > | |
| std::deque< EventWrapper< UFSHostDevice,&UFSHostDevice::writeDone > > | |
| std::deque< FetchRequestPtr > | |
| std::deque< flit * > | |
| std::deque< GPUDynInstPtr > | |
| std::deque< iGbReg::RxDesc * > | |
| std::deque< iGbReg::TxDesc * > | |
| std::deque< IndirectPredictor::HistoryEntry > | |
| std::deque< LSQRequestPtr > | |
| std::deque< MasterPort * > | |
| std::deque< Minor::ForwardInstData > | |
| std::deque< Minor::ForwardLineData > | |
| std::deque< Minor::LSQ::LSQRequest > | |
| std::deque< Minor::QueuedInst > | |
| std::deque< Packet > | |
| std::deque< SerialLink::DeferredPacket > | |
| std::deque< SlavePort * > | |
| std::deque< SrcType * > | |
| std::deque< std::pair< Packet, GPUDynInstPtr > > | |
| std::deque< std::pair< Packet, Wavefront * > > | |
| std::deque< std::pair< Tick, EthPacketPtr > > | |
| std::deque< std::unique_ptr< ReconvergenceStackEntry > > | |
| std::deque< struct FlashDevice::CallBackEntry > | |
| std::deque< struct UFSHostDevice::SCSIResumeInfo > | |
| std::deque< struct UFSHostDevice::taskStart > | |
| std::deque< struct UFSHostDevice::transferInfo > | |
| std::deque< struct UFSHostDevice::transferStart > | |
| std::deque< struct UFSHostDevice::UTPTransferReqDesc * > | |
| std::deque< struct UFSHostDevice::writeToDiskBurst > | |
| std::deque< T * > | |
| std::deque< Tick > | |
| std::deque< uint8_t > | |
| ArmISA::TableWalker::DescriptorBase | |
| ArmISA::TableWalker::L1Descriptor | |
| ArmISA::TableWalker::L2Descriptor | Level 2 page table descriptor |
| ArmISA::TableWalker::LongDescriptor | Long-descriptor format (LPAE) |
| RealViewCtrl::Device | |
| RealViewOsc | This is an implementation of a programmable oscillator on the that can be configured through the RealView/Versatile Express configuration interface |
| RealViewTemperatureSensor | This device implements the temperature sensor used in the RealView/Versatile Express platform |
| PciHost::DeviceInterface | Callback interface from PCI devices to the host |
| Stats::DistData | |
| DistHeaderPkt | |
| Stats::DistPrint | |
| Stats::DistProxy< Stat > | |
| Stats::DistStor | Templatized storage and interface for a distribution stat |
| CopyEngineReg::DmaDesc | |
| DMARequest | |
| DmesgEntry | |
| DNR | |
| dp_regs | Ethernet device registers |
| dp_rom | |
| Drainable | Interface for objects that might require draining before checkpointing |
| BasePixelPump::PixelEvent | Callback helper class with suspend support |
| BaseXBar::Layer< SrcType, DstType > | A layer is an internal crossbar arbitration point with its own flow control |
| CopyEngine::CopyEngineChannel | |
| DistIface | The interface class to talk to peer gem5 processes |
| TCPIface | |
| DmaCallback | DMA callback class |
| DmaPort | |
| DmaReadFifo | Buffered DMA engine helper class |
| HDLcd::DmaEngine | |
| BaseXBar::Layer< MasterPort, SlavePort > | |
| BaseXBar::RespLayer | |
| BaseXBar::Layer< SlavePort, MasterPort > | |
| BaseXBar::ReqLayer | |
| BaseXBar::SnoopRespLayer | |
| PacketQueue | A packet queue is a class that holds deferred packets and later sends them using the associated slave port or master port |
| ReqPacketQueue | |
| Cache::CacheReqPacketQueue | Override the default behaviour of sendDeferredPacket to enable the memory-side cache port to also send requests based on the current MSHR status |
| RespPacketQueue | |
| SnoopRespPacketQueue | |
| Queue< Entry > | A high-level queue interface, to be used by both the MSHR queue and the write buffer |
| Queue< MSHR > | |
| MSHRQueue | A Class for maintaining a list of pending and allocated memory requests |
| Queue< WriteQueueEntry > | |
| WriteQueue | A write queue for all eviction packets, i.e |
| SimObject | Abstract superclass for simulation objects |
| AbstractNVM | This is an interface between the disk interface (which will handle the disk data transactions) and the timing model |
| FlashDevice | Flash Device model The Flash Device model is a timing model for a NAND flash device |
| AbstractReplacementPolicy | |
| LRUPolicy | |
| PseudoLRUPolicy | Implementation of tree-based pseudo-LRU replacement |
| WeightedLRUPolicy | |
| AlphaISA::Interrupts | |
| AlphaISA::ISA | |
| ArmISA::Interrupts | |
| ArmISA::ISA | Some registers alias with others, and therefore need to be translated |
| ArmISA::PMU | Model of an ARM PMU version 3 |
| ArmISA::Stage2MMU | |
| BaseMemProbe | Base class for memory system probes accepting Packet instances |
| MemFootprintProbe | Probe to track footprint of accessed memory Two granularity of footprint measurement i.e |
| MemTraceProbe | |
| StackDistProbe | |
| BaseTLB | |
| AlphaISA::TLB | |
| ArmISA::TLB | |
| GenericTLB | |
| MipsISA::TLB | |
| PowerISA::TLB | |
| RiscvISA::TLB | |
| SparcISA::TLB | |
| X86ISA::TLB | |
| BasicLink | |
| BasicExtLink | |
| GarnetExtLink | |
| SimpleExtLink | |
| BasicIntLink | |
| GarnetIntLink | |
| SimpleIntLink | |
| BPredUnit | Basically a wrapper class to hold both the branch predictor and the BTB |
| BiModeBP | Implements a bi-mode branch predictor |
| LocalBP | Implements a local predictor that uses the PC to index into a table of counters |
| LTAGE | |
| TournamentBP | Implements a tournament branch predictor, hopefully identical to the one used in the 21264 |
| CacheMemory | |
| ClockDomain | The ClockDomain provides clock to group of clocked objects bundled under the same clock domain |
| DerivedClockDomain | The derived clock domains provides the notion of a clock domain that is connected to a parent clock domain that can either be a source clock domain or a derived clock domain |
| RealViewOsc | This is an implementation of a programmable oscillator on the that can be configured through the RealView/Versatile Express configuration interface |
| SrcClockDomain | The source clock domains provides the notion of a clock domain that is connected to a tunable clock source |
| ClockedObject | Extends the SimObject with a clock and accessor functions to relate ticks to the cycles of the object |
| DirectedGenerator | |
| InvalidateGenerator | |
| SeriesRequestGenerator | |
| DirectoryMemory | |
| DiskImage | Basic interface for accessing a disk image |
| CowDiskImage | Specialization for accessing a copy-on-write disk image layer |
| RawDiskImage | Specialization for accessing a raw disk image |
| DVFSHandler | DVFS Handler class, maintains a list of all the domains it can handle |
| EmulatedDriver | EmulatedDriver is an abstract base class for fake SE-mode device drivers |
| ClDriver | |
| EtherDump | |
| EtherObject | The base EtherObject class, allows for an accesor function to a simobj that returns the Port |
| DistEtherLink | Model for a fixed bandwidth full duplex ethernet link |
| EtherBus | |
| EtherLink | |
| EtherSwitch | |
| EtherTapBase | |
| EtherTapStub | |
| FaultModel | |
| FUDesc | |
| FUPool | Pool of FU's, specific to the new CPU model |
| GenericTimer | |
| Gicv2mFrame | Ultimately this class should be embedded in the Gicv2m class, but this confuses Python as 'Gicv2m::Frame' gets interpreted as 'Frame' in namespace Gicv2m |
| I2CDevice | |
| IdeDisk | IDE Disk device model |
| IntrControl | |
| KvmVM | KVM VM container |
| MemChecker | MemChecker |
| MessageBuffer | |
| MinorFU | A functional unit that can execute any of opClasses operations with a single op(eration)Lat(ency) and issueLat(ency) associated with the unit rather than each operation (as in src/FuncUnit) |
| MinorFUPool | A collection of MinorFUs |
| MinorFUTiming | Extra timing capability to allow individual ops to have their source register dependency latencies tweaked based on the ExtMachInst of the source instruction |
| MinorOpClass | Boxing for MinorOpClass to get around a build problem with C++11 but also allow for future additions to op class checking |
| MinorOpClassSet | Wrapper for a matchable set of op classes |
| MipsISA::Interrupts | |
| MipsISA::ISA | |
| OpDesc | |
| Platform | |
| Malta | Top level class for Malta Chipset emulation |
| Pc | |
| RealView | |
| T1000 | |
| Tsunami | Top level class for Tsunami Chipset emulation |
| PowerISA::Interrupts | |
| PowerISA::ISA | |
| PowerModel | A PowerModel is a class containing a power model for a SimObject |
| PowerModelState | A PowerModelState is an abstract class used as interface to get power figures out of SimObjects |
| MathExprPowerModel | A Equation power model |
| Prefetcher | |
| ProbeListenerObject | This class is a minimal wrapper around SimObject |
| ElasticTrace | The elastic trace is a type of probe listener and listens to probe points in multiple stages of the O3CPU |
| SimpleTrace | |
| SimPoint | |
| Process | |
| AlphaProcess | |
| AlphaISA::AlphaLinuxProcess | A process with emulated Alpha/Linux syscalls |
| ArmProcess | |
| ArmProcess32 | |
| ArmFreebsdProcess32 | A process with emulated Arm/Freebsd syscalls |
| ArmLinuxProcess32 | A process with emulated Arm/Linux syscalls |
| ArmProcess64 | |
| ArmFreebsdProcess64 | A process with emulated Arm/Freebsd syscalls |
| ArmLinuxProcess64 | A process with emulated Arm/Linux syscalls |
| MipsProcess | |
| MipsLinuxProcess | A process with emulated Mips/Linux syscalls |
| PowerProcess | |
| PowerLinuxProcess | A process with emulated PPC/Linux syscalls |
| RiscvProcess | |
| RiscvLinuxProcess | A process with emulated Riscv/Linux syscalls |
| SparcProcess | |
| Sparc32Process | |
| SparcISA::Sparc32LinuxProcess | A process with emulated SPARC/Linux syscalls |
| Sparc64Process | |
| SparcISA::Sparc64LinuxProcess | A process with emulated 32 bit SPARC/Linux syscalls |
| SparcISA::SparcSolarisProcess | A process with emulated SPARC/Solaris syscalls |
| X86ISA::X86Process | |
| X86ISA::I386Process | |
| X86ISA::I386LinuxProcess | |
| X86ISA::X86_64Process | |
| X86ISA::X86_64LinuxProcess | |
| RealViewTemperatureSensor | This device implements the temperature sensor used in the RealView/Versatile Express platform |
| RiscvISA::Interrupts | |
| RiscvISA::ISA | |
| Root | |
| SimpleDisk | |
| SnoopFilter | This snoop filter keeps track of which connected port has a particular line of data |
| SouthBridge | |
| SparcISA::Interrupts | |
| SparcISA::ISA | |
| SubSystem | The SubSystem simobject does nothing, it is just a container for other simobjects used by the configuration system |
| Terminal | |
| ThermalCapacitor | A ThermalCapacitor is used to model a thermal capacitance between two thermal domains |
| ThermalDomain | A ThermalDomain is used to group objects under that operate under the same temperature |
| ThermalNode | A ThermalNode is used to connect thermal entities, such as resistors, capacitors, references and domains |
| ThermalReference | A ThermalReference is a thermal domain with fixed temperature |
| ThermalResistor | A ThermalResistor is used to model a thermal resistance between two thermal domains |
| TimingExpr | |
| TimingExprBin | |
| TimingExprIf | |
| TimingExprLet | |
| TimingExprLiteral | |
| TimingExprReadIntReg | |
| TimingExprRef | |
| TimingExprSrcReg | |
| TimingExprUn | |
| Trace::InstTracer | |
| Trace::ExeTracer | |
| Trace::NativeTrace | |
| Trace::ArmNativeTrace | |
| Trace::SparcNativeTrace | |
| Trace::X86NativeTrace | |
| Trace::InstPBTrace | |
| Trace::IntelTrace | |
| UFSHostDevice::UFSSCSIDevice | Device layer: This is your Logic unit This layer implements the SCSI functionality of the UFS Device One logic unit controls one or more disk partitions |
| VectorRegisterFile | |
| VirtIODeviceBase | Base class for all VirtIO-based devices |
| VirtIO9PBase | This class implements a VirtIO transport layer for the 9p network file system |
| VirtIO9PProxy | VirtIO 9p proxy base class |
| VirtIO9PDiod | VirtIO 9p proxy that communicates with the diod 9p server using pipes |
| VirtIO9PSocket | VirtIO 9p proxy that communicates with a 9p server over tcp sockets |
| VirtIOBlock | VirtIO block device |
| VirtIOConsole | VirtIO console |
| VirtIODummyDevice | |
| VncInput | |
| VncServer | |
| VoltageDomain | A VoltageDomain is used to group clock domains that operate under the same voltage |
| Wavefront | |
| WireBuffer | |
| X86ISA::ACPI::RSDP | |
| X86ISA::ACPI::SysDescTable | |
| X86ISA::ACPI::RSDT | |
| X86ISA::ACPI::XSDT | |
| X86ISA::E820Entry | |
| X86ISA::E820Table | |
| X86ISA::IntelMP::BaseConfigEntry | |
| X86ISA::IntelMP::Bus | |
| X86ISA::IntelMP::IntAssignment | |
| X86ISA::IntelMP::IOIntAssignment | |
| X86ISA::IntelMP::LocalIntAssignment | |
| X86ISA::IntelMP::IOAPIC | |
| X86ISA::IntelMP::Processor | |
| X86ISA::IntelMP::ConfigTable | |
| X86ISA::IntelMP::ExtConfigEntry | |
| X86ISA::IntelMP::AddrSpaceMapping | |
| X86ISA::IntelMP::BusHierarchy | |
| X86ISA::IntelMP::CompatAddrSpaceMod | |
| X86ISA::IntelMP::FloatingPointer | |
| X86ISA::IntLine | |
| X86ISA::IntSinkPin | |
| X86ISA::IntSourcePin | |
| X86ISA::ISA | |
| X86ISA::SMBios::SMBiosStructure | |
| X86ISA::SMBios::BiosInformation | |
| X86ISA::SMBios::SMBiosTable | |
| DrainManager | This class coordinates draining of a System |
| DRAMCtrl::DRAMPacket | A DRAM packet stores packets along with the timestamp of when the packet entered the queue, and also the decoded address |
| DRAMPower | DRAMPower is a standalone tool which calculates the power consumed by a DRAM in the system |
| DRAMSim2Wrapper | Wrapper class to avoid having DRAMSim2 names like ClockDomain etc clashing with the normal gem5 world |
| ecoff_aouthdr | |
| ecoff_exechdr | |
| ecoff_extsym | |
| ecoff_fdr | |
| ecoff_filehdr | |
| ecoff_scnhdr | |
| ecoff_sym | |
| ecoff_symhdr | |
| TraceCPU::ElasticDataGen | The elastic data memory request generator to read protobuf trace containing execution trace annotated with data and ordering dependencies |
| EmbeddedPyBind | |
| EmbeddedPython | |
| X86ISA::EmulEnv | |
| IniFile::Entry | A single key/value pair |
| EtherSwitch::Interface::PortFifo::EntryOrder | |
| eth_addr | |
| Net::EthAddr | |
| eth_hdr | |
| Net::EthHdr | |
| EtherInt | |
| DistEtherLink::LocalIface | Interface to the local simulated system |
| EtherLink::Interface | |
| EtherSwitch::Interface | Model for an Ethernet switch port |
| EtherTapInt | |
| IGbEInt | |
| NSGigEInt | |
| Sinic::Interface | |
| EthPacketData | |
| Net::EthPtr | |
| EventBase | Common base class for Event and GlobalEvent, so they can share flag and priority definitions and accessor functions |
| BaseGlobalEvent | Common base class for GlobalEvent and GlobalSyncEvent |
| BaseGlobalEventTemplate< Derived > | Funky intermediate class to support CRTP so that we can have a common constructor to create the local events, even though the types of the local events are defined in the derived classes |
| BaseGlobalEventTemplate< GlobalEvent > | |
| GlobalEvent | The main global event class |
| DebugBreakEvent | |
| GlobalSimLoopExitEvent | |
| Stats::StatEvent | Event to dump and/or reset the statistics |
| BaseGlobalEventTemplate< GlobalSyncEvent > | |
| GlobalSyncEvent | A special global event that synchronizes all threads and forces them to process asynchronously enqueued events |
| DistIface::SyncEvent | The global event to schedule periodic dist sync |
| Event | |
| AtomicSimpleCPU::TickEvent | |
| BaseGlobalEvent::BarrierEvent | The base class for the local events that will synchronize threads to perform the global event |
| GlobalEvent::BarrierEvent | |
| GlobalSyncEvent::BarrierEvent | |
| BaseKvmCPU::TickEvent | |
| BasePixelPump::PixelEvent | Callback helper class with suspend support |
| BaseRemoteGDB::SingleStepEvent | |
| BaseRemoteGDB::TrapEvent | |
| ComputeUnit::DataPort::MemReqEvent | |
| ComputeUnit::DataPort::MemRespEvent | |
| Consumer::ConsumerEvent | |
| CountedExitEvent | |
| CpuEvent | This class creates a global list of events that need a pointer to a thread context |
| CpuEventWrapper< T, F > | |
| DefaultCommit< Impl >::TrapEvent | Event class used to schedule a squash due to a trap (fault or interrupt) to happen on a specific cycle |
| DefaultFetch< Impl >::FinishTranslationEvent | |
| DmaCallback::DmaChunkEvent | Event invoked by DmaDevice on completion of each chunk |
| DmaReadFifo::DmaDoneEvent | |
| DVFSHandler::UpdateEvent | Update performance level event, encapsulates all the required information for a future call to change a domain's performance level |
| EndQuiesceEvent | Event for timing out quiesce instruction |
| EtherBus::DoneEvent | |
| EtherTapBase::TxEvent | |
| EventWrapper< T, F > | |
| EventWrapper< ArchTimer,&ArchTimer::counterLimitReached > | |
| EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::doL0LongDescriptorWrapper > | |
| EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::doL1DescriptorWrapper > | |
| EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::doL1LongDescriptorWrapper > | |
| EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::doL2DescriptorWrapper > | |
| EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::doL2LongDescriptorWrapper > | |
| EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::doL3LongDescriptorWrapper > | |
| EventWrapper< ArmISA::TableWalker,&ArmISA::TableWalker::processWalkWrapper > | |
| EventWrapper< BaseCache::CacheSlavePort,&BaseCache::CacheSlavePort::processSendRetry > | |
| EventWrapper< BaseXBar::Layer,&BaseXBar::Layer::releaseLayer > | |
| EventWrapper< Bridge::BridgeMasterPort,&Bridge::BridgeMasterPort::trySendTiming > | |
| EventWrapper< Bridge::BridgeSlavePort,&Bridge::BridgeSlavePort::trySendTiming > | |
| EventWrapper< Cache,&Cache::writebackTempBlockAtomic > | |
| EventWrapper< CommMonitor,&CommMonitor::samplePeriodic > | |
| EventWrapper< CopyEngine::CopyEngineChannel,&CopyEngine::CopyEngineChannel::fetchAddrComplete > | |
| EventWrapper< CopyEngine::CopyEngineChannel,&CopyEngine::CopyEngineChannel::fetchDescComplete > | |
| EventWrapper< CopyEngine::CopyEngineChannel,&CopyEngine::CopyEngineChannel::readCopyBytesComplete > | |
| EventWrapper< CopyEngine::CopyEngineChannel,&CopyEngine::CopyEngineChannel::writeCopyBytesComplete > | |
| EventWrapper< CopyEngine::CopyEngineChannel,&CopyEngine::CopyEngineChannel::writeStatusComplete > | |
| EventWrapper< CpuLocalTimer::Timer,&CpuLocalTimer::Timer::timerAtZero > | |
| EventWrapper< CpuLocalTimer::Timer,&CpuLocalTimer::Timer::watchdogAtZero > | |
| EventWrapper< Device,&Device::txEventTransmit > | |
| EventWrapper< DmaPort,&DmaPort::sendDma > | |
| EventWrapper< DRAMCtrl,&DRAMCtrl::processNextReqEvent > | |
| EventWrapper< DRAMCtrl,&DRAMCtrl::processRespondEvent > | |
| EventWrapper< DRAMCtrl::Rank,&DRAMCtrl::Rank::processActivateEvent > | |
| EventWrapper< DRAMCtrl::Rank,&DRAMCtrl::Rank::processPowerEvent > | |
| EventWrapper< DRAMCtrl::Rank,&DRAMCtrl::Rank::processPrechargeEvent > | |
| EventWrapper< DRAMCtrl::Rank,&DRAMCtrl::Rank::processRefreshEvent > | |
| EventWrapper< DRAMCtrl::Rank,&DRAMCtrl::Rank::processWakeUpEvent > | |
| EventWrapper< DRAMCtrl::Rank,&DRAMCtrl::Rank::processWriteDoneEvent > | |
| EventWrapper< DRAMSim2,&DRAMSim2::sendResponse > | |
| EventWrapper< DRAMSim2,&DRAMSim2::tick > | |
| EventWrapper< ElasticTrace,&ElasticTrace::regEtraceListeners > | |
| EventWrapper< EnergyCtrl,&EnergyCtrl::updatePLAck > | |
| EventWrapper< EtherSwitch::Interface,&EtherSwitch::Interface::transmit > | |
| EventWrapper< FlashDevice,&FlashDevice::actionComplete > | |
| EventWrapper< HDLcd,&HDLcd::virtRefresh > | |
| EventWrapper< IdeDisk,&IdeDisk::dmaPrdReadDone > | |
| EventWrapper< IdeDisk,&IdeDisk::dmaReadDone > | |
| EventWrapper< IdeDisk,&IdeDisk::dmaWriteDone > | |
| EventWrapper< IdeDisk,&IdeDisk::doDmaRead > | |
| EventWrapper< IdeDisk,&IdeDisk::doDmaTransfer > | |
| EventWrapper< IdeDisk,&IdeDisk::doDmaWrite > | |
| EventWrapper< IGbE,&IGbE::delayIntEvent > | |
| EventWrapper< IGbE,&IGbE::radvProcess > | |
| EventWrapper< IGbE,&IGbE::rdtrProcess > | |
| EventWrapper< IGbE,&IGbE::tadvProcess > | |
| EventWrapper< IGbE,&IGbE::tick > | |
| EventWrapper< IGbE,&IGbE::tidvProcess > | |
| EventWrapper< IGbE::DescCache,&IGbE::DescCache::fetchComplete > | |
| EventWrapper< IGbE::DescCache,&IGbE::DescCache::fetchDescriptors1 > | |
| EventWrapper< IGbE::DescCache,&IGbE::DescCache::wbComplete > | |
| EventWrapper< IGbE::DescCache,&IGbE::DescCache::writeback1 > | |
| EventWrapper< IGbE::RxDescCache,&IGbE::RxDescCache::pktComplete > | |
| EventWrapper< IGbE::RxDescCache,&IGbE::RxDescCache::pktSplitDone > | |
| EventWrapper< IGbE::TxDescCache,&IGbE::TxDescCache::headerComplete > | |
| EventWrapper< IGbE::TxDescCache,&IGbE::TxDescCache::nullCallback > | |
| EventWrapper< IGbE::TxDescCache,&IGbE::TxDescCache::pktComplete > | |
| EventWrapper< Link,&Link::processTxQueue > | |
| EventWrapper< Link,&Link::txDone > | |
| EventWrapper< MasterPort,&MasterPort::sendRetryResp > | |
| EventWrapper< MemTest,&MemTest::noRequest > | |
| EventWrapper< MemTest,&MemTest::noResponse > | |
| EventWrapper< MemTest,&MemTest::tick > | |
| EventWrapper< NSGigE,&NSGigE::rxDmaReadDone > | |
| EventWrapper< NSGigE,&NSGigE::rxDmaWriteDone > | |
| EventWrapper< NSGigE,&NSGigE::rxKick > | |
| EventWrapper< NSGigE,&NSGigE::txDmaReadDone > | |
| EventWrapper< NSGigE,&NSGigE::txDmaWriteDone > | |
| EventWrapper< NSGigE,&NSGigE::txEventTransmit > | |
| EventWrapper< NSGigE,&NSGigE::txKick > | |
| EventWrapper< PacketQueue,&PacketQueue::processSendEvent > | |
| EventWrapper< Pl011,&Pl011::generateInterrupt > | |
| EventWrapper< PL031,&PL031::counterMatch > | |
| EventWrapper< Pl050,&Pl050::generateInterrupt > | |
| EventWrapper< Pl111,&Pl111::fillFifo > | |
| EventWrapper< Pl111,&Pl111::generateInterrupt > | |
| EventWrapper< Pl111,&Pl111::readFramebuffer > | |
| EventWrapper< Root,&Root::timeSync > | |
| EventWrapper< RxLink,&RxLink::rxDone > | |
| EventWrapper< SerialLink::SerialLinkMasterPort,&SerialLink::SerialLinkMasterPort::trySendTiming > | |
| EventWrapper< SerialLink::SerialLinkSlavePort,&SerialLink::SerialLinkSlavePort::trySendTiming > | |
| EventWrapper< SimpleMemory,&SimpleMemory::dequeue > | |
| EventWrapper< SimpleMemory,&SimpleMemory::release > | |
| EventWrapper< Sinic::Device,&Sinic::Device::rxDmaDone > | |
| EventWrapper< Sinic::Device,&Sinic::Device::txDmaDone > | |
| EventWrapper< Sp804::Timer,&Sp804::Timer::counterAtZero > | |
| EventWrapper< ThermalModel,&ThermalModel::doStep > | |
| EventWrapper< TimingSimpleCPU,&TimingSimpleCPU::fetch > | |
| EventWrapper< TraceCPU,&TraceCPU::schedDcacheNext > | |
| EventWrapper< TraceCPU,&TraceCPU::schedIcacheNext > | |
| EventWrapper< TrafficGen,&TrafficGen::noProgress > | |
| EventWrapper< TrafficGen,&TrafficGen::update > | |
| EventWrapper< TxLink,&TxLink::txDone > | |
| EventWrapper< UFSHostDevice,&UFSHostDevice::finalUTP > | |
| EventWrapper< UFSHostDevice,&UFSHostDevice::readDone > | |
| EventWrapper< UFSHostDevice,&UFSHostDevice::readGarbage > | |
| EventWrapper< UFSHostDevice,&UFSHostDevice::SCSIStart > | |
| EventWrapper< UFSHostDevice,&UFSHostDevice::UFSHostDevice::taskStart > | |
| EventWrapper< UFSHostDevice,&UFSHostDevice::UFSHostDevice::transferStart > | |
| EventWrapper< UFSHostDevice,&UFSHostDevice::writeDone > | |
| EventWrapper< X86ISA::GpuTLB,&X86ISA::GpuTLB::cleanup > | |
| EventWrapper< X86ISA::GpuTLB,&X86ISA::GpuTLB::exitCallback > | |
| EventWrapper< X86ISA::Walker,&X86ISA::Walker::startWalkWrapper > | |
| FullO3CPU< Impl >::TickEvent | |
| GarnetSyntheticTraffic::TickEvent | |
| GPUCoalescer::GPUCoalescerWakeupEvent | |
| GPUCoalescer::IssueEvent | |
| GpuDispatcher::TickEvent | |
| InstructionQueue< Impl >::FUCompletion | FU completion event class |
| Intel8254Timer::Counter::CounterEvent | Event for counter interrupt |
| LdsState::TickEvent | Event to allow event-driven execution |
| LocalSimLoopExitEvent | |
| LSQUnit< Impl >::WritebackEvent | Writeback event, specifically for when stores forward data to loads |
| MC146818::RTCEvent | Event for RTC periodic interrupt |
| MC146818::RTCTickEvent | Event for RTC periodic interrupt |
| Minor::LSQ::SplitDataRequest::TranslationEvent | Event to step between translations |
| MipsISA::ISA::CP0Event | |
| Pl390::PostIntEvent | Event definition to post interrupt to CPU after a delay |
| PyEvent | PyBind wrapper for Events |
| RubyDirectedTester::DirectedStartEvent | |
| RubySystem::RubyEvent | |
| RubyTester::CheckStartEvent | |
| Sequencer::SequencerWakeupEvent | |
| Shader::TickEvent | |
| StubSlavePort::ResponseEvent | |
| Ticked::ClockEvent | An event to call process periodically |
| TimingSimpleCPU::IprEvent | |
| TimingSimpleCPU::TimingCPUPort::TickEvent | |
| TimingSimpleCPU::IcachePort::ITickEvent | |
| TLBCoalescer::CleanupEvent | |
| TLBCoalescer::IssueProbeEvent | |
| Uart8250::IntrEvent | |
| VGic::PostVIntEvent | Event definition to post interrupt to CPU after a delay |
| X86ISA::GpuTLB::TLBEvent | |
| EventManager | |
| BasePixelPump | Timing generator for a pixel-based display |
| DRAMCtrl::Rank | Rank class includes a vector of banks |
| Intel8254Timer | Programmable Interval Timer (Intel 8254) |
| X86ISA::I8254::X86Intel8254Timer | |
| MC146818 | Real-Time Clock (MC146818) |
| MaltaIO::RTC | |
| TsunamiIO::RTC | |
| X86ISA::Cmos::X86RTC | |
| SimObject | Abstract superclass for simulation objects |
| EventQueue | Queue of events sorted in time order |
| ArmISA::PMU::EventType | Event type configuration |
| exception | |
| CxxConfigManager::Exception | Exception for instantiate/post-instantiate errors |
| RejectException | |
| ExecContext | The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate the state of the CPU model |
| BaseDynInst< Impl > | |
| BaseO3DynInst< Impl > | |
| CheckerCPU | CheckerCPU class |
| Minor::ExecContext | ExecContext bears the exec_context interface for Minor |
| SimpleExecContext | |
| ExecStage | |
| Minor::Execute::ExecuteThreadInfo | |
| X86ISA::ExtMachInst | |
| FaultBase | |
| AlphaISA::AlphaFault | |
| AlphaISA::AlignmentFault | |
| AlphaISA::ArithmeticFault | |
| AlphaISA::DtbFault | |
| AlphaISA::DtbAcvFault | |
| AlphaISA::DtbAlignmentFault | |
| AlphaISA::DtbPageFault | |
| AlphaISA::NDtbMissFault | |
| AlphaISA::PDtbMissFault | |
| AlphaISA::FloatEnableFault | |
| AlphaISA::IntegerOverflowFault | |
| AlphaISA::InterruptFault | |
| AlphaISA::ItbFault | |
| AlphaISA::ItbAcvFault | |
| AlphaISA::ItbPageFault | |
| AlphaISA::MachineCheckFault | |
| AlphaISA::PalFault | |
| AlphaISA::ResetFault | |
| AlphaISA::UnimplementedOpcodeFault | |
| ArmISA::ArmFault | |
| ArmISA::ArmFaultVals< ArmSev > | |
| ArmISA::ArmSev | |
| ArmISA::ArmFaultVals< DataAbort > | |
| ArmISA::AbortFault< DataAbort > | |
| ArmISA::DataAbort | |
| ArmISA::ArmFaultVals< FastInterrupt > | |
| ArmISA::FastInterrupt | |
| ArmISA::ArmFaultVals< FlushPipe > | |
| ArmISA::FlushPipe | |
| ArmISA::ArmFaultVals< HypervisorCall > | |
| ArmISA::HypervisorCall | |
| ArmISA::ArmFaultVals< HypervisorTrap > | |
| ArmISA::HypervisorTrap | |
| ArmISA::ArmFaultVals< IllegalInstSetStateFault > | |
| ArmISA::IllegalInstSetStateFault | Illegal Instruction Set State fault (AArch64 only) |
| ArmISA::ArmFaultVals< Interrupt > | |
| ArmISA::Interrupt | |
| ArmISA::ArmFaultVals< PCAlignmentFault > | |
| ArmISA::PCAlignmentFault | PC alignment fault (AArch64 only) |
| ArmISA::ArmFaultVals< PrefetchAbort > | |
| ArmISA::AbortFault< PrefetchAbort > | |
| ArmISA::PrefetchAbort | |
| ArmISA::ArmFaultVals< Reset > | |
| ArmISA::Reset | |
| ArmISA::ArmFaultVals< SecureMonitorCall > | |
| ArmISA::SecureMonitorCall | |
| ArmISA::ArmFaultVals< SecureMonitorTrap > | |
| ArmISA::SecureMonitorTrap | |
| ArmISA::ArmFaultVals< SPAlignmentFault > | |
| ArmISA::SPAlignmentFault | Stack pointer alignment fault (AArch64 only) |
| ArmISA::ArmFaultVals< SupervisorCall > | |
| ArmISA::SupervisorCall | |
| ArmISA::ArmFaultVals< SupervisorTrap > | |
| ArmISA::SupervisorTrap | |
| ArmISA::ArmFaultVals< SystemError > | |
| ArmISA::SystemError | System error (AArch64 only) |
| ArmISA::ArmFaultVals< UndefinedInstruction > | |
| ArmISA::UndefinedInstruction | |
| ArmISA::ArmFaultVals< VirtualDataAbort > | |
| ArmISA::AbortFault< VirtualDataAbort > | |
| ArmISA::VirtualDataAbort | |
| ArmISA::ArmFaultVals< VirtualFastInterrupt > | |
| ArmISA::VirtualFastInterrupt | |
| ArmISA::ArmFaultVals< VirtualInterrupt > | |
| ArmISA::VirtualInterrupt | |
| ArmISA::ArmFaultVals< T > | |
| ArmISA::AbortFault< T > | |
| GenericAlignmentFault | |
| GenericISA::M5DebugFault | |
| GenericISA::M5VarArgsFault< Func > | |
| GenericPageTableFault | |
| MipsISA::MipsFaultBase | |
| MipsISA::MipsFault< AddressErrorFault > | |
| MipsISA::AddressFault< AddressErrorFault > | |
| MipsISA::AddressErrorFault | |
| MipsISA::MipsFault< BreakpointFault > | |
| MipsISA::BreakpointFault | |
| MipsISA::MipsFault< CoprocessorUnusableFault > | |
| MipsISA::CoprocessorUnusableFault | |
| MipsISA::MipsFault< DspStateDisabledFault > | |
| MipsISA::DspStateDisabledFault | |
| MipsISA::MipsFault< IntegerOverflowFault > | |
| MipsISA::IntegerOverflowFault | |
| MipsISA::MipsFault< InterruptFault > | |
| MipsISA::InterruptFault | |
| MipsISA::MipsFault< MachineCheckFault > | |
| MipsISA::MachineCheckFault | |
| MipsISA::MipsFault< NonMaskableInterrupt > | |
| MipsISA::NonMaskableInterrupt | |
| MipsISA::MipsFault< ReservedInstructionFault > | |
| MipsISA::ReservedInstructionFault | |
| MipsISA::MipsFault< ResetFault > | |
| MipsISA::ResetFault | |
| MipsISA::MipsFault< SoftResetFault > | |
| MipsISA::SoftResetFault | |
| MipsISA::MipsFault< SystemCallFault > | |
| MipsISA::SystemCallFault | |
| MipsISA::MipsFault< ThreadFault > | |
| MipsISA::ThreadFault | |
| MipsISA::MipsFault< TlbInvalidFault > | |
| MipsISA::AddressFault< TlbInvalidFault > | |
| MipsISA::TlbFault< TlbInvalidFault > | |
| MipsISA::TlbInvalidFault | |
| MipsISA::MipsFault< TlbModifiedFault > | |
| MipsISA::AddressFault< TlbModifiedFault > | |
| MipsISA::TlbFault< TlbModifiedFault > | |
| MipsISA::TlbModifiedFault | |
| MipsISA::MipsFault< TlbRefillFault > | |
| MipsISA::AddressFault< TlbRefillFault > | |
| MipsISA::TlbFault< TlbRefillFault > | |
| MipsISA::TlbRefillFault | |
| MipsISA::MipsFault< TrapFault > | |
| MipsISA::TrapFault | |
| MipsISA::MipsFault< T > | |
| MipsISA::AddressFault< T > | |
| MipsISA::TlbFault< T > | |
| PowerISA::PowerFault | |
| PowerISA::AlignmentFault | |
| PowerISA::MachineCheckFault | |
| PowerISA::UnimplementedOpcodeFault | |
| ReExec | |
| RiscvISA::RiscvFault | |
| RiscvISA::BreakpointFault | |
| RiscvISA::IllegalFrmFault | |
| RiscvISA::SyscallFault | |
| RiscvISA::UnimplementedFault | |
| RiscvISA::UnknownInstFault | |
| SparcISA::SparcFaultBase | |
| SparcISA::SparcFault< CleanWindow > | |
| SparcISA::CleanWindow | |
| SparcISA::SparcFault< CpuMondo > | |
| SparcISA::CpuMondo | |
| SparcISA::SparcFault< DataAccessError > | |
| SparcISA::DataAccessError | |
| SparcISA::SparcFault< DataAccessException > | |
| SparcISA::DataAccessException | |
| SparcISA::SparcFault< DataAccessProtection > | |
| SparcISA::DataAccessProtection | |
| SparcISA::SparcFault< DataInvalidTSBEntry > | |
| SparcISA::DataInvalidTSBEntry | |
| SparcISA::SparcFault< DataRealTranslationMiss > | |
| SparcISA::DataRealTranslationMiss | |
| SparcISA::SparcFault< DevMondo > | |
| SparcISA::DevMondo | |
| SparcISA::SparcFault< DivisionByZero > | |
| SparcISA::DivisionByZero | |
| SparcISA::SparcFault< ExternallyInitiatedReset > | |
| SparcISA::ExternallyInitiatedReset | |
| SparcISA::SparcFault< FastDataAccessMMUMiss > | |
| SparcISA::FastDataAccessMMUMiss | |
| SparcISA::SparcFault< FastDataAccessProtection > | |
| SparcISA::FastDataAccessProtection | |
| SparcISA::SparcFault< FastInstructionAccessMMUMiss > | |
| SparcISA::FastInstructionAccessMMUMiss | |
| SparcISA::SparcFault< FillNNormal > | |
| SparcISA::EnumeratedFault< FillNNormal > | |
| SparcISA::FillNNormal | |
| SparcISA::SparcFault< FillNOther > | |
| SparcISA::EnumeratedFault< FillNOther > | |
| SparcISA::FillNOther | |
| SparcISA::SparcFault< FpDisabled > | |
| SparcISA::FpDisabled | |
| SparcISA::SparcFault< FpExceptionIEEE754 > | |
| SparcISA::FpExceptionIEEE754 | |
| SparcISA::SparcFault< FpExceptionOther > | |
| SparcISA::FpExceptionOther | |
| SparcISA::SparcFault< HstickMatch > | |
| SparcISA::HstickMatch | |
| SparcISA::SparcFault< IllegalInstruction > | |
| SparcISA::IllegalInstruction | |
| SparcISA::SparcFault< InstructionAccessError > | |
| SparcISA::InstructionAccessError | |
| SparcISA::SparcFault< InstructionAccessException > | |
| SparcISA::InstructionAccessException | |
| SparcISA::SparcFault< InstructionBreakpoint > | |
| SparcISA::InstructionBreakpoint | |
| SparcISA::SparcFault< InstructionInvalidTSBEntry > | |
| SparcISA::InstructionInvalidTSBEntry | |
| SparcISA::SparcFault< InstructionRealTranslationMiss > | |
| SparcISA::InstructionRealTranslationMiss | |
| SparcISA::SparcFault< InternalProcessorError > | |
| SparcISA::InternalProcessorError | |
| SparcISA::SparcFault< InterruptLevelN > | |
| SparcISA::EnumeratedFault< InterruptLevelN > | |
| SparcISA::InterruptLevelN | |
| SparcISA::SparcFault< InterruptVector > | |
| SparcISA::InterruptVector | |
| SparcISA::SparcFault< LDDFMemAddressNotAligned > | |
| SparcISA::LDDFMemAddressNotAligned | |
| SparcISA::SparcFault< LDQFMemAddressNotAligned > | |
| SparcISA::LDQFMemAddressNotAligned | |
| SparcISA::SparcFault< MemAddressNotAligned > | |
| SparcISA::MemAddressNotAligned | |
| SparcISA::SparcFault< PAWatchpoint > | |
| SparcISA::PAWatchpoint | |
| SparcISA::SparcFault< PowerOnReset > | |
| SparcISA::PowerOnReset | |
| SparcISA::SparcFault< PrivilegedAction > | |
| SparcISA::PrivilegedAction | |
| SparcISA::SparcFault< PrivilegedOpcode > | |
| SparcISA::PrivilegedOpcode | |
| SparcISA::SparcFault< REDStateException > | |
| SparcISA::REDStateException | |
| SparcISA::SparcFault< ResumableError > | |
| SparcISA::ResumableError | |
| SparcISA::SparcFault< SoftwareInitiatedReset > | |
| SparcISA::SoftwareInitiatedReset | |
| SparcISA::SparcFault< SpillNNormal > | |
| SparcISA::EnumeratedFault< SpillNNormal > | |
| SparcISA::SpillNNormal | |
| SparcISA::SparcFault< SpillNOther > | |
| SparcISA::EnumeratedFault< SpillNOther > | |
| SparcISA::SpillNOther | |
| SparcISA::SparcFault< STDFMemAddressNotAligned > | |
| SparcISA::STDFMemAddressNotAligned | |
| SparcISA::SparcFault< StoreError > | |
| SparcISA::StoreError | |
| SparcISA::SparcFault< STQFMemAddressNotAligned > | |
| SparcISA::STQFMemAddressNotAligned | |
| SparcISA::SparcFault< TagOverflow > | |
| SparcISA::TagOverflow | |
| SparcISA::SparcFault< TrapInstruction > | |
| SparcISA::EnumeratedFault< TrapInstruction > | |
| SparcISA::TrapInstruction | |
| SparcISA::SparcFault< TrapLevelZero > | |
| SparcISA::TrapLevelZero | |
| SparcISA::SparcFault< VAWatchpoint > | |
| SparcISA::VAWatchpoint | |
| SparcISA::SparcFault< WatchDogReset > | |
| SparcISA::WatchDogReset | |
| SparcISA::SparcFault< T > | |
| SparcISA::EnumeratedFault< T > | |
| SyscallRetryFault | |
| UnimpFault | |
| X86ISA::UnimpInstFault | |
| X86ISA::X86FaultBase | |
| X86ISA::DebugException | |
| X86ISA::SecurityException | |
| X86ISA::X86Abort | |
| X86ISA::DoubleFault | |
| X86ISA::MachineCheck | |
| X86ISA::X86Fault | |
| X86ISA::AlignmentCheck | |
| X86ISA::BoundRange | |
| X86ISA::DeviceNotAvailable | |
| X86ISA::DivideError | |
| X86ISA::GeneralProtection | |
| X86ISA::InvalidOpcode | |
| X86ISA::InvalidTSS | |
| X86ISA::PageFault | |
| X86ISA::SegmentNotPresent | |
| X86ISA::SIMDFloatingPointFault | |
| X86ISA::StackFault | |
| X86ISA::X87FpExceptionPending | |
| X86ISA::X86Interrupt | |
| X86ISA::ExternalInterrupt | |
| X86ISA::InitInterrupt | |
| X86ISA::NonMaskableInterrupt | |
| X86ISA::SoftwareInterrupt | |
| X86ISA::StartupInterrupt | |
| X86ISA::SystemManagementInterrupt | |
| X86ISA::X86Trap | |
| X86ISA::Breakpoint | |
| X86ISA::OverflowTrap | |
| SparcISA::SparcFaultBase::FaultVals | |
| ArmISA::ArmFault::FaultVals | |
| MipsISA::MipsFaultBase::FaultVals | |
| FDArray | |
| Minor::Fetch1::Fetch1ThreadInfo | Stage cycle-by-cycle state |
| Minor::Fetch2::Fetch2ThreadInfo | Data members after this line are cycle-to-cycle state |
| FetchStage | |
| FetchUnit | |
| Fifo< T > | Simple FIFO implementation backed by a circular buffer |
| Fifo< uint8_t > | |
| Bitmap::FileHeader | |
| TraceCPU::FixedRetryGen | Generator to read protobuf trace containing memory requests at fixed timestamps, perform flow control and issue memory requests |
| Debug::Flag | |
| Debug::AllFlags | |
| Debug::CompoundFlag | |
| Debug::SimpleFlag | |
| Flags< T > | |
| Flags< FlagsType > | |
| Flags< FlagsType >< FlagsType > | |
| FlashDevice::FlashDeviceStats | |
| flit | |
| Credit | |
| flitBuffer | |
| Float16 | |
| LTAGE::FoldedHistory | |
| cp::Format | |
| Minor::ForwardInstData | Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appropriate to the configured stage widths |
| Minor::ForwardLineData | Line fetch data in the forward direction |
| VncServer::FrameBufferRect | |
| VncServer::FrameBufferUpdate | |
| VncInput::FrameBufferUpdateReq | |
| DefaultRename< Impl >::FreeEntries | Structures whose free entries impact the amount of instructions that can be renamed |
| FUPool::FUIdxQueue | Class that implements a circular queue to hold FU indices |
| FunctionProfile | |
| FuncUnit | |
| Minor::FUPipeline | A functional unit configured from a MinorFU object |
| FutexKey | FutexKey class defines an unique identifier for a particular futex in the system |
| FXSave | |
| GdbCommand | |
| GDBListener | |
| Stats::Global | |
| GlobalMemPipeline | |
| GPUCoalescerRequest | |
| GPUExecContext | |
| GPUDynInst | |
| HsailISA::GPUISA | |
| GPUStaticInstFlags | |
| GPUStaticInst | |
| HsailISA::HsailGPUStaticInst | |
| HsailISA::AtomicInstBase< MemDataType::OperandType, AddrOperandType, NumSrcOperands, HasDst > | |
| HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst > | |
| HsailISA::BrInstBase< LabelOperand > | |
| HsailISA::BrDirectInst | |
| HsailISA::BrInstBase< SRegOperand > | |
| HsailISA::BrIndirectInst | |
| HsailISA::BrnInstBase< LabelOperand > | |
| HsailISA::BrnDirectInst | |
| HsailISA::BrnInstBase< SRegOperand > | |
| HsailISA::BrnIndirectInst | |
| HsailISA::CbrInstBase< LabelOperand > | |
| HsailISA::CbrDirectInst | |
| HsailISA::CbrInstBase< SRegOperand > | |
| HsailISA::CbrIndirectInst | |
| HsailISA::CommonInstBase< DataType::OperandType, DataType::OperandType, NumSrcOperands > | |
| HsailISA::ArithInst< DataType, NumSrcOperands > | |
| HsailISA::CommonInstBase< DestDataType::OperandType, SrcDataType::OperandType, 1 > | |
| HsailISA::CvtInst< DestDataType, SrcDataType > | |
| HsailISA::PopcountInst< DestDataType, SrcDataType > | |
| HsailISA::CommonInstBase< DestDataType::OperandType, SrcDataType::OperandType, 2 > | |
| HsailISA::CmpInstBase< DestDataType::OperandType, SrcDataType::OperandType > | |
| HsailISA::CmpInst< DestDataType, SrcDataType > | |
| HsailISA::CommonInstBase< DestOperandType, SrcOperandType, 2 > | |
| HsailISA::CmpInstBase< DestOperandType, SrcOperandType > | |
| HsailISA::AtomicInstBase< OperandType, AddrOperandType, NumSrcOperands, HasDst > | |
| HsailISA::BrInstBase< TargetType > | |
| HsailISA::BrnInstBase< TargetType > | |
| HsailISA::Call | |
| HsailISA::CbrInstBase< TargetType > | |
| HsailISA::CommonInstBase< DestOperandType, SrcOperandType, NumSrcOperands > | |
| HsailISA::LdaInstBase< DestOperandType, AddrOperandType > | |
| HsailISA::LdInstBase< MemOperandType, DestOperandType, AddrOperandType > | |
| HsailISA::SpecialInst1SrcBase< DestOperandType > | |
| HsailISA::SpecialInstNoSrcBase< DestOperandType > | |
| HsailISA::SpecialInstNoSrcNoDest | |
| HsailISA::Barrier | |
| HsailISA::MemFence | |
| HsailISA::Ret | |
| HsailISA::StInstBase< MemDataType, SrcOperandType, AddrOperandType > | |
| HsailISA::Stub | |
| HsailISA::ThreeNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType, Src2OperandType > | |
| HsailISA::TwoNonUniformSourceInstBase< DestOperandType, Src0OperandType, Src1OperandType > | |
| HsailISA::LdaInstBase< DestDataType::OperandType, AddrOperandType > | |
| HsailISA::LdaInst< DestDataType, AddrOperandType > | |
| HsailISA::LdInstBase< MemDataType::CType, DestDataType::OperandType, AddrOperandType > | |
| HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > | |
| HsailISA::SpecialInst1SrcBase< DestDataType::OperandType > | |
| HsailISA::SpecialInst1Src< DestDataType > | |
| HsailISA::SpecialInstNoSrcBase< DestDataType::OperandType > | |
| HsailISA::SpecialInstNoSrc< DestDataType > | |
| HsailISA::StInstBase< MemDataType, SrcDataType::OperandType, AddrOperandType > | |
| HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > | |
| HsailISA::ThreeNonUniformSourceInstBase< DataType::OperandType, B1::OperandType, DataType::OperandType, DataType::OperandType > | |
| HsailISA::ThreeNonUniformSourceInst< DataType, B1, DataType, DataType > | |
| HsailISA::CmovInst< DataType > | |
| HsailISA::ThreeNonUniformSourceInstBase< DataType::OperandType, DataType::OperandType, U32::OperandType, U32::OperandType > | |
| HsailISA::ThreeNonUniformSourceInst< DataType, DataType, U32, U32 > | |
| HsailISA::ExtractInsertInst< DataType > | |
| HsailISA::ThreeNonUniformSourceInstBase< DestDataType::OperandType, Src0DataType::OperandType, Src1DataType::OperandType, Src2DataType::OperandType > | |
| HsailISA::ThreeNonUniformSourceInst< DestDataType, Src0DataType, Src1DataType, Src2DataType > | |
| HsailISA::TwoNonUniformSourceInstBase< B1::OperandType, DataType::OperandType, U32::OperandType > | |
| HsailISA::TwoNonUniformSourceInst< B1, DataType, U32 > | |
| HsailISA::ClassInst< DataType > | |
| HsailISA::TwoNonUniformSourceInstBase< DataType::OperandType, DataType::OperandType, U32::OperandType > | |
| HsailISA::TwoNonUniformSourceInst< DataType, DataType, U32 > | |
| HsailISA::ShiftInst< DataType > | |
| HsailISA::TwoNonUniformSourceInstBase< DestDataType::OperandType, Src0DataType::OperandType, Src1DataType::OperandType > | |
| HsailISA::TwoNonUniformSourceInst< DestDataType, Src0DataType, Src1DataType > | |
| KernelLaunchStaticInst | |
| TraceCPU::ElasticDataGen::GraphNode | The struct GraphNode stores an instruction in the trace file |
| ExternalMaster::Handler | |
| ExternalSlave::Handler | |
| StubSlavePortHandler | |
| TraceCPU::ElasticDataGen::HardwareResource | Models structures that hold the in-flight nodes |
| hash | |
| std::hash< ArmISA::ExtMachInst > | |
| std::hash< PowerISA::ExtMachInst > | |
| std::hash< BasicBlockRange > | |
| std::hash< FutexKey > | The unordered_map structure needs the parenthesis operator defined for std::hash if a user defined key is used |
| std::hash< X86ISA::ExtMachInst > | |
| UFSHostDevice::HCIMem | Host Controller Interface This is a set of registers that allow the driver to control the transactions to the flash devices |
| DistHeaderPkt::Header | |
| VirtQueue::VirtRing< T >::Header | |
| HexFile | |
| Histogram | |
| IndirectPredictor::HistoryEntry | |
| Stats::HistStor | Templatized storage and interface for a histogram stat |
| HostState | |
| HsaCode | |
| HsailCode | |
| HsaDriverSizes | |
| HsailISA::HsailDataType< _OperandType, _CType, _memType, _vgprType, IsBits > | |
| HsailISA::HsailOperandType< _DestOperand, _SrcOperand > | |
| HsaKernelInfo | |
| HsaObject | |
| BrigObject | |
| HsaQueueEntry | |
| TimeBufStruct< Impl >::iewComm | |
| IndirectPredictor | |
| Sinic::Regs::Info | |
| Stats::Info | |
| Stats::DistInfo | |
| Stats::InfoProxy< Stat, DistInfo > | |
| Stats::DistInfoProxy< Stat > | |
| Stats::ScalarInfo | |
| Stats::InfoProxy< Stat, ScalarInfo > | |
| Stats::ScalarInfoProxy< Stat > | |
| Stats::ProxyInfo | |
| Stats::FunctorProxy< T > | |
| Stats::MethodProxy< T, V > | A proxy similar to the FunctorProxy, but allows calling a method of a bound object, instead of a global free-standing function |
| Stats::ValueProxy< T > | |
| Stats::SparseHistInfo | |
| Stats::InfoProxy< Stat, SparseHistInfo > | |
| Stats::SparseHistInfoProxy< Stat > | |
| Stats::Vector2dInfo | |
| Stats::InfoProxy< Stat, Vector2dInfo > | |
| Stats::Vector2dInfoProxy< Stat > | |
| Stats::VectorDistInfo | |
| Stats::InfoProxy< Stat, VectorDistInfo > | |
| Stats::VectorDistInfoProxy< Stat > | |
| Stats::VectorInfo | |
| Stats::InfoProxy< Stat, VectorInfo > | |
| Stats::VectorInfoProxy< Stat > | |
| Stats::FormulaInfo | |
| Stats::InfoProxy< Stat, FormulaInfo > | |
| Stats::FormulaInfoProxy< Stat > | |
| Stats::InfoAccess | |
| Stats::DataWrap< Average, ScalarInfoProxy > | |
| Stats::ScalarBase< Average, AvgStor > | |
| Stats::Average | A stat that calculates the per tick average of a value |
| Stats::DataWrap< AverageDeviation, DistInfoProxy > | |
| Stats::DistBase< AverageDeviation, AvgSampleStor > | |
| Stats::AverageDeviation | Calculates the per tick mean and variance of the samples |
| Stats::DataWrap< AverageVector, VectorInfoProxy > | |
| Stats::DataWrapVec< AverageVector, VectorInfoProxy > | |
| Stats::VectorBase< AverageVector, AvgStor > | |
| Stats::AverageVector | A vector of Average stats |
| Stats::DataWrap< Derived, DistInfoProxy > | |
| Stats::DistBase< Derived, Stor > | Implementation of a distribution stat |
| Stats::DataWrap< Derived, ScalarInfoProxy > | |
| Stats::ScalarBase< Derived, Stor > | Implementation of a scalar stat |
| Stats::ValueBase< Derived > | |
| Stats::DataWrap< Derived, SparseHistInfoProxy > | |
| Stats::SparseHistBase< Derived, Stor > | Implementation of a sparse histogram stat |
| Stats::DataWrap< Derived, Vector2dInfoProxy > | |
| Stats::DataWrapVec< Derived, Vector2dInfoProxy > | |
| Stats::DataWrapVec2d< Derived, Vector2dInfoProxy > | |
| Stats::DataWrap< Derived, VectorDistInfoProxy > | |
| Stats::DataWrapVec< Derived, VectorDistInfoProxy > | |
| Stats::VectorDistBase< Derived, Stor > | |
| Stats::DataWrap< Derived, VectorInfoProxy > | |
| Stats::DataWrapVec< Derived, VectorInfoProxy > | |
| Stats::VectorBase< Derived, Stor > | Implementation of a vector of stats |
| Stats::DataWrap< Distribution, DistInfoProxy > | |
| Stats::DistBase< Distribution, DistStor > | |
| Stats::Distribution | A simple distribution stat |
| Stats::DataWrap< Formula, FormulaInfoProxy > | |
| Stats::DataWrapVec< Formula, FormulaInfoProxy > | |
| Stats::Formula | A formula for statistics that is calculated when printed |
| Stats::DataWrap< Histogram, DistInfoProxy > | |
| Stats::DistBase< Histogram, HistStor > | |
| Stats::Histogram | A simple histogram stat |
| Stats::DataWrap< Scalar, ScalarInfoProxy > | |
| Stats::ScalarBase< Scalar, StatStor > | |
| Stats::Scalar | This is a simple scalar statistic, like a counter |
| Stats::DataWrap< SparseHistogram, SparseHistInfoProxy > | |
| Stats::SparseHistBase< SparseHistogram, SparseHistStor > | |
| Stats::SparseHistogram | |
| Stats::DataWrap< StandardDeviation, DistInfoProxy > | |
| Stats::DistBase< StandardDeviation, SampleStor > | |
| Stats::StandardDeviation | Calculates the mean and variance of all the samples |
| Stats::DataWrap< Value, ScalarInfoProxy > | |
| Stats::ValueBase< Value > | |
| Stats::Value | |
| Stats::DataWrap< Vector, VectorInfoProxy > | |
| Stats::DataWrapVec< Vector, VectorInfoProxy > | |
| Stats::VectorBase< Vector, StatStor > | |
| Stats::Vector | A vector of scalar stats |
| Stats::DataWrap< Vector2d, Vector2dInfoProxy > | |
| Stats::DataWrapVec< Vector2d, Vector2dInfoProxy > | |
| Stats::DataWrapVec2d< Vector2d, Vector2dInfoProxy > | |
| Stats::Vector2dBase< Vector2d, StatStor > | |
| Stats::Vector2d | A 2-Dimensional vecto of scalar stats |
| Stats::DataWrap< VectorAverageDeviation, VectorDistInfoProxy > | |
| Stats::DataWrapVec< VectorAverageDeviation, VectorDistInfoProxy > | |
| Stats::VectorDistBase< VectorAverageDeviation, AvgSampleStor > | |
| Stats::VectorAverageDeviation | This is a vector of AverageDeviation stats |
| Stats::DataWrap< VectorDistribution, VectorDistInfoProxy > | |
| Stats::DataWrapVec< VectorDistribution, VectorDistInfoProxy > | |
| Stats::VectorDistBase< VectorDistribution, DistStor > | |
| Stats::VectorDistribution | A vector of distributions |
| Stats::DataWrap< VectorStandardDeviation, VectorDistInfoProxy > | |
| Stats::DataWrapVec< VectorStandardDeviation, VectorDistInfoProxy > | |
| Stats::VectorDistBase< VectorStandardDeviation, SampleStor > | |
| Stats::VectorStandardDeviation | This is a vector of StandardDeviation stats |
| Stats::DataWrap< Derived, InfoProxyType > | |
| Stats::DataWrapVec< Derived, InfoProxyType > | |
| Stats::DataWrapVec2d< Derived, InfoProxyType > | |
| Stats::Vector2dBase< Derived, Stor > | |
| Bitmap::InfoHeaderV1 | |
| IniFile | This class represents the contents of a ".ini" file |
| PseudoInst::InitParamKey | Unique keys to retrieve various params by the initParam pseudo inst |
| Minor::Latch< Data >::Input | Encapsulate wires on either input or output of the latch |
| TraceGen::InputStream | The InputStream encapsulates a trace file and the internal buffers and populates TraceElements based on the input |
| TraceCPU::FixedRetryGen::InputStream | The InputStream encapsulates a trace file and the internal buffers and populates TraceElements based on the input |
| TraceCPU::ElasticDataGen::InputStream | The InputStream encapsulates a trace file and the internal buffers and populates GraphNodes based on the input |
| X86ISA::Decoder::InstBytes | |
| ElasticTrace::InstExecInfo | |
| Minor::InstId | Id for lines and instructions |
| Trace::InstRecord | |
| Trace::ExeTracerRecord | |
| Trace::NativeTraceRecord | |
| Trace::InstPBTraceRecord | This in an instruction tracer that records the flow of instructions through multiple cpus and systems to a protobuf file specified by proto/inst.proto for further analysis |
| Trace::IntelTraceRecord | |
| X86ISA::InstRegIndex | Class for register indices passed to instruction constructors |
| InstructionQueue< Impl > | A standard instruction queue class |
| Iob::IntBusy | |
| Iob::IntCtl | |
| X86ISA::IntDevice | |
| X86ISA::I82094AA | |
| X86ISA::I8259 | |
| X86ISA::Interrupts | |
| X86ISA::SMBios::SMBiosTable::SMBiosHeader::IntermediateHeader | |
| ArchTimer::Interrupt | |
| Iob::IntMan | |
| ArmV8KvmCPU::IntRegInfo | Mapping between integer registers in gem5 and KVM |
| ip6_hdr | |
| Net::Ip6Hdr | |
| Net::ip6_opt_dstopts | |
| Net::ip6_opt_fragment | |
| Net::ip6_opt_hdr | |
| Net::Ip6Opt | |
| Net::ip6_opt_routing_type2 | |
| Net::Ip6Ptr | |
| ip_hdr | |
| Net::IpHdr | |
| ip_opt | |
| Net::IpOpt | |
| Net::IpAddress | |
| Net::IpNetmask | |
| Net::IpWithPort | |
| Net::IpPtr | |
| IndirectPredictor::IPredEntry | |
| IssueStruct< Impl > | |
| VncInput::KeyEventMessage | |
| Kvm | KVM parent interface |
| ArmKvmCPU::KvmCoreMiscRegInfo | |
| KvmDevice | KVM device wrapper |
| KvmFPReg | |
| ArmKvmCPU::KvmIntRegInfo | |
| Label | |
| LabelMap | |
| Packet::PrintReqState::LabelStackEntry | An entry in the label stack |
| Minor::Latch< Data > | Wraps a MinorBuffer with Input/Output interfaces to ensure that units within the model can only see the right end of buffers between them |
| Minor::Latch< Minor::BranchData > | |
| Minor::Latch< Minor::ForwardInstData > | |
| Minor::Latch< Minor::ForwardLineData > | |
| LdsChunk | This represents a slice of the overall LDS, intended to be associated with an individual workgroup |
| LinearEquation | This class describes a linear equation with constant coefficients |
| LinearSystem | |
| EtherLink::Link | |
| LinkEntry | |
| LinkOrder | |
| std::list< T > | STL list class |
| std::list< AddrRange > | |
| std::list< ArmISA::TableWalker::WalkerState * > | |
| std::list< BasicSignal > | |
| std::list< CacheBlk::Lock > | |
| std::list< Callback * > | |
| std::list< char * > | |
| std::list< ComputeUnit::waveIdentifier > | |
| std::list< CxxConfigManager::Renaming > | |
| std::list< DefaultRename::RenameHistory > | |
| std::list< DeferredPacket > | |
| std::list< DynInstPtr > | |
| std::list< EtherInt * > | |
| std::list< Event * > | |
| std::list< InstructionQueue::ListOrderEntry > | |
| std::list< InstSeqNum > | |
| std::list< int > | |
| std::list< LabelStackEntry > | |
| std::list< ListOrderEntry > | |
| std::list< LockedAddr > | |
| std::list< PacketFifoEntry > | |
| std::list< QueuedPrefetcher::DeferredPacket > | |
| std::list< SimObject * > | |
| std::list< SimpleMemory::DeferredPacket > | |
| std::list< SparcISA::TlbEntry * > | |
| std::list< StorageElement * > | |
| std::list< Target > | |
| MSHR::TargetList | |
| WriteQueueEntry::TargetList | |
| std::list< ThreadID > | |
| std::list< TlbEntry * > | |
| std::list< TraceCPU::ElasticDataGen::ReadyNode > | |
| std::list< Transaction > | |
| std::list< uint8_t > | |
| std::list< unsigned > | |
| std::list< WriteCluster > | |
| std::list< X86ISA::Walker::WalkerState * > | |
| ListenSocket | |
| InstructionQueue< Impl >::ListOrderEntry | Entry for the list age ordering by op class |
| LocalMemPipeline | |
| CacheBlk::Lock | Represents that the indicated thread context has a "lock" on the block, in the LL/SC sense |
| LockedAddr | Locked address class that represents a physical address and a context id |
| Logger | |
| ExitLogger | |
| Trace::Logger | Debug logging base class |
| Trace::OstreamLogger | Logging wrapper for ostreams with the format: <when>: <name>: <message-body> |
| LTAGE::LoopEntry | |
| LSQ< Impl > | |
| LSQUnit< Impl > | Class that implements the actual LQ and SQ for each specific thread |
| ltseqnum | |
| UFSHostDevice::LUNInfo | Logic unit information structure |
| m5_twin32_t | |
| m5_twin64_t | |
| MachineID | |
| HsailISA::MachInst | |
| PCEventQueue::MapCompare | |
| MathExpr | |
| MemCmd | |
| MemDepUnit< MemDepPred, Impl >::MemDepEntry | Memory dependence entries that track memory operations, marking when the instruction is ready to execute and what instructions depend upon it |
| MemDepUnit< MemDepPred, Impl > | Memory dependency unit class |
| HsailISA::MemInst | |
| HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst > | |
| HsailISA::LdaInst< DestDataType, AddrOperandType > | |
| HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType > | |
| HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType > | |
| KvmVM::MemorySlot | Structures tracking memory slots |
| KvmVM::MemSlot | |
| MemState | This class holds the memory state for the Process class and all of its derived, architecture-specific children |
| Message | |
| RubyRequest | |
| MicrocodeRom | |
| X86ISAInst::MicrocodeRom | |
| Minor::MinorStats | Currently unused stats class |
| MipsAccess | |
| ArmV8KvmCPU::MiscRegInfo | Mapping between misc registers in gem5 and registers in KVM |
| ArmISA::ISA::MiscRegInitializerEntry | |
| ArmISA::ISA::MiscRegLUTEntry | Register translation entry used in lookUpMiscReg |
| MiscRegSwitch | |
| ArmISA::ISA | Some registers alias with others, and therefore need to be translated |
| CommMonitor::MonitorStats | Stats declarations, all in a struct for convenience |
| MSICAP | Defines the MSI Capability register and its associated bitfields for the a PCI/PCIe device |
| MSIX | Defines the MSI-X Capability register and its associated bitfields for a PCIe device |
| MSIXCAP | |
| MSIXPbaEntry | |
| MSIXTable | |
| Named | |
| MemChecker::ByteTracker | The ByteTracker keeps track of transactions for the same byte – all outstanding reads, the completed reads (and what they observed) and write clusters (see WriteCluster) |
| Minor::Decode | |
| Minor::Execute | Execute stage |
| Minor::Fetch1 | A stage responsible for fetching "lines" from memory and passing them to Fetch2 |
| Minor::Fetch2 | This stage receives lines of data from Fetch1, separates them into instructions and passes them to Decode |
| Minor::LSQ | |
| Minor::LSQ::StoreBuffer | Store buffer |
| Minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits > | TimeBuffer with MinorTrace and Named interfaces |
| Minor::Queue< ElemType, ReportTraits, BubbleTraits > | Wrapper for a queue type to act as a pipeline stage input queue |
| Minor::Scoreboard | A scoreboard of register dependencies including, for each register: The number of in-flight instructions which will generate a result for this register |
| Minor::MinorBuffer< Data > | |
| Minor::MinorBuffer< ElemType, ReportTraits > | |
| Minor::SelfStallingPipeline< ElemType, ReportTraits, BubbleTraits > | A pipeline simulating class that will stall (not advance when advance() is called) if a non-bubble value lies at the far end of the pipeline |
| Minor::FUPipeline | A functional unit configured from a MinorFU object |
| Minor::MinorBuffer< Minor::BranchData > | |
| Minor::MinorBuffer< Minor::ForwardInstData > | |
| Minor::MinorBuffer< Minor::ForwardLineData > | |
| Minor::Queue< FetchRequestPtr, ReportTraitsPtrAdaptor< FetchRequestPtr >, NoBubbleTraits< FetchRequestPtr > > | |
| Minor::Queue< LSQRequestPtr, ReportTraitsPtrAdaptor< LSQRequestPtr >, NoBubbleTraits< LSQRequestPtr > > | |
| Minor::Queue< Minor::ForwardInstData, ReportTraitsAdaptor< Minor::ForwardInstData >, BubbleTraitsAdaptor< Minor::ForwardInstData > > | |
| Minor::Queue< Minor::ForwardLineData, ReportTraitsAdaptor< Minor::ForwardLineData >, BubbleTraitsAdaptor< Minor::ForwardLineData > > | |
| Minor::Queue< Minor::QueuedInst, Minor::ReportTraitsAdaptor< Minor::QueuedInst > > | |
| NDRange | |
| NetDest | |
| Minor::NoBubbleTraits< ElemType > | .. |
| MathExpr::Node | |
| Stats::Node | Base class for formula statistic node |
| Stats::BinaryNode< Op > | |
| Stats::ConstNode< T > | |
| Stats::ConstVectorNode< T > | |
| Stats::FormulaNode | |
| Stats::ScalarProxyNode< Stat > | |
| Stats::ScalarStatNode | |
| Stats::SumNode< Op > | |
| Stats::UnaryNode< Op > | |
| Stats::VectorStatNode | |
| Trie< Key, Value >::Node | |
| StackDistCalc::Node | Node which takes form of Leaf, INode or Root |
| TCPIface::NodeInfo | Compute node info and storage for the very first connection from each node (used by the switch) |
| ns_desc32 | |
| ns_desc64 | |
| O3CPUImpl | Implementation specific struct that defines several key types to the CPU, the stages within the CPU, the time buffers, and the DynInst |
| ObjectFile | |
| AoutObject | |
| DtbObject | |
| EcoffObject | |
| ElfObject | |
| RawObject | |
| ObjectMatch | |
| OFSchedulingPolicy | |
| OperatingSystem | This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to an operating system syscall interface |
| FreeBSD | This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha FreeBSD syscall interface |
| ArmFreebsd32 | |
| ArmFreebsd64 | |
| Linux | This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Alpha Linux syscall interface |
| AlphaLinux | |
| ArmLinux32 | |
| ArmLinux64 | |
| MipsLinux | |
| PowerLinux | |
| RiscvLinux | |
| SparcLinux | |
| Sparc32Linux | |
| X86Linux32 | |
| X86Linux64 | |
| Solaris | This class encapsulates the types, structures, constants, functions, and syscall-number mappings specific to the Solaris syscall interface |
| SparcSolaris | |
| MathExpr::OpSearch | |
| Stats::OpString< Op > | |
| Stats::OpString< std::divides< Result > > | |
| Stats::OpString< std::minus< Result > > | |
| Stats::OpString< std::modulus< Result > > | |
| Stats::OpString< std::multiplies< Result > > | |
| Stats::OpString< std::negate< Result > > | |
| Stats::OpString< std::plus< Result > > | |
| OPTR | |
| Minor::Latch< Data >::Output | |
| Stats::Output | |
| Stats::Text | |
| OutputDirectory | Interface for creating files in a gem5 output directory |
| OutputStream | |
| OutputFile< StreamType > | |
| OutVcState | |
| P9MsgHeader | |
| P9MsgInfo | |
| PacketFifo | |
| PacketFifoEntry | |
| ProbePoints::PacketInfo | A struct to hold on to the essential fields from a packet, so that the packet and underlying request can be safely passed on, and consequently modified or even deleted |
| FlashDevice::PageMapEntry | Every logical address maps to a physical block and a physical page |
| AlphaISA::PageTableEntry | |
| SparcISA::PageTableEntry | |
| X86ISA::PageTableOps | Page table operations specific to x86 ISA |
| std::pair< X, Y > | STL pair class |
| std::pair< Addr, Addr > | |
| std::pair< flit_stage, Cycles > | |
| std::pair< int, AtomicOpFunctor * > | |
| std::pair< Packet, GPUDynInstPtr > | |
| std::pair< Packet, Wavefront * > | |
| std::pair< TCPIface::NodeInfo, int > | |
| std::pair< Tick, EthPacketPtr > | |
| std::pair< uint32_t, uint32_t > | |
| std::pair< VC_state_type, Cycles > | |
| std::pair< Wavefront *, bool > | |
| std::pair< Wavefront *, DISPATCH_STATUS > | |
| PAL | |
| CxxConfigDirectoryEntry::ParamDesc | |
| pcap_file_header | |
| pcap_pkthdr | |
| Linux::pcb_struct | |
| PCEvent | |
| BaseRemoteGDB::HardBreakpoint | |
| BreakPCEvent | |
| DumpStatsPCEvent | |
| IdleStartEvent | |
| IdleStartEvent | |
| IdleStartEvent | |
| Linux::DmesgDumpEvent | Dump the guest kernel's dmesg buffer to a file in gem5's output directory and print a warning |
| Linux::KernelPanicEvent | Dump the guest kernel's dmesg buffer to a file in gem5's output directory and panic |
| LinuxAlphaSystem::PrintThreadInfo | |
| LinuxMipsSystem::PrintThreadInfo | |
| PanicPCEvent | |
| SkipFuncEvent | |
| FreeBSD::UDelayEvent | A class to skip udelay() and related calls in the kernel |
| FreebsdAlphaSystem::SkipCalibrateClocksEvent | |
| Linux::DebugPrintkEvent | |
| Linux::UDelayEvent | A class to skip udelay() and related calls in the kernel |
| LinuxAlphaSystem::SkipDelayLoopEvent | |
| LinuxMipsSystem::SkipDelayLoopEvent | |
| PCEventQueue | |
| PciBusAddr | |
| PCIConfig | |
| StridePrefetcher::PCTable | |
| pdr | |
| PerfectCacheLineState< ENTRY > | |
| PerfectCacheMemory< ENTRY > | |
| PerfKvmCounter | An instance of a performance counter |
| PerfKvmCounterConfig | PerfEvent counter configuration |
| PersistentTable | |
| PersistentTableEntry | |
| PhysRegFile::PhysFloatReg | |
| PhysRegFile | Simple physical register file class |
| Pixel | Internal gem5 representation of a Pixel |
| PixelConverter | Configurable RGB pixel converter |
| VncInput::PixelEncodingsMessage | |
| VncInput::PixelFormat | |
| VncInput::PixelFormatMessage | |
| PMCAP | Defines the Power Management capability register and all its associated bitfields for a PCIe device |
| VncInput::PointerEventMessage | |
| PollQueue | |
| PoolManager | |
| SimplePoolManager | |
| Port | Ports are used to interface memory objects to each other |
| BaseMasterPort | A BaseMasterPort is a protocol-agnostic master port, responsible only for the structural connection to a slave port |
| MasterPort | A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the three different level of transport functions |
| AddrMapper::MapperMasterPort | |
| AtomicSimpleCPU::AtomicCPUPort | An AtomicCPUPort overrides the default behaviour of the recvAtomicSnoop and ignores the packet instead of panicking |
| AtomicSimpleCPU::AtomicCPUDPort | |
| BaseKvmCPU::KVMCpuPort | KVM memory port |
| Bridge::BridgeMasterPort | Port on the side that forwards requests and receives responses |
| CoherentXBar::CoherentXBarMasterPort | Declaration of the coherent crossbar master port type, one will be instantiated for each of the slave interfaces connecting to the crossbar |
| CoherentXBar::SnoopRespPort | Internal class to bridge between an incoming snoop response from a slave port and forwarding it through an outgoing slave port |
| CommMonitor::MonitorMasterPort | This is the master port of the communication monitor |
| ComputeUnit::DataPort | Data access Port |
| ComputeUnit::DTLBPort | Data TLB port |
| ComputeUnit::ITLBPort | |
| ComputeUnit::LDSPort | Port intended to communicate between the CU and its LDS |
| ComputeUnit::SQCPort | |
| DmaPort | |
| ExternalMaster::Port | Derive from this class to create an external port interface |
| FullO3CPU< Impl >::DcachePort | DcachePort class for the load/store queue |
| FullO3CPU< Impl >::IcachePort | IcachePort class for instruction fetch |
| GarnetSyntheticTraffic::CpuPort | |
| GpuDispatcher::TLBPort | |
| MemCheckerMonitor::MonitorMasterPort | This is the master port of the communication monitor |
| MemTest::CpuPort | |
| MinorCPU::MinorCPUPort | Provide a non-protected base class for Minor's Ports as derived classes are created by Fetch1 and Execute |
| Minor::Fetch1::IcachePort | Exposable fetch port |
| Minor::LSQ::DcachePort | Exposable data port |
| NoncoherentXBar::NoncoherentXBarMasterPort | Declaration of the crossbar master port type, one will be instantiated for each of the slave ports connecting to the crossbar |
| QueuedMasterPort | The QueuedMasterPort combines two queues, a request queue and a snoop response queue, that both share the same port |
| AbstractController::MemoryPort | Port that forwards requests and receives responses from the memory controller |
| BaseCache::CacheMasterPort | A cache master port is used for the memory-side port of the cache, and in addition to the basic timing port that only sends response packets through a transmit list, it also offers the ability to schedule and send request packets (requests & writebacks) |
| MessageMasterPort | |
| X86ISA::IntDevice::IntMasterPort | |
| RubyPort::MemMasterPort | |
| RubyPort::PioMasterPort | |
| RubyDirectedTester::CpuPort | |
| RubyTester::CpuPort | |
| SerialLink::SerialLinkMasterPort | Port on the side that forwards requests and receives responses |
| System::SystemPort | Private class for the system port which is only used as a master for debug access and for non-structural entities that do not have a port of their own |
| TimingSimpleCPU::TimingCPUPort | A TimingCPUPort overrides the default behaviour of the recvTiming and recvRetry and implements events for the scheduling of handling of incoming packets in the following cycle |
| TimingSimpleCPU::DcachePort | |
| TimingSimpleCPU::IcachePort | |
| TLBCoalescer::MemSidePort | |
| TraceCPU::DcachePort | DcachePort class that interfaces with L1 Data Cache |
| TraceCPU::IcachePort | IcachePort class that interfaces with L1 Instruction Cache |
| TrafficGen::TrafficGenPort | Master port specialisation for the traffic generator |
| X86ISA::GpuTLB::MemSidePort | MemSidePort is the TLB Port closer to the memory side If this is a last level TLB then this port will not be connected |
| X86ISA::Walker::WalkerPort | |
| BaseSlavePort | A BaseSlavePort is a protocol-agnostic slave port, responsible only for the structural connection to a master port |
| SlavePort | A SlavePort is a specialisation of a port |
| AddrMapper::MapperSlavePort | |
| Bridge::BridgeSlavePort | The port on the side that receives requests and sends responses |
| CommMonitor::MonitorSlavePort | This is the slave port of the communication monitor |
| DRAMSim2::MemoryPort | The memory port has to deal with its own flow control to avoid having unbounded storage that is implicitly created in the port itself |
| ExternalSlave::Port | Derive from this class to create an external port interface |
| StubSlavePort | Implement a `stub' port which just responds to requests by printing a message |
| LdsState::CuSidePort | CuSidePort is the LDS Port closer to the CU side |
| MemCheckerMonitor::MonitorSlavePort | This is the slave port of the communication monitor |
| QueuedSlavePort | A queued port is a port that has an infinite queue for outgoing packets and thus decouples the module that wants to send request/responses from the flow control (retry mechanism) of the port |
| BaseCache::CacheSlavePort | A cache slave port is used for the CPU-side port of the cache, and it is basically a simple timing port that uses a transmit list for responses to the CPU (or connected master) |
| CoherentXBar::CoherentXBarSlavePort | Declaration of the coherent crossbar slave port type, one will be instantiated for each of the master ports connecting to the crossbar |
| DRAMCtrl::MemoryPort | |
| NoncoherentXBar::NoncoherentXBarSlavePort | Declaration of the non-coherent crossbar slave port type, one will be instantiated for each of the master ports connecting to the crossbar |
| RubyPort::MemSlavePort | |
| RubyPort::PioSlavePort | |
| SimpleTimingPort | The simple timing port uses a queued port to implement recvFunctional and recvTimingReq through recvAtomic |
| MessageSlavePort | |
| X86ISA::IntDevice::IntSlavePort | |
| PioPort | Programmed i/o port that all devices that are sensitive to an address range use |
| SerialLink::SerialLinkSlavePort | The port on the side that receives requests and sends responses |
| SimpleMemory::MemoryPort | |
| TLBCoalescer::CpuSidePort | |
| X86ISA::GpuTLB::CpuSidePort | |
| BaseXBar::PortCache | |
| CxxConfigDirectoryEntry::PortDesc | Similar to ParamDesc to describe ports |
| PortProxy | This object is a proxy for a structural port, to be used for debug accesses |
| FSTranslatingPortProxy | A TranslatingPortProxy in FS mode translates a virtual address to a physical address and then calls the read/write functions of the port |
| SETranslatingPortProxy | |
| InstructionQueue< Impl >::pqCompare | Struct for comparing entries to be added to the priority queue |
| PrdEntry | |
| PrdTableEntry | |
| BPredUnit::PredictorHistory | |
| PrefetchEntry | |
| cp::Print | |
| Printable | Abstract base class for objects which support being printed to a stream for debugging |
| CacheBlkPrintWrapper | Simple class to provide virtual print() method on cache blocks without allocating a vtable pointer for every single cache block |
| MSHR | Miss Status and handling Register |
| Packet | A Packet is used to encapsulate a transfer between two objects in the memory system (e.g., the L1 and L2 cache) |
| WriteQueueEntry | Write queue entry |
| ProbeListener | ProbeListener base class; here to simplify things like containers containing multiple types of ProbeListener |
| ProbeListenerArgBase< Arg > | ProbeListenerArgBase is used to define the base interface to a ProbeListenerArg (i.e the notify method on specific type) |
| ProbeListenerArg< T, Arg > | ProbeListenerArg generates a listener for the class of Arg and the class type T which is the class containing the function that notify will call |
| ProbeListenerArgBase< double > | |
| PowerModel::ThermalProbeListener | Listener class to catch thermal events |
| ProbeListenerArgBase< ProbePoints::PacketInfo > | |
| BaseMemProbe::PacketListener | |
| ProbeListenerArgBase< uint64_t > | |
| ArmISA::PMU::ProbeListener | |
| ProbeManager | ProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners with probe points |
| ProbePoint | ProbeListener base class; again used to simplify use of ProbePoints in containers and used as to define interface for adding removing listeners to the ProbePoint |
| ProbePointArg< T > | ProbePointArg generates a point for the class of Arg |
| ProbePointArg< double > | |
| ProbePointArg< DynInstPtr > | |
| ProbePointArg< Packet > | |
| ProbePointArg< Request > | |
| ProbePointArg< std::pair > | |
| ProbePointArg< std::pair< DynInstPtr, Packet > > | |
| ProbePointArg< std::pair< SimpleThread *, const RefCountingPtr > > | |
| RiscvISA::ProcessInfo | |
| PowerISA::ProcessInfo | |
| ArmISA::ProcessInfo | |
| AlphaISA::ProcessInfo | |
| X86ISA::ProcessInfo | |
| MipsISA::ProcessInfo | |
| ProfileNode | |
| Profiler | |
| ProtoStream | A ProtoStream provides the shared functionality of the input and output streams |
| ProtoInputStream | A ProtoInputStream wraps a coded stream, potentially with decompression, based on looking at the file name |
| ProtoOutputStream | A ProtoOutputStream wraps a coded stream, potentially with compression, based on looking at the file name |
| X86ISA::PS2Device | |
| X86ISA::PS2Keyboard | |
| X86ISA::PS2Mouse | |
| PowerISA::PTE | |
| RiscvISA::PTE | |
| MipsISA::PTE | |
| ArmISA::PTE | |
| PXCAP | Defines the PCI Express capability register and its associated bitfields for a PCIe device |
| Minor::QueuedInst | Container class to box instructions in the FUs to make those queues have correct bubble behaviour when stepped |
| TraceCPU::ElasticDataGen::ReadyNode | Struct to store a ready-to-execute node and its execution tick |
| ReconvergenceStackEntry | A reconvergence stack entry conveys the necessary state to implement control flow divergence |
| RefCounted | Derive from RefCounted if you want to enable reference counting of this class |
| BaseDynInst< Impl > | |
| Minor::MinorDynInst | Dynamic instruction for Minor |
| StaticInst | Base, ISA-independent static instruction class |
| ArmISA::ArmStaticInst | |
| ArmISA::BranchEret64 | |
| ArmISA::BranchImm64 | |
| ArmISA::BranchImmCond64 | |
| ArmISA::BranchImmImmReg64 | |
| ArmISA::BranchImmReg64 | |
| ArmISA::BranchReg64 | |
| ArmISA::BranchRet64 | |
| ArmISA::DataX1Reg2ImmOp | |
| ArmISA::DataX1RegImmOp | |
| ArmISA::DataX1RegOp | |
| ArmISA::DataX2RegImmOp | |
| ArmISA::DataX2RegOp | |
| ArmISA::DataX3RegOp | |
| ArmISA::DataXCondCompImmOp | |
| ArmISA::DataXCondCompRegOp | |
| ArmISA::DataXCondSelOp | |
| ArmISA::DataXERegOp | |
| ArmISA::DataXImmOnlyOp | |
| ArmISA::DataXImmOp | |
| ArmISA::DataXSRegOp | |
| ArmISA::MicroOpX | |
| ArmISA::MicroIntImmXOp | |
| ArmISA::MightBeMicro64 | |
| ArmISA::Memory64 | |
| ArmISA::MemoryEx64 | |
| ArmISA::MemoryImm64 | |
| ArmISA::MemoryDImm64 | |
| ArmISA::MemoryDImmEx64 | |
| ArmISA::MemoryPostIndex64 | |
| ArmISA::MemoryPreIndex64 | |
| ArmISA::MemoryLiteral64 | |
| ArmISA::MemoryRaw64 | |
| ArmISA::MemoryReg64 | |
| ArmISA::PredOp | Base class for predicated integer operations |
| ArmISA::BranchImm | |
| ArmISA::BranchImmCond | |
| ArmISA::BranchImmReg | |
| ArmISA::BranchReg | |
| ArmISA::BranchRegCond | |
| ArmISA::BranchRegReg | |
| ArmISA::DataImmOp | |
| ArmISA::DataRegOp | |
| ArmISA::DataRegRegOp | |
| ArmISA::FpOp | |
| ArmISA::FpCondCompRegOp | |
| ArmISA::FpCondSelOp | |
| ArmISA::FpRegImmOp | |
| ArmISA::FpRegRegImmOp | |
| ArmISA::FpRegRegOp | |
| ArmISA::FpRegRegRegCondOp | |
| ArmISA::FpRegRegRegImmOp | |
| ArmISA::FpRegRegRegOp | |
| ArmISA::FpRegRegRegRegOp | |
| ArmISA::MicroOp | Base class for Memory microops |
| ArmISA::MicroIntImmOp | Microops of the form IntRegA = IntRegB op Imm |
| ArmISA::MicroMemOp | Memory microops which use IntReg + Imm addressing |
| ArmISA::MicroIntMov | Microops of the form IntRegA = IntRegB |
| ArmISA::MicroIntOp | Microops of the form IntRegA = IntRegB op IntRegC |
| ArmISA::MicroIntRegOp | Microops of the form IntRegA = IntRegB op shifted IntRegC |
| ArmISA::MicroIntRegXOp | |
| ArmISA::MicroMemPairOp | |
| ArmISA::MicroNeonMemOp | Microops for Neon loads/stores |
| ArmISA::MicroNeonMixLaneOp64 | |
| ArmISA::MicroNeonMixOp | Microops for Neon load/store (de)interleaving |
| ArmISA::MicroNeonMixLaneOp | |
| ArmISA::MicroNeonMixOp64 | Microops for AArch64 NEON load/store (de)interleaving |
| ArmISA::MicroSetPCCPSR | Microops of the form PC = IntRegA CPSR = IntRegB |
| ArmISA::MightBeMicro | |
| ArmISA::Memory | |
| ArmISA::MemoryImm | |
| ArmISA::MemoryDImm | |
| ArmISA::MemoryExDImm | |
| ArmISA::MemoryExImm | |
| ArmISA::MemoryReg | |
| ArmISA::MemoryDReg | |
| ArmISA::RfeOp | |
| ArmISA::SrsOp | |
| ArmISA::Mult3 | Base class for multipy instructions using three registers |
| ArmISA::Mult4 | Base class for multipy instructions using four registers |
| ArmISA::PredImmOp | Base class for predicated immediate operations |
| ArmISA::PredIntOp | Base class for predicated integer operations |
| ArmISA::PredMacroOp | Base class for predicated macro-operations |
| ArmISA::BigFpMemImmOp | |
| ArmISA::BigFpMemLitOp | |
| ArmISA::BigFpMemPostOp | |
| ArmISA::BigFpMemPreOp | |
| ArmISA::BigFpMemRegOp | |
| ArmISA::MacroMemOp | Base class for microcoded integer memory instructions |
| ArmISA::MacroVFPMemOp | Base class for microcoded floating point memory instructions |
| ArmISA::PairMemOp | Base class for pair load/store instructions |
| ArmISA::VfpMacroOp | |
| ArmISA::VldMultOp | Base classes for microcoded integer memory instructions |
| ArmISA::VldMultOp64 | Base classes for microcoded AArch64 NEON memory instructions |
| ArmISA::VldSingleOp | |
| ArmISA::VldSingleOp64 | |
| ArmISA::VstMultOp | Base class for microcoded integer memory instructions |
| ArmISA::VstMultOp64 | |
| ArmISA::VstSingleOp | |
| ArmISA::VstSingleOp64 | |
| ArmISA::PredMicroop | Base class for predicated micro-operations |
| ArmISA::Swap | |
| ImmOp | |
| McrrOp | |
| MiscRegRegImmOp | |
| MrrcOp | |
| MrsOp | |
| MsrBase | |
| MsrImmOp | |
| MsrRegOp | |
| RegImmImmOp | |
| RegImmOp | |
| RegImmRegOp | |
| RegImmRegShiftOp | |
| RegMiscRegImmOp | |
| RegRegImmImmOp | |
| RegRegImmOp | |
| RegRegOp | |
| RegRegRegImmOp | |
| RegRegRegOp | |
| RegRegRegRegOp | |
| UnknownOp | |
| ArmISA::SysDC64 | |
| DecoderFaultInst | |
| FailUnimplemented | Static instruction class for unimplemented instructions that cause simulator termination |
| McrMrcMiscInst | Certain mrc/mcr instructions act as nops or flush the pipe based on what register the instruction is trying to access |
| RegRegImmImmOp64 | |
| RegRegRegImmOp64 | |
| UnknownOp64 | |
| WarnUnimplemented | Base class for unimplemented instructions that cause a warning to be printed (but do not terminate simulation) |
| PowerISA::PowerStaticInst | |
| PowerISA::CondLogicOp | Class for condition register logical operations |
| PowerISA::CondMoveOp | Class for condition register move operations |
| PowerISA::FloatOp | Base class for floating point operations |
| PowerISA::IntOp | We provide a base class for integer operations and then inherit for several other classes |
| PowerISA::IntImmOp | Class for integer immediate (signed and unsigned) operations |
| PowerISA::IntShiftOp | Class for integer operations with a shift |
| PowerISA::IntRotateOp | Class for integer rotate operations |
| PowerISA::MemOp | Base class for memory operations |
| PowerISA::MemDispOp | Class for memory operations with displacement |
| PowerISA::MiscOp | Class for misc operations |
| PowerISA::PCDependentDisassembly | Base class for instructions whose disassembly is not purely a function of the machine instruction (i.e., it depends on the PC) |
| PowerISA::BranchCond | Base class for conditional branches |
| PowerISA::BranchNonPCRelCond | Base class for conditional, non PC-relative branches |
| PowerISA::BranchPCRelCond | Base class for conditional, PC-relative branches |
| PowerISA::BranchRegCond | Base class for conditional, register-based branches |
| PowerISA::BranchNonPCRel | Base class for unconditional, non PC-relative branches |
| PowerISA::BranchPCRel | Base class for unconditional, PC-relative branches |
| X86ISA::X86StaticInst | Base class for all X86 static instructions |
| X86ISA::MacroopBase | |
| X86ISA::X86MicroopBase | |
| X86ISA::FpOp | Base classes for FpOps which provides a generateDisassembly method |
| X86ISA::MediaOpBase | |
| X86ISA::MediaOpImm | |
| X86ISA::MediaOpReg | |
| X86ISA::MemOp | Base class for memory ops |
| X86ISA::LdStOp | Base class for load and store ops using one register |
| X86ISA::LdStSplitOp | Base class for load and store ops using two registers, we will call them split ops for this reason |
| X86ISA::RegOpBase | Base classes for RegOps which provides a generateDisassembly method |
| X86ISA::RegOp | |
| X86ISA::RegOpImm | |
| RefCountingPtr< T > | If you want a reference counting pointer to a mutable object, create it like this: |
| RefCountingPtr< MinorDynInst > | |
| RefCountingPtr< StaticInst > | |
| iGbReg::Regs::Reg< T > | |
| CopyEngineReg::Reg< T > | |
| CopyEngineReg::Reg< uint16_t > | |
| CopyEngineReg::ChanRegs::CHANCTRL | |
| CopyEngineReg::Reg< uint32_t > | |
| CopyEngineReg::ChanRegs::CHANERR | |
| iGbReg::Regs::Reg< uint32_t > | |
| iGbReg::Regs::CTRL | |
| iGbReg::Regs::CTRL_EXT | |
| iGbReg::Regs::EECD | |
| iGbReg::Regs::EERD | |
| iGbReg::Regs::FCRTH | |
| iGbReg::Regs::FCRTL | |
| iGbReg::Regs::FCTTV | |
| iGbReg::Regs::FWSM | |
| iGbReg::Regs::ICR | |
| iGbReg::Regs::ITR | |
| iGbReg::Regs::MANC | |
| iGbReg::Regs::MDIC | |
| iGbReg::Regs::PBA | |
| iGbReg::Regs::RADV | |
| iGbReg::Regs::RCTL | |
| iGbReg::Regs::RDH | |
| iGbReg::Regs::RDLEN | |
| iGbReg::Regs::RDT | |
| iGbReg::Regs::RDTR | |
| iGbReg::Regs::RFCTL | |
| iGbReg::Regs::RSRPD | |
| iGbReg::Regs::RXCSUM | |
| iGbReg::Regs::RXDCTL | |
| iGbReg::Regs::SRRCTL | |
| iGbReg::Regs::STATUS | |
| iGbReg::Regs::SWSM | |
| iGbReg::Regs::TADV | |
| iGbReg::Regs::TCTL | |
| iGbReg::Regs::TDH | |
| iGbReg::Regs::TDLEN | |
| iGbReg::Regs::TDT | |
| iGbReg::Regs::TIDV | |
| iGbReg::Regs::TXDCA_CTL | |
| iGbReg::Regs::TXDCTL | |
| CopyEngineReg::Reg< uint64_t > | |
| CopyEngineReg::ChanRegs::CHANSTS | |
| iGbReg::Regs::Reg< uint64_t > | |
| iGbReg::Regs::RDBA | |
| iGbReg::Regs::TDBA | |
| CopyEngineReg::Reg< uint8_t > | |
| CopyEngineReg::ChanRegs::CHANCMD | |
| CopyEngineReg::Regs::INTRCTRL | |
| BitfieldBackend::RegularBitfieldTypes< Type > | |
| BitfieldBackend::BitfieldTypes< Type > | |
| TimeBufStruct< Impl >::renameComm | |
| DefaultRename< Impl >::RenameHistory | Holds the information for each destination register rename |
| CxxConfigManager::Renaming | Name substitution when instantiating any object whose name starts with fromPrefix |
| Minor::ReportIF | Interface class for data with reporting/tracing facilities |
| Minor::ReportTraitsAdaptor< ElemType > | ...ReportTraits are trait classes with the same functionality as ReportIF, but with elements explicitly passed into the report.. |
| Minor::ReportTraitsPtrAdaptor< PtrType > | A similar adaptor but for elements held by pointer ElemType should implement ReportIF |
| Request | |
| RequestDesc | |
| UFSHostDevice::UTPTransferReqDesc::RequestDescHeader | Struct RequestDescHeader dword0: Descriptor Header DW0 dword1: Descriptor Header DW1 dword2: Descriptor Header DW2 dword3: Descriptor Header DW3 |
| Minor::Reservable | Base class for space reservation requestable objects |
| Minor::InputBuffer< Minor::ForwardInstData > | |
| Minor::InputBuffer< Minor::ForwardLineData > | |
| Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits > | Like a Queue but with a restricted interface and a setTail function which, when the queue is empty, just takes a reference to the pushed item as the single element |
| Minor::Queue< ElemType, ReportTraits, BubbleTraits > | Wrapper for a queue type to act as a pipeline stage input queue |
| Minor::Queue< FetchRequestPtr, ReportTraitsPtrAdaptor< FetchRequestPtr >, NoBubbleTraits< FetchRequestPtr > > | |
| Minor::Queue< LSQRequestPtr, ReportTraitsPtrAdaptor< LSQRequestPtr >, NoBubbleTraits< LSQRequestPtr > > | |
| Minor::Queue< Minor::ForwardInstData, ReportTraitsAdaptor< Minor::ForwardInstData >, BubbleTraitsAdaptor< Minor::ForwardInstData > > | |
| Minor::Queue< Minor::ForwardLineData, ReportTraitsAdaptor< Minor::ForwardLineData >, BubbleTraitsAdaptor< Minor::ForwardLineData > > | |
| Minor::Queue< Minor::QueuedInst, Minor::ReportTraitsAdaptor< Minor::QueuedInst > > | |
| BaseDynInst< Impl >::Result | |
| CheckerCPU::Result | |
| ReturnAddrStack | Return address stack class, implements a simple RAS |
| ArmLinux64::rlimit | Limit struct for getrlimit/setrlimit |
| Linux::rlimit | Limit struct for getrlimit/setrlimit |
| ArmFreebsd32::rlimit | Limit struct for getrlimit/setrlimit |
| ArmFreebsd64::rlimit | Limit struct for getrlimit/setrlimit |
| OperatingSystem::rlimit | Limit struct for getrlimit/setrlimit |
| ArmLinux32::rlimit | Limit struct for getrlimit/setrlimit |
| RNDXR | |
| ROB< Impl > | ROB class |
| RouteInfo | |
| RoutingUnit | |
| RRSchedulingPolicy | |
| ArmLinux32::rusage | For getrusage() |
| ArmLinux64::rusage | For getrusage() |
| ArmFreebsd64::rusage | For getrusage() |
| OperatingSystem::rusage | For getrusage() |
| Linux::rusage | |
| ArmFreebsd32::rusage | For getrusage() |
| iGbReg::RxDesc | |
| Stats::SampleStor | Templatized storage and interface for a distribution that calculates mean and variance |
| SatCounter | Private counter class for the internal saturating counters |
| Stats::ScalarPrint | |
| Stats::ScalarProxy< Stat > | A proxy class to access the stat at a given index in a VectorBase stat |
| Scheduler | |
| ScheduleStage | |
| SchedulingPolicy< Impl > | |
| SchedulingPolicy< OFSchedulingPolicy > | |
| SchedulingPolicy< RRSchedulingPolicy > | |
| Serializable::ScopedCheckpointSection | Scoped checkpoint section helper class |
| EventQueue::ScopedMigration | Temporarily migrate execution to a different event queue |
| EventQueue::ScopedRelease | Temporarily release the event queue service lock |
| Scoreboard | Implements a simple scoreboard to track which registers are ready |
| ScoreboardCheckStage | |
| UFSHostDevice::SCSIReply | SCSI reply structure |
| UFSHostDevice::SCSIResumeInfo | After a SCSI command has been identified, the SCSI resume function will handle it |
| IniFile::Section | A section |
| ObjectFile::Section | |
| BrigObject::SectionInfo | |
| CowDiskImage::Sector | |
| Packet::SenderState | A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a MemObject that sees the packet |
| AbstractController::SenderState | |
| AddrMapper::AddrMapperSenderState | |
| CommMonitor::CommMonitorSenderState | Sender state class for the monitor so that we can annotate packets with a transmit time and receive time |
| ComputeUnit::DataPort::SenderState | |
| ComputeUnit::DTLBPort::SenderState | SenderState is information carried along with the packet throughout the TLB hierarchy |
| ComputeUnit::ITLBPort::SenderState | SenderState is information carried along with the packet throughout the TLB hierarchy |
| ComputeUnit::LDSPort::SenderState | SenderState is information carried along with the packet, esp |
| ComputeUnit::SQCPort::SenderState | |
| DmaPort::DmaReqState | |
| GarnetSyntheticTraffic::GarnetSyntheticTrafficSenderState | |
| LSQUnit< Impl >::LSQSenderState | Derived class to hold any sender state the LSQ needs |
| MemCheckerMonitor::MemCheckerMonitorSenderState | |
| Minor::Fetch1::FetchRequest | Memory access queuing |
| Minor::LSQ::LSQRequest | Derived SenderState to carry data access info |
| Minor::LSQ::SingleDataRequest | SingleDataRequest is used for requests that don't fragment |
| Minor::LSQ::SpecialDataRequest | Special request types that don't actually issue memory requests |
| Minor::LSQ::BarrierDataRequest | Request for doing barrier accounting in the store buffer |
| Minor::LSQ::FailedDataRequest | FailedDataRequest represents requests from instructions that failed their predicates but need to ride the requests/transfers queues to maintain trace ordering |
| Minor::LSQ::SplitDataRequest | |
| Packet::PrintReqState | Object used to maintain state of a PrintReq |
| QueueEntry | A queue entry base class, to be used by both the MSHRs and write-queue entries |
| MSHR | Miss Status and handling Register |
| WriteQueueEntry | Write queue entry |
| RubyPort::SenderState | |
| RubyTester::SenderState | |
| TimingSimpleCPU::SplitFragmentSenderState | |
| TimingSimpleCPU::SplitMainSenderState | |
| X86ISA::GpuTLB::TranslationState | TLB TranslationState: this currently is a somewhat bastardization of the usage of SenderState, whereby the receiver of a packet is not usually supposed to need to look at the contents of the senderState, you're really only supposed to look at what you pushed on, pop it off, and send it back |
| X86ISA::Walker::WalkerSenderState | |
| SequencerRequest | |
| Serializable | Basic support for object serialization |
| AlphaBackdoor::Access | |
| AlphaISA::TlbEntry | |
| ArchTimer | Per-CPU architected timer |
| ArmISA::PMU::CounterState | State of a counter within the PMU |
| ArmISA::TlbEntry | |
| BasePixelPump | Timing generator for a pixel-based display |
| CopyEngine::CopyEngineChannel | |
| CopyEngineReg::ChanRegs | |
| CopyEngineReg::Regs | |
| CpuLocalTimer::Timer | |
| IGbE::DescCache< iGbReg::RxDesc > | |
| IGbE::RxDescCache | |
| IGbE::DescCache< iGbReg::TxDesc > | |
| IGbE::TxDescCache | |
| DisplayTimings | |
| DistEtherLink::Link | Model base class for a single uni-directional link |
| DistEtherLink::RxLink | Model for a receive link |
| DistEtherLink::TxLink | Model for a send link |
| DistIface | The interface class to talk to peer gem5 processes |
| DistIface::RecvScheduler | Class to encapsulate information about data packets received |
| DistIface::RecvScheduler::Desc | Received packet descriptor |
| DistIface::Sync | This class implements global sync operations among gem5 peer processes |
| DistIface::SyncNode | |
| DistIface::SyncSwitch | |
| DmaReadFifo | Buffered DMA engine helper class |
| EtherSwitch::Interface | Model for an Ethernet switch port |
| EtherSwitch::Interface::PortFifo | |
| EtherSwitch::Interface::PortFifoEntry | |
| Event | |
| FDEntry | Holds a single file descriptor mapping and that mapping's data for processes running in syscall emulation mode |
| DeviceFDEntry | Holds file descriptors needed to simulate devices opened with pseudo files (commonly with calls to ioctls) |
| HBFDEntry | Extends the base class to include a host-backed file descriptor field that records the integer used to represent the file descriptor on the host and the file's flags |
| FileFDEntry | Holds file descriptors for host-backed files; host-backed files are files which were opened on the physical machine where the simulation is running (probably the thing on/under your desk) |
| PipeFDEntry | Holds the metadata needed to maintain the mappings for file descriptors allocated with the pipe() system calls and its variants |
| FrameBuffer | Internal gem5 representation of a frame buffer |
| GenericISA::PCStateBase | |
| GenericISA::SimplePCState< MachInst > | |
| GenericISA::DelaySlotPCState< MachInst > | |
| GenericISA::DelaySlotUPCState< MachInst > | |
| GenericISA::UPCState< MachInst > | |
| NullISA::PCState | |
| X86ISA::PCState | |
| Globals | Container for serializing global variables (not associated with any serialized object) |
| IGbE::DescCache< T > | |
| iGbReg::Regs | |
| Kernel::Statistics | |
| AlphaISA::Kernel::Statistics | |
| ArmISA::Kernel::Statistics | |
| MipsISA::Kernel::Statistics | |
| PowerISA::Kernel::Statistics | |
| RiscvISA::Kernel::Statistics | |
| SparcISA::Kernel::Statistics | |
| X86ISA::Kernel::Statistics | |
| PageTableBase | Declaration of base class for page table |
| FuncPageTable | Declaration of functional page table |
| NoArchPageTable | Faux page table class indended to stop the usage of an architectural page table, when there is none defined for a particular ISA |
| MultiLevelPageTable< ISAOps > | This class implements an in-memory multi-level page table that can be configured to follow ISA specifications |
| PhysicalMemory | The physical memory encapsulates all memories in the system and provides basic functionality for accessing those memories without going through the memory system and interconnect |
| Pl390::BankedRegs | Registers "banked for each connected processor" per ARM IHI0048B |
| PollEvent | |
| BaseRemoteGDB::InputEvent | |
| GDBListener::InputEvent | |
| TapEvent | |
| TapListener::Event | |
| Terminal::DataEvent | |
| Terminal::ListenEvent | |
| VirtIO9PDiod::DiodDataEvent | |
| VirtIO9PSocket::SocketDataEvent | |
| VncServer::DataEvent | DataEvent to read data from vnc |
| VncServer::ListenEvent | ListenEvent to accept a vnc client connection |
| Random | |
| SimObject | Abstract superclass for simulation objects |
| Sp804::Timer | |
| SystemCounter | Global system counter |
| ThreadState | Struct for holding general thread state that is needed across CPU models |
| O3ThreadState< class > | Class that has various thread state, such as the status, the current instruction being processed, whether or not the thread has a trap pending or is being externally updated, the ThreadContext pointer, etc |
| O3ThreadState< Impl > | |
| SimpleThread | The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interface |
| Ticked | Ticked attaches gem5's event queue/scheduler to evaluate calls and provides a start/stop interface to ticking |
| Minor::Pipeline | The constructed pipeline |
| TickedObject | TickedObject attaches Ticked to ClockedObject and can be used as a base class where ticked operation |
| VirtQueue | Base wrapper around a virtqueue |
| VirtIO9PBase::FSQueue | Virtqueue for 9p requests |
| VirtIOBlock::RequestQueue | Virtqueue for disk requests |
| VirtIOConsole::TermRecvQueue | Virtqueue for data going from the host to the guest |
| VirtIOConsole::TermTransQueue | Virtqueue for data going from the guest to the host |
| VncServer::ServerCutText | |
| VncServer::ServerInitMsg | |
| Set | |
| BitfieldBackend::SignedBitfieldTypes< Type > | |
| BitfieldBackend::BitfieldTypes< Type > | |
| SimObjectResolver | Base class to wrap object resolving functionality |
| CxxConfigManager::SimObjectResolver | Class for resolving SimObject names to SimObjects usable by the checkpoint restore mechanism |
| PybindSimObjectResolver | Resolve a SimObject name using the Pybind configuration |
| SimpleCPUPolicy< Impl > | Struct that defines the key classes to be used by the CPU |
| SimpleFreeList | Free list for a single class of registers (e.g., integer or floating point) |
| SimpleRenameMap | Register rename map for a single class of registers (e.g., integer or floating point) |
| X86ISA::SMBios::SMBiosTable::SMBiosHeader | |
| SNHash | |
| SnoopFilter::SnoopItem | Per cache line item tracking a bitmask of SlavePorts who have an outstanding request to this line (requested) or already share a cache line with this address (holder) |
| SparcISA::SparcLinuxProcess | |
| SparcISA::Sparc32LinuxProcess | A process with emulated SPARC/Linux syscalls |
| SparcISA::Sparc64LinuxProcess | A process with emulated 32 bit SPARC/Linux syscalls |
| Stats::SparseHistData | Data structure of sparse histogram |
| Stats::SparseHistPrint | |
| Stats::SparseHistStor | Templatized storage and interface for a sparse histogram stat |
| LSQUnit< Impl >::SQEntry | |
| StackDistCalc | The stack distance calculator is a passive object that merely observes the addresses pass to it |
| MipsISA::StackTrace | |
| RiscvISA::StackTrace | |
| SparcISA::StackTrace | |
| PowerISA::StackTrace | |
| X86ISA::StackTrace | |
| AlphaISA::StackTrace | |
| ArmISA::StackTrace | |
| DefaultRename< Impl >::Stalls | Source of possible stalls |
| DefaultDecode< Impl >::Stalls | Source of possible stalls |
| DefaultFetch< Impl >::Stalls | Source of possible stalls |
| StaticInstFlags | |
| StaticInst | Base, ISA-independent static instruction class |
| Stats::StatStor | Templatized storage and interface for a simple scalar stat |
| StatTest | |
| StorageElement | |
| StorageMap | |
| Stats::StorageParams | |
| Stats::AvgStor::Params | |
| Stats::DistParams | The parameters for a distribution stat |
| Stats::AvgSampleStor::Params | |
| Stats::DistStor::Params | The parameters for a distribution stat |
| Stats::HistStor::Params | The parameters for a distribution stat |
| Stats::SampleStor::Params | |
| Stats::SparseHistStor::Params | The parameters for a sparse histogram stat |
| Stats::StatStor::Params | |
| StorageSpace | |
| StoreSet | Implements a store set predictor for determining if memory instructions are dependent upon each other |
| StoreTrace | |
| StridePrefetcher::StrideEntry | |
| StringWrap | |
| SubBlock | |
| EtherSwitch::SwitchTableEntry | |
| SymbolTable | |
| SyscallDesc | This class provides the wrapper interface for the system call implementations which are defined in the sim/syscall_emul files and bound to the ISAs in the architecture specific code (i.e |
| SyscallFlagTransTable | This struct is used to build target-OS-dependent tables that map the target's flags to the host's flags |
| SyscallReturn | This class represents the return value from an emulated system call, including any errno setting |
| ArmLinuxProcessBits::SyscallTable | |
| ArmFreebsdProcessBits::SyscallTable | |
| FaultModel::system_conf | |
| LTAGE::TageEntry | |
| TapListener | |
| MSHR::Target | |
| WriteQueueEntry::Target | |
| UFSHostDevice::taskStart | Task start information |
| TBETable< ENTRY > | |
| tcp_hdr | |
| Net::TcpHdr | |
| tcp_opt | |
| Net::TcpOpt | |
| Net::TcpPtr | |
| Stats::Temp | Helper class to construct formula node trees |
| TestClass | |
| X86Linux64::tgt_fsid | |
| ArmLinux64::tgt_iovec | |
| ArmFreebsd32::tgt_iovec | |
| ArmFreebsd64::tgt_iovec | |
| OperatingSystem::tgt_iovec | |
| X86Linux64::tgt_iovec | |
| Linux::tgt_iovec | |
| ArmLinux32::tgt_iovec | |
| SparcLinux::tgt_stat | |
| ArmLinux64::tgt_stat | |
| ArmLinux32::tgt_stat | |
| PowerLinux::tgt_stat | |
| ArmFreebsd64::tgt_stat | |
| Linux::tgt_stat | Stat buffer |
| Solaris::tgt_stat | Stat buffer |
| ArmFreebsd32::tgt_stat | |
| ArmLinux32::tgt_stat64 | |
| ArmFreebsd64::tgt_stat64 | |
| RiscvLinux::tgt_stat64 | |
| ArmFreebsd32::tgt_stat64 | |
| ArmLinux64::tgt_stat64 | |
| Sparc32Linux::tgt_stat64 | |
| PowerLinux::tgt_stat64 | |
| Solaris::tgt_stat64 | |
| Linux::tgt_stat64 | |
| X86Linux64::tgt_stat64 | |
| X86Linux64::tgt_statfs | |
| AlphaLinux::tgt_sysinfo | |
| MipsLinux::tgt_sysinfo | |
| Sparc32Linux::tgt_sysinfo | |
| ArmLinux32::tgt_sysinfo | |
| X86Linux32::tgt_sysinfo | |
| SparcLinux::tgt_sysinfo | |
| ArmLinux64::tgt_sysinfo | |
| X86Linux64::tgt_sysinfo | |
| Solaris::tgt_timespec | |
| ThermalEntity | An abstract class that represents any thermal entity which is used in the circuital thermal equivalent model |
| ThermalCapacitor | A ThermalCapacitor is used to model a thermal capacitance between two thermal domains |
| ThermalDomain | A ThermalDomain is used to group objects under that operate under the same temperature |
| ThermalReference | A ThermalReference is a thermal domain with fixed temperature |
| ThermalResistor | A ThermalResistor is used to model a thermal resistance between two thermal domains |
| Linux::thread_info | |
| ThreadContext | ThreadContext is the external interface to all thread state for anything outside of the CPU |
| CheckerThreadContext< TC > | Derived ThreadContext class for use with the Checker |
| O3ThreadContext< class > | Derived ThreadContext class for use with the O3CPU |
| ProxyThreadContext< TC > | ProxyThreadContext class that provides a way to implement a ThreadContext without having to derive from it |
| ProxyThreadContext< SimpleThread > | |
| LTAGE::ThreadHistory | |
| IndirectPredictor::ThreadInfo | |
| Linux::ThreadInfo | |
| FreeBSD::ThreadInfo | |
| Trace::ArmNativeTrace::ThreadState | |
| Trace::X86NativeTrace::ThreadState | |
| TickEvent | |
| TimingSimpleCPU::DcachePort::DTickEvent | |
| Time | |
| TimeBuffer< T > | |
| TimeBuffer< bool > | |
| TimeBuffer< Data > | |
| Minor::MinorBuffer< Data > | |
| TimeBuffer< DecodeStruct > | |
| TimeBuffer< ElemType > | |
| Minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits > | TimeBuffer with MinorTrace and Named interfaces |
| Minor::MinorBuffer< ElemType, ReportTraits > | |
| TimeBuffer< FetchStruct > | |
| TimeBuffer< IEWStruct > | |
| TimeBuffer< IssueStruct > | |
| TimeBuffer< Minor::BranchData > | |
| Minor::MinorBuffer< Minor::BranchData > | |
| TimeBuffer< Minor::ForwardInstData > | |
| Minor::MinorBuffer< Minor::ForwardInstData > | |
| TimeBuffer< Minor::ForwardLineData > | |
| Minor::MinorBuffer< Minor::ForwardLineData > | |
| TimeBuffer< RenameStruct > | |
| TimeBuffer< TimeStruct > | |
| TimeBufStruct< Impl > | Struct that defines all backwards communication |
| TimerTable | |
| ArmLinux32::timespec | |
| Linux::timespec | For clock_gettime() |
| RiscvLinux::timespec | |
| ArmLinux64::timespec | |
| OperatingSystem::timeval | For gettimeofday() |
| ArmLinux32::timeval | For gettimeofday() |
| ArmLinux64::timeval | For gettimeofday() |
| ArmFreebsd64::timeval | For gettimeofday() |
| Linux::timeval | For gettimeofday() |
| ArmFreebsd32::timeval | For gettimeofday() |
| TimingExprEvalContext | Object to gather the visible context for evaluation |
| TIR | |
| MipsISA::TlbEntry | |
| SparcISA::TlbEntry | |
| PowerISA::TlbEntry | |
| RiscvISA::TlbEntry | |
| TlbEntry | |
| X86ISA::GpuTlbEntry | |
| SparcISA::TlbMap | |
| SparcISA::TlbRange | |
| ArmISA::TlbTestInterface | |
| ArmFreebsd32::tms | For times() |
| PowerLinux::tms | For times() |
| ArmLinux64::tms | For times() |
| Linux::tms | For times() |
| ArmLinux32::tms | For times() |
| ArmFreebsd64::tms | For times() |
| Topology | |
| TraceCPU::FixedRetryGen::TraceElement | This struct stores a line in the trace file |
| TraceGen::TraceElement | This struct stores a line in the trace file |
| ElasticTrace::TraceInfo | |
| TraceRecord | Class for recording cache contents |
| MemChecker::Transaction | Captures the lifetimes of read and write operations, and the values they consumed or produced respectively |
| UFSHostDevice::transferDoneInfo | Transfer completion info |
| UFSHostDevice::transferInfo | Different events, and scenarios require different types of information |
| UFSHostDevice::transferStart | Transfer start information |
| TrafficGen::Transition | Struct to represent a probabilistic transition during parsing |
| BaseTLB::Translation | |
| ArmISA::Stage2LookUp | |
| ArmISA::Stage2MMU::Stage2Translation | This translation class is used to trigger the data fetch once a timing translation returns the translated physical address |
| DataTranslation< ExecContextPtr > | This class represents part of a data address translation |
| DefaultFetch< Impl >::FetchTranslation | |
| Minor::Fetch1::FetchRequest | Memory access queuing |
| Minor::LSQ::LSQRequest | Derived SenderState to carry data access info |
| TimingSimpleCPU::FetchTranslation | |
| X86ISA::GpuTLB::Translation | |
| Trie< Key, Value > | |
| Trie< Addr, X86ISA::TlbEntry > | |
| SparcISA::TteTag | |
| iGbReg::TxDesc | |
| udp_hdr | |
| Net::UdpHdr | |
| Net::UdpPtr | |
| UFSHostDevice::UFSHCDSGEntry | Struct UFSHCDSGEntry - UFSHCI PRD Entry baseAddr: Lower 32bit physical address DW-0 upperAddr: Upper 32bit physical address DW-1 reserved: Reserved for future use DW-2 size: size of physical segment DW-3 |
| UFSHostDevice::UFSHostDeviceStats | Statistics |
| UnifiedFreeList | FreeList class that simply holds the list of free integer and floating point registers |
| UnifiedRenameMap | Unified register rename map for all classes of registers |
| unordered_map | |
| FutexMap | FutexMap class holds a map of all futexes used in the system |
| BaseRemoteGDB::Unsupported | Exception to throw when something isn't supported |
| UFSHostDevice::UPIUMessage | UPIU tranfer message |
| UserDesc64 | |
| UFSHostDevice::UTPTransferCMDDesc | Struct UTPTransferCMDDesc - UFS Commad Descriptor structure commandUPIU: Command UPIU Frame address responseUPIU: Response UPIU Frame address PRDTable: Physcial Region Descriptor All lengths as defined by JEDEC220 |
| UFSHostDevice::UTPTransferReqDesc | Struct UTPTransferReqDesc - UTRD structure header: UTRD header DW-0 to DW-3 commandDescBaseAddrLo: UCD base address low DW-4 commandDescBaseAddrHi: UCD base address high DW-5 responseUPIULength: response UPIU length DW-6 responseUPIUOffset: response UPIU offset DW-6 PRDTableLength: Physical region descriptor length DW-7 PRDTableOffset: Physical region descriptor offset DW-7 |
| UFSHostDevice::UTPUPIUHeader | All the data structures are defined in the UFS standard This standard be found at the JEDEC website free of charge (login required): http://www.jedec.org/standards-documents/results/jesd220 |
| UFSHostDevice::UTPUPIURSP | Struct UTPUPIURSP - Response UPIU structure header: UPIU header DW-0 to DW-2 residualTransferCount: Residual transfer count DW-3 reserved: Reserved DW-4 to DW-7 senseDataLen: Sense data length DW-8 U16 senseData: Sense data field DW-8 to DW-12 |
| UFSHostDevice::UTPUPIUTaskReq | Struct UTPUPIUTaskReq - Task request UPIU structure header - UPIU header structure DW0 to DW-2 inputParam1: Input param 1 DW-3 inputParam2: Input param 2 DW-4 inputParam3: Input param 3 DW-5 reserved: Reserver DW-6 to DW-7 |
| Solaris::utsname | Interface struct for uname() |
| OperatingSystem::utsname | Interface struct for uname() |
| Linux::utsname | Interface struct for uname() |
| PowerISA::VAddr | |
| RiscvISA::VAddr | |
| SparcISA::VAddr | |
| MipsISA::VAddr | |
| ArmISA::VAddr | |
| AlphaISA::VAddr | |
| VecRegisterState | |
| std::vector< T > | STL vector class |
| std::vector< AbstractController * > | |
| std::vector< AbstractMemory * > | |
| std::vector< Addr > | |
| std::vector< AddrRange > | |
| std::vector< AlphaISA::TlbEntry > | |
| std::vector< ArmFreebsdProcessBits::SyscallTable > | |
| std::vector< ArmISA::PMU::CounterState > | |
| std::vector< ArmLinuxProcessBits::SyscallTable > | |
| std::vector< ArmV8KvmCPU::ArmV8KvmCPU::IntRegInfo > | |
| std::vector< ArmV8KvmCPU::ArmV8KvmCPU::MiscRegInfo > | |
| std::vector< BackingStoreEntry > | |
| std::vector< BankedArray::AccessRecord > | |
| std::vector< BankType > | |
| std::vector< BaseGlobalEvent::BarrierEvent * > | |
| std::vector< BasePixelPump::PixelEvent * > | |
| std::vector< BaseRemoteGDB * > | |
| std::vector< BasicExtLink * > | |
| std::vector< BasicIntLink * > | |
| std::vector< bool > | |
| std::vector< CCReg > | |
| std::vector< char * > | |
| std::vector< Check * > | |
| std::vector< Clocked * > | |
| std::vector< CoherentXBar::SnoopRespPort * > | |
| std::vector< ComputeUnit * > | |
| std::vector< ComputeUnit::DataPort * > | |
| std::vector< ComputeUnit::DTLBPort * > | |
| std::vector< const std::string * > | |
| std::vector< ContextID > | |
| std::vector< CopyEngine::CopyEngineChannel * > | |
| std::vector< Counter > | |
| std::vector< CreditLink * > | |
| std::vector< Cycles > | |
| std::vector< Debug::Flag * > | |
| std::vector< DefaultBTB::BTBEntry > | |
| std::vector< DerivedClockDomain * > | |
| std::vector< DmaDoneEvent * > | |
| std::vector< DmaDoneEvent > | |
| std::vector< DomainID > | |
| std::vector< double > | |
| std::vector< Drainable * > | |
| std::vector< DRAMCtrl::Bank > | |
| std::vector< DRAMCtrl::Command > | |
| std::vector< DRAMCtrl::Rank * > | |
| std::vector< DynInstPtr > | |
| std::vector< ElasticTrace::TraceInfo * > | |
| std::vector< EmulatedDriver * > | |
| std::vector< Entry > | |
| std::vector< EtherSwitch::Interface * > | |
| std::vector< FaultModel::system_conf > | |
| std::vector< FetchUnit > | |
| std::vector< flit * > | |
| std::vector< flitBuffer * > | |
| std::vector< FuncUnit * > | |
| std::vector< GDBListener * > | |
| std::vector< Gicv2mFrame * > | |
| std::vector< GPUStaticInst * > | |
| std::vector< HsaCode * > | |
| std::vector< HsailCode * > | |
| std::vector< HsaKernelInfo > | |
| std::vector< Index > | |
| std::vector< IndexNodeMap > | |
| std::vector< IndirectPredictor::ThreadInfo > | |
| std::vector< InputUnit * > | |
| std::vector< InstSeqNum > | |
| std::vector< int > | |
| std::vector< int32_t > | |
| std::vector< IntReg > | |
| std::vector< KvmVM::MemorySlot > | |
| std::vector< LinearEquation > | |
| std::vector< LinkOrder > | |
| std::vector< LSQUnit::SQEntry > | |
| std::vector< LTAGE::ThreadHistory > | |
| std::vector< MachInst > | |
| std::vector< MasterPort * > | |
| std::vector< MemDepEntryPtr > | |
| std::vector< MessageBuffer * > | |
| std::vector< Minor::Decode::DecodeThreadInfo > | |
| std::vector< Minor::Execute::ExecuteThreadInfo > | |
| std::vector< Minor::Fetch1::Fetch1ThreadInfo > | |
| std::vector< Minor::Fetch2::Fetch2ThreadInfo > | |
| std::vector< Minor::FUPipeline * > | |
| std::vector< Minor::InputBuffer< Minor::ForwardInstData > > | |
| std::vector< Minor::InputBuffer< Minor::ForwardLineData > > | |
| std::vector< Minor::MinorThread * > | |
| std::vector< Minor::Scoreboard > | |
| std::vector< MinorFU * > | |
| std::vector< MinorFUTiming * > | |
| std::vector< MinorOpClass * > | |
| std::vector< MiscReg > | |
| std::vector< MsgPtr > | |
| std::vector< MSHR > | |
| std::vector< MSIXPbaEntry > | |
| std::vector< MSIXTable > | |
| std::vector< NetDest > | |
| std::vector< NetworkInterface * > | |
| std::vector< NetworkLink * > | |
| std::vector< O3ThreadState * > | |
| std::vector< ObjectFile::Section > | |
| std::vector< OpDesc * > | |
| std::vector< OutputUnit * > | |
| std::vector< OutVcState * > | |
| std::vector< Packet * > | |
| std::vector< Packet > | |
| std::vector< PhysRegFile::PhysFloatReg > | |
| std::vector< PhysRegIndex > | |
| std::vector< Pixel > | |
| std::vector< Pl390::BankedRegs * > | |
| std::vector< PollEvent * > | |
| std::vector< PortID > | |
| std::vector< PowerModel * > | |
| std::vector< PowerModelState * > | |
| std::vector< PrefetchEntry > | |
| std::vector< ProbeListener * > | |
| std::vector< ProbeListenerArgBase< Arg > * > | |
| std::vector< ProbeListenerUPtr > | |
| std::vector< ProbePoint * > | |
| std::vector< Process * > | |
| std::vector< QueuedSlavePort * > | |
| std::vector< record_t > | |
| std::vector< ReqLayer * > | |
| std::vector< Request * > | |
| std::vector< RespLayer * > | |
| std::vector< Result > | |
| std::vector< ReturnAddrStack > | |
| std::vector< Router * > | |
| std::vector< RubyPort::MemSlavePort * > | |
| std::vector< RubyPort::PioMasterPort * > | |
| std::vector< SatCounter > | |
| std::vector< Scheduler > | |
| std::vector< Sequencer * > | |
| std::vector< Set > | |
| std::vector< SimpleExecContext * > | |
| std::vector< SlavePort * > | |
| std::vector< SnoopRespLayer * > | |
| std::vector< SrcClockDomain * > | |
| std::vector< SSID > | |
| std::vector< Stats::Counter > | |
| std::vector< Stats::DistData > | |
| std::vector< Stats::Histogram * > | |
| std::vector< std::deque > | |
| std::vector< std::deque< struct FlashDevice::CallBackEntry > > | |
| std::vector< std::function< HsaObject *(const std::string &, int, uint8_t *)> > | |
| std::vector< std::list > | |
| std::vector< std::map< uint32_t, AbstractController * > > | |
| std::vector< std::pair< int, AtomicOpFunctor * > > | |
| std::vector< std::pair< TCPIface::NodeInfo, int > > | |
| std::vector< std::pair< uint32_t, uint32_t > > | |
| std::vector< std::pair< Wavefront *, bool > > | |
| std::vector< std::pair< Wavefront *, DISPATCH_STATUS > > | |
| std::vector< std::string > | |
| std::vector< std::unique_ptr< BaseMemProbe::PacketListener > > | |
| std::vector< std::unique_ptr< BasicBlock > > | |
| std::vector< std::unique_ptr< GenericTimer::CoreTimers > > | |
| std::vector< std::unique_ptr< ObjectFile > > | |
| std::vector< std::vector< AbstractCacheEntry * > > | |
| std::vector< std::vector< Addr > > | |
| std::vector< std::vector< bool > > | |
| std::vector< std::vector< double > > | |
| std::vector< std::vector< IndirectPredictor::IPredEntry > > | |
| std::vector< std::vector< int > > | |
| std::vector< std::vector< MessageBuffer * > > | |
| std::vector< std::vector< MiscReg > > | |
| std::vector< std::vector< Stats::Histogram * > > | |
| std::vector< std::vector< std::pair< Wavefront *, WAVE_STATUS > > * > | |
| std::vector< std::vector< std::pair< Wavefront *, WAVE_STATUS > > > | |
| std::vector< std::vector< std::string > > | |
| std::vector< std::vector< std::vector< Addr > > > | |
| std::vector< std::vector< uint32_t > > | |
| std::vector< std::vector< uint64_t > > | |
| std::vector< std::vector< Wavefront * > * > | |
| std::vector< std::vector< Wavefront * > > | |
| std::vector< StorageElement * > | |
| std::vector< string > | |
| std::vector< struct ArmISA::ISA::MiscRegLUTEntry > | |
| std::vector< struct FlashDevice::PageMapEntry > | |
| std::vector< struct vring_used_elem > | |
| std::vector< Switch * > | |
| std::vector< System * > | |
| std::vector< TheGpuISA::RawMachInst > | |
| std::vector< TheISA::ISA * > | |
| std::vector< TheISA::PCState > | |
| std::vector< ThermalCapacitor * > | |
| std::vector< ThermalDomain * > | |
| std::vector< ThermalEntity * > | |
| std::vector< ThermalNode * > | |
| std::vector< ThermalReference * > | |
| std::vector< ThermalResistor * > | |
| std::vector< ThreadContext * > | |
| std::vector< ThreadID > | |
| std::vector< Throttle * > | |
| std::vector< Tick > | |
| std::vector< TimingExpr * > | |
| std::vector< TLBCoalescer::CpuSidePort * > | |
| std::vector< TLBCoalescer::MemSidePort * > | |
| std::vector< TlbEntry > | |
| std::vector< TraceCPU::ElasticDataGen::GraphNode * > | |
| std::vector< TraceRecord * > | |
| std::vector< UFSHostDevice::UFSSCSIDevice * > | |
| std::vector< uint32_t * > | |
| std::vector< uint32_t > | |
| std::vector< uint64_t > | |
| std::vector< uint8_t > | |
| std::vector< unsigned > | |
| std::vector< unsigned int > | |
| std::vector< value_type > | |
| std::vector< VectorMask > | |
| std::vector< VectorRegisterFile * > | |
| std::vector< VirtDescriptor > | |
| std::vector< VirtDescriptor::Index > | |
| std::vector< VirtQueue * > | |
| std::vector< VirtualChannel * > | |
| std::vector< VirtualReg > | |
| std::vector< VNET_type > | |
| std::vector< WaitClass > | |
| std::vector< Wavefront * > | |
| std::vector< WriteQueueEntry > | |
| std::vector< X86ISA::ACPI::SysDescTable * > | |
| std::vector< X86ISA::E820Entry * > | |
| std::vector< X86ISA::GpuTLB::CpuSidePort * > | |
| std::vector< X86ISA::GpuTLB::MemSidePort * > | |
| std::vector< X86ISA::GpuTlbEntry > | |
| std::vector< X86ISA::IntelMP::BaseConfigEntry * > | |
| std::vector< X86ISA::IntelMP::ExtConfigEntry * > | |
| std::vector< X86ISA::IntSinkPin * > | |
| std::vector< X86ISA::SMBios::SMBiosStructure * > | |
| Stats::VectorPrint | |
| Stats::VectorProxy< Stat > | |
| VirtDescriptor | VirtIO descriptor (chain) wrapper |
| VirtQueue::VirtRing< T > | VirtIO ring buffer wrapper |
| VirtQueue::VirtRing< struct vring_used_elem > | |
| VirtQueue::VirtRing< VirtDescriptor::Index > | |
| VirtualChannel | |
| Sinic::Device::VirtualReg | |
| VncKeyboard | A device that expects to receive input from the vnc server should derrive (through mulitple inheritence if necessary from VncKeyboard or VncMouse and call setKeyboard() or setMouse() respectively on the vnc server |
| Pl050 | |
| VncMouse | |
| Pl050 | |
| VPtr< T > | |
| ArmISA::VReg | 128-bit NEON vector register |
| vring | |
| vring_avail | |
| vring_desc | |
| vring_used | |
| vring_used_elem | |
| X86ISA::X86_64Process::VSyscallPage | |
| X86ISA::I386Process::VSyscallPage | |
| WaitClass | |
| ArmISA::TableWalker::WalkerState | |
| X86ISA::Walker::WalkerState | |
| ComputeUnit::waveIdentifier | |
| ComputeUnit::waveQueue | |
| WholeTranslationState | This class captures the state of an address translation |
| TimeBuffer< T >::wire | |
| MemChecker::WriteCluster | Captures sets of writes where all writes are overlapping with at least one other write |
| WriteMask | |
| UFSHostDevice::writeToDiskBurst | Disk transfer burst information |
| Base | |
| Stats::InfoProxy< Stat, Base > | |
