PCI device, base implementation is only config space. More...

#include <device.hh>

Inheritance diagram for PciDevice:

Public Member Functions
virtual Tick	writeConfig (PacketPtr pkt)
	Write to the PCI config space data that is stored locally. More...

virtual Tick	readConfig (PacketPtr pkt)
	Read from the PCI config space data that is stored locally. More...

Addr	pciToDma (Addr pci_addr) const

void	intrPost ()

void	intrClear ()

uint8_t	interruptLine () const

AddrRangeList	getAddrRanges () const override
	Determine the address ranges that this device responds to. More...

	PciDevice (const PciDeviceParams *params)
	Constructor for PCI Dev. More...

void	serialize (CheckpointOut &cp) const override
	Serialize this object to the given output stream. More...

void	unserialize (CheckpointIn &cp) override
	Reconstruct the state of this object from a checkpoint. More...

const PciBusAddr &	busAddr () const

Public Member Functions inherited from DmaDevice
	DmaDevice (const Params *p)

virtual	~DmaDevice ()

void	dmaWrite (Addr addr, int size, Event event, uint8_t data, Tick delay=0)

void	dmaRead (Addr addr, int size, Event event, uint8_t data, Tick delay=0)

bool	dmaPending () const

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

unsigned int	cacheBlockSize () const

BaseMasterPort &	getMasterPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a master port with a given name and index. More...

Public Member Functions inherited from PioDevice
	PioDevice (const Params *p)

virtual	~PioDevice ()

const Params *	params () const

virtual BaseSlavePort &	getSlavePort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a slave port with a given name and index. More...

Public Member Functions inherited from MemObject
const Params *	params () const

	MemObject (const Params *params)

Public Member Functions inherited from ClockedObject
	ClockedObject (const ClockedObjectParams *p)

const Params *	params () const

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Enums::PwrState	pwrState () const

std::string	pwrStateName () const

std::vector< double >	pwrStateWeights () const
	Returns the percentage residency for each power state. More...

void	computeStats ()
	Record stats values like state residency by computing the time difference from previous update. More...

void	pwrState (Enums::PwrState)

void	regStats () override
	Register statistics for this object. More...

Public Member Functions inherited from SimObject
const Params *	params () const

	SimObject (const Params *_params)

virtual	~SimObject ()

virtual const std::string	name () const

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...

virtual void	resetStats ()
	Reset statistics associated with this object. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

virtual void	startup ()
	startup() is the final initialization call before simulation. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from EventManager
	EventManager (EventManager &em)

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick)-1)

void	setCurTick (Tick newVal)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Clocked
void	updateClockPeriod () const
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Protected Member Functions
bool	isBAR (Addr addr, int bar) const
	Does the given address lie within the space mapped by the given base address register? More...

int	getBAR (Addr addr)
	Which base address register (if any) maps the given address? More...

bool	getBAR (Addr addr, int &bar, Addr &offs)
	Which base address register (if any) maps the given address? More...

Protected Member Functions inherited from PioDevice
virtual Tick	read (PacketPtr pkt)=0
	Pure virtual function that the device must implement. More...

virtual Tick	write (PacketPtr pkt)=0
	Pure virtual function that the device must implement. More...

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

Protected Attributes
const PciBusAddr	_busAddr

PCIConfig	config
	The current config space. More...

std::vector< MSIXTable >	msix_table
	MSIX Table and PBA Structures. More...

std::vector< MSIXPbaEntry >	msix_pba

uint32_t	BARSize [6]
	The size of the BARs. More...

Addr	BARAddrs [6]
	The current address mapping of the BARs. More...

bool	legacyIO [6]
	Whether the BARs are really hardwired legacy IO locations. More...

PciHost::DeviceInterface	hostInterface

Tick	pioDelay

Tick	configDelay


const int	PMCAP_BASE
	The capability list structures and base addresses. More...

const int	PMCAP_ID_OFFSET

const int	PMCAP_PC_OFFSET

const int	PMCAP_PMCS_OFFSET

PMCAP	pmcap

const int	MSICAP_BASE

MSICAP	msicap

const int	MSIXCAP_BASE

const int	MSIXCAP_ID_OFFSET

const int	MSIXCAP_MXC_OFFSET

const int	MSIXCAP_MTAB_OFFSET

const int	MSIXCAP_MPBA_OFFSET

int	MSIX_TABLE_OFFSET

int	MSIX_TABLE_END

int	MSIX_PBA_OFFSET

int	MSIX_PBA_END

MSIXCAP	msixcap

const int	PXCAP_BASE

PXCAP	pxcap

Protected Attributes inherited from DmaDevice
DmaPort	dmaPort

Protected Attributes inherited from PioDevice
System *	sys

PioPort	pioPort
	The pioPort that handles the requests for us and provides us requests that it sees. More...

Protected Attributes inherited from ClockedObject
Enums::PwrState	_currPwrState
	To keep track of the current power state. More...

Tick	prvEvalTick

Stats::Scalar	numPwrStateTransitions

Stats::Distribution	pwrStateClkGateDist

Stats::Vector	pwrStateResidencyTicks

Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Additional Inherited Members
Public Types inherited from DmaDevice
typedef DmaDeviceParams	Params

Public Types inherited from PioDevice
typedef PioDeviceParams	Params

Public Types inherited from MemObject
typedef MemObjectParams	Params

Public Types inherited from ClockedObject
typedef ClockedObjectParams	Params
	Parameters of ClockedObject. More...

Public Types inherited from SimObject
typedef SimObjectParams	Params

Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Get the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)

static void	unserializeGlobals (CheckpointIn &cp)

Static Public Attributes inherited from Serializable
static int	ckptCount = 0

static int	ckptMaxCount = 0

static int	ckptPrevCount = -1

Detailed Description

PCI device, base implementation is only config space.

Definition at line 70 of file device.hh.

Constructor & Destructor Documentation

PciDevice::PciDevice ( const PciDeviceParams * params )

Constructor for PCI Dev.

This function copies data from the config file object PCIConfigData and registers the device with a PciHost object.

Definition at line 66 of file device.cc.

References BARAddrs, BARSize, PCIConfig::baseAddr, PCIConfig::bist, PCIConfig::cacheLineSize, PCIConfig::capabilityPtr, PCIConfig::cardbusCIS, PCIConfig::classCode, PCIConfig::command, config, PCIConfig::device, PCIConfig::expansionROM, fatal, fatal_if(), PCIConfig::headerType, htole(), ArmISA::i, PCIConfig::interruptLine, PCIConfig::interruptPin, isPowerOf2(), PCIConfig::latencyTimer, legacyIO, letoh(), MSICAP::ma, PCIConfig::maximumLatency, MSICAP::mc, MSICAP::md, MSICAP::mid, PCIConfig::minimumGrant, MSICAP::mmask, MSIXCAP::mpba, MSICAP::mpend, msicap, msix_pba, MSIX_PBA_END, MSIX_PBA_OFFSET, msix_table, MSIX_TABLE_END, MSIX_TABLE_OFFSET, msixcap, MSIXCAP_BASE, MSIXVECS_PER_PBA, MSIXCAP::mtab, MSICAP::mua, MSIXCAP::mxc, MSIXCAP::mxid, PMCAP::pc, PMCAP::pid, pmcap, PMCAP::pmcs, PCIConfig::progIF, pxcap, PXCAP::pxcap, PXCAP::pxdc, PXCAP::pxdc2, PXCAP::pxdcap, PXCAP::pxdcap2, PXCAP::pxds, PXCAP::pxid, PXCAP::pxlc, PXCAP::pxlcap, PXCAP::pxls, PCIConfig::reserved, PCIConfig::revision, PCIConfig::status, PCIConfig::subClassCode, PCIConfig::subsystemID, PCIConfig::subsystemVendorID, and PCIConfig::vendor.

Member Function Documentation

const PciBusAddr& PciDevice::busAddr ( ) const

inline

Definition at line 225 of file device.hh.

References _busAddr.

AddrRangeList PciDevice::getAddrRanges ( ) const

overridevirtual

Determine the address ranges that this device responds to.

Returns: a list of non-overlapping address ranges

Implements PioDevice.

Definition at line 277 of file device.cc.

References BARAddrs, BARSize, RangeSize(), and X86ISA::x.

int PciDevice::getBAR ( Addr addr )

inlineprotected

Which base address register (if any) maps the given address?

Returns: The BAR number (0-5 inclusive), or -1 if none.

Definition at line 134 of file device.hh.

References ArmISA::i, and isBAR().

Referenced by getBAR(), PciVirtIO::read(), CopyEngine::read(), IGbE::read(), PciVirtIO::write(), CopyEngine::write(), and IGbE::write().

bool PciDevice::getBAR	(	Addr	addr,
		int &	bar,
		Addr &	offs
	)

inlineprotected

Which base address register (if any) maps the given address?

Parameters

addr	The address to check.

Return values

bar	The BAR number (0-5 inclusive), only valid if return value is true.
offs	The offset from the base address, only valid if return value is true.

Returns: True iff address maps to a base address register's region.

Definition at line 153 of file device.hh.

References ArmISA::b, BARAddrs, and getBAR().

uint8_t PciDevice::interruptLine ( ) const

inline

Definition at line 196 of file device.hh.

References config, PCIConfig::interruptLine, and letoh().

Referenced by GenericPciHost::mapPciInterrupt().

void PciDevice::intrClear ( )

inline

Definition at line 194 of file device.hh.

References PciHost::DeviceInterface::clearInt(), and hostInterface.

Referenced by IGbE::cpuClearInt(), Sinic::Base::cpuIntrClear(), NSGigE::cpuIntrClear(), IdeDisk::intrClear(), and PciVirtIO::read().

void PciDevice::intrPost ( )

inline

Definition at line 193 of file device.hh.

References hostInterface, and PciHost::DeviceInterface::postInt().

Referenced by Sinic::Base::cpuInterrupt(), NSGigE::cpuInterrupt(), IGbE::cpuPostInt(), IdeController::intrPost(), and PciVirtIO::kick().

bool PciDevice::isBAR	(	Addr	addr,
		int	bar
	)		const

inlineprotected

Does the given address lie within the space mapped by the given base address register?

Definition at line 123 of file device.hh.

References BARAddrs, and BARSize.

Referenced by getBAR().

Addr PciDevice::pciToDma ( Addr pci_addr ) const

inline

Definition at line 189 of file device.hh.

References PciHost::DeviceInterface::dmaAddr(), and hostInterface.

Referenced by IGbE::TxDescCache::actionAfterWb(), IGbE::DescCache< T >::fetchDescriptors1(), IGbE::TxDescCache::getPacketData(), IGbE::DescCache< iGbReg::RxDesc >::pciToDma(), IdeDisk::pciToDma(), IGbE::TxDescCache::processContextDesc(), Sinic::Device::rxKick(), Sinic::Device::txKick(), IGbE::DescCache< T >::writeback1(), and IGbE::RxDescCache::writePacket().

Tick PciDevice::readConfig ( PacketPtr pkt )

virtual

Read from the PCI config space data that is stored locally.

This may be overridden by the device but at some point it will eventually call this for normal operations that it does not need to override.

Parameters

pkt	packet containing the write the offset into config space

Reimplemented in IdeController.

Definition at line 220 of file device.cc.

References _busAddr, config, configDelay, PCIConfig::data, PciBusAddr::dev, DPRINTF, PciBusAddr::func, Packet::get(), Packet::getAddr(), Packet::getSize(), Packet::makeAtomicResponse(), SimObject::name(), ArmISA::offset, panic, PCI_CONFIG_SIZE, PCI_DEVICE_SPECIFIC, Packet::set(), and warn_once.

Referenced by GenericPciHost::read(), NSGigE::read(), and IdeController::readConfig().

void PciDevice::serialize ( CheckpointOut & cp ) const

overridevirtual

Serialize this object to the given output stream.

Parameters

os	The stream to serialize to.

Implements Serializable.

Reimplemented in IdeController.

Definition at line 425 of file device.cc.

References BARAddrs, BARSize, bits(), config, csprintf(), PCIConfig::data, ArmISA::i, MSICAP::ma, MSICAP::mc, MSICAP::md, MSICAP::mid, MSICAP::mmask, MSIXCAP::mpba, MSICAP::mpend, msicap, msix_pba, msix_table, msixcap, MSIXCAP_BASE, MSIXVECS_PER_PBA, MSIXCAP::mtab, MSICAP::mua, MSIXCAP::mxc, MSIXCAP::mxid, paramOut(), PMCAP::pc, PMCAP::pid, pmcap, PMCAP::pmcs, pxcap, PXCAP::pxcap, PXCAP::pxdc, PXCAP::pxdc2, PXCAP::pxdcap, PXCAP::pxdcap2, PXCAP::pxds, PXCAP::pxid, PXCAP::pxlc, PXCAP::pxlcap, PXCAP::pxls, SERIALIZE_ARRAY, and SERIALIZE_SCALAR.

Referenced by Sinic::Base::serialize(), IdeController::serialize(), CopyEngine::serialize(), NSGigE::serialize(), and IGbE::serialize().

void PciDevice::unserialize ( CheckpointIn & cp )

overridevirtual

Reconstruct the state of this object from a checkpoint.

Parameters

cp	The checkpoint use.
section	The section name of this object

Implements Serializable.

Reimplemented in IdeController.

Definition at line 490 of file device.cc.

References BARAddrs, BARSize, bits(), config, csprintf(), PCIConfig::data, ArmISA::i, MSICAP::ma, MSICAP::mc, MSICAP::md, MSICAP::mid, MSICAP::mmask, MSIXCAP::mpba, MSICAP::mpend, msicap, msix_pba, msix_table, msixcap, MSIXCAP_BASE, MSIXCAP::mtab, MSICAP::mua, MSIXCAP::mxc, MSIXCAP::mxid, paramIn(), PMCAP::pc, PMCAP::pid, PioDevice::pioPort, pmcap, PMCAP::pmcs, pxcap, PXCAP::pxcap, PXCAP::pxdc, PXCAP::pxdc2, PXCAP::pxdcap, PXCAP::pxdcap2, PXCAP::pxds, PXCAP::pxid, PXCAP::pxlc, PXCAP::pxlcap, PXCAP::pxls, SlavePort::sendRangeChange(), UNSERIALIZE_ARRAY, and UNSERIALIZE_SCALAR.

Referenced by Sinic::Base::unserialize(), IdeController::unserialize(), CopyEngine::unserialize(), NSGigE::unserialize(), and IGbE::unserialize().

Tick PciDevice::writeConfig ( PacketPtr pkt )

virtual

Write to the PCI config space data that is stored locally.

This may be overridden by the device but at some point it will eventually call this for normal operations that it does not need to override.

Parameters

pkt	packet containing the write the offset into config space

Reimplemented in IGbE, NSGigE, and IdeController.

Definition at line 288 of file device.cc.

References _busAddr, BAR_IO_MASK, BAR_IO_SPACE, BAR_MEM_MASK, BAR_NUMBER, BARAddrs, BARSize, PCIConfig::baseAddr, PCIConfig::cacheLineSize, PCIConfig::command, config, configDelay, PciBusAddr::dev, DPRINTF, PCIConfig::expansionROM, PciBusAddr::func, Packet::get(), Packet::getAddr(), Packet::getSize(), hostInterface, htole(), PCIConfig::interruptLine, PCIConfig::latencyTimer, legacyIO, letoh(), Packet::makeAtomicResponse(), PciHost::DeviceInterface::memAddr(), SimObject::name(), ArmISA::offset, panic, PCI0_BASE_ADDR0, PCI0_BASE_ADDR1, PCI0_BASE_ADDR2, PCI0_BASE_ADDR3, PCI0_BASE_ADDR4, PCI0_BASE_ADDR5, PCI0_INTERRUPT_LINE, PCI0_INTERRUPT_PIN, PCI0_MAXIMUM_LATENCY, PCI0_MINIMUM_GRANT, PCI0_ROM_BASE_ADDR, PCI_CACHE_LINE_SIZE, PCI_CLASS_CODE, PCI_COMMAND, PCI_CONFIG_SIZE, PCI_DEVICE_SPECIFIC, PCI_LATENCY_TIMER, PCI_REVISION_ID, PCI_STATUS, PciHost::DeviceInterface::pioAddr(), PioDevice::pioPort, SlavePort::sendRangeChange(), PCIConfig::status, and warn_once.

Referenced by IdeController::writeConfig(), NSGigE::writeConfig(), and IGbE::writeConfig().

Member Data Documentation

const PciBusAddr PciDevice::_busAddr

protected

Definition at line 73 of file device.hh.

Referenced by busAddr(), readConfig(), and writeConfig().

Addr PciDevice::BARAddrs[6]

protected

The current address mapping of the BARs.

Definition at line 113 of file device.hh.

Referenced by getAddrRanges(), getBAR(), IdeController::IdeController(), isBAR(), PciDevice(), Sinic::Device::read(), serialize(), unserialize(), Sinic::Device::write(), IdeController::writeConfig(), and writeConfig().

uint32_t PciDevice::BARSize[6]

protected

The size of the BARs.

Definition at line 110 of file device.hh.

Referenced by getAddrRanges(), IdeController::IdeController(), isBAR(), PciDevice(), PciVirtIO::PciVirtIO(), Sinic::Device::read(), serialize(), unserialize(), Sinic::Device::write(), and writeConfig().

PCIConfig PciDevice::config

protected

The current config space.

Definition at line 76 of file device.hh.

Referenced by IdeController::IdeController(), interruptLine(), PciDevice(), PciVirtIO::PciVirtIO(), Sinic::Device::read(), readConfig(), serialize(), unserialize(), Sinic::Device::write(), IdeController::writeConfig(), writeConfig(), and NSGigE::writeConfig().

Tick PciDevice::configDelay

protected

Definition at line 186 of file device.hh.

Referenced by IdeController::readConfig(), readConfig(), IdeController::writeConfig(), writeConfig(), NSGigE::writeConfig(), and IGbE::writeConfig().

PciHost::DeviceInterface PciDevice::hostInterface

protected

Definition at line 183 of file device.hh.

Referenced by intrClear(), intrPost(), pciToDma(), and writeConfig().

bool PciDevice::legacyIO[6]

protected

Whether the BARs are really hardwired legacy IO locations.

Definition at line 116 of file device.hh.

Referenced by IdeController::IdeController(), PciDevice(), and writeConfig().

MSICAP PciDevice::msicap

protected

Definition at line 88 of file device.hh.

Referenced by PciDevice(), serialize(), and unserialize().

const int PciDevice::MSICAP_BASE

protected

Definition at line 87 of file device.hh.

std::vector<MSIXPbaEntry> PciDevice::msix_pba

protected

Definition at line 107 of file device.hh.

Referenced by PciDevice(), serialize(), and unserialize().

int PciDevice::MSIX_PBA_END

protected

Definition at line 98 of file device.hh.

Referenced by PciDevice().

int PciDevice::MSIX_PBA_OFFSET

protected

Definition at line 97 of file device.hh.

Referenced by PciDevice().

std::vector<MSIXTable> PciDevice::msix_table

protected

MSIX Table and PBA Structures.

Definition at line 106 of file device.hh.

Referenced by PciDevice(), serialize(), and unserialize().

int PciDevice::MSIX_TABLE_END

protected

Definition at line 96 of file device.hh.

Referenced by PciDevice().

int PciDevice::MSIX_TABLE_OFFSET

protected

Definition at line 95 of file device.hh.

Referenced by PciDevice().

MSIXCAP PciDevice::msixcap

protected

Definition at line 99 of file device.hh.

Referenced by PciDevice(), serialize(), and unserialize().

const int PciDevice::MSIXCAP_BASE

protected

Definition at line 90 of file device.hh.

Referenced by PciDevice(), serialize(), and unserialize().

const int PciDevice::MSIXCAP_ID_OFFSET

protected

Definition at line 91 of file device.hh.

const int PciDevice::MSIXCAP_MPBA_OFFSET

protected

Definition at line 94 of file device.hh.

const int PciDevice::MSIXCAP_MTAB_OFFSET

protected

Definition at line 93 of file device.hh.

const int PciDevice::MSIXCAP_MXC_OFFSET

protected

Definition at line 92 of file device.hh.

Tick PciDevice::pioDelay

protected

Definition at line 185 of file device.hh.

Referenced by IdeController::read(), CopyEngine::read(), Sinic::Device::read(), NSGigE::read(), IGbE::read(), IdeController::write(), CopyEngine::write(), Sinic::Device::write(), NSGigE::write(), and IGbE::write().

PMCAP PciDevice::pmcap

protected

Definition at line 85 of file device.hh.

Referenced by PciDevice(), serialize(), and unserialize().

const int PciDevice::PMCAP_BASE

protected

The capability list structures and base addresses.

Definition at line 81 of file device.hh.

const int PciDevice::PMCAP_ID_OFFSET

protected

Definition at line 82 of file device.hh.

const int PciDevice::PMCAP_PC_OFFSET

protected

Definition at line 83 of file device.hh.

const int PciDevice::PMCAP_PMCS_OFFSET

protected

Definition at line 84 of file device.hh.

PXCAP PciDevice::pxcap

protected

Definition at line 102 of file device.hh.

Referenced by PciDevice(), serialize(), and unserialize().

const int PciDevice::PXCAP_BASE

protected

Definition at line 101 of file device.hh.

The documentation for this class was generated from the following files:

dev/pci/device.hh
dev/pci/device.cc

Public Member Functions

Protected Member Functions

Protected Attributes

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

Member Function Documentation

Member Data Documentation