trace.hh File Reference

#include <string>
#include "base/cprintf.hh"
#include "base/debug.hh"
#include "base/match.hh"
#include "base/types.hh"
#include "sim/core.hh"

Go to the source code of this file.

Classes
class	Trace::Logger
	Debug logging base class. More...
class	Trace::OstreamLogger
	Logging wrapper for ostreams with the format: <when>: <name>: <message-body> More...
struct	StringWrap
class	Named

Namespaces
	Trace

Macros
#define	DTRACE(x)   (false)
#define	DDUMP(x, data, count)   do {} while (0)
#define	DPRINTF(x,...)   do {} while (0)
#define	DPRINTFS(x,...)   do {} while (0)
#define	DPRINTFR(...)   do {} while (0)
#define	DDUMPN(data, count)   do {} while (0)
#define	DPRINTFN(...)   do {} while (0)
#define	DPRINTFNR(...)   do {} while (0)

Functions
Logger *	Trace::getDebugLogger ()
	Get the current global debug logger. More...
std::ostream &	Trace::output ()
	Get the ostream from the current global logger. More...
void	Trace::setDebugLogger (Logger *logger)
	Delete the current global logger and assign a new one. More...
void	Trace::enable ()
	Enable/disable debug logging. More...
void	Trace::disable ()
const std::string &	name ()

Macro Definition Documentation

#define DDUMP	(		x,
			data,
			count
	)		do {} while (0)

Definition at line 211 of file trace.hh.

Referenced by BaseRemoteGDB::cmd_unsupported(), VirtDescriptor::dump(), VirtIO9PBase::dumpMsg(), LinuxArmSystem::initState(), SimpleDisk::read(), RawDiskImage::read(), CowDiskImage::read(), StubSlavePort::recvAtomic(), EtherTapBase::recvSimulated(), Sinic::Device::rxDmaDone(), NSGigE::rxDmaReadDone(), NSGigE::rxDmaWriteDone(), DistEtherLink::RxLink::rxDone(), Sinic::Device::rxFilter(), NSGigE::rxFilter(), EtherBus::send(), EtherTapBase::sendSimulated(), EtherLink::Link::transmit(), Sinic::Device::transmit(), NSGigE::transmit(), EtherLink::Link::txComplete(), Sinic::Device::txDmaDone(), NSGigE::txDmaReadDone(), NSGigE::txDmaWriteDone(), EtherBus::txDone(), RawDiskImage::write(), and CowDiskImage::write().

#define DDUMPN	(		data,
			count
	)		do {} while (0)

Definition at line 215 of file trace.hh.

#define DPRINTF	(		x,
			...
	)		do {} while (0)

Definition at line 212 of file trace.hh.

Referenced by ArmISA::TLB::_flushMva(), MemChecker::abortWrite(), AlphaISA::RemoteGDB::acc(), ArmISA::RemoteGDB::acc(), Cache::access(), AbstractMemory::access(), DRAMSim2::accessAndRespond(), DRAMCtrl::accessAndRespond(), LRU::accessBlock(), FlashDevice::accessDevice(), FlashDevice::accessTimes(), IGbE::TxDescCache::actionAfterWb(), FlashDevice::actionComplete(), O3ThreadContext< class >::activate(), DRAMCtrl::activateBank(), BaseKvmCPU::activateContext(), MinorCPU::activateContext(), AtomicSimpleCPU::activateContext(), TimingSimpleCPU::activateContext(), ActivityRecorder::activateStage(), DefaultIEW< Impl >::activateStage(), FullO3CPU< Impl >::activateThread(), ActivityRecorder::activity(), DefaultIEW< Impl >::activityThisCycle(), CheckTable::addCheck(), ElasticTrace::addCommittedInst(), ElasticTrace::addDepTraceRecord(), ArmISA::PMU::addEventProbe(), InstructionQueue< Impl >::addIfReady(), LabelMap::addLabel(), InstructionQueue< Impl >::addReadyMemInst(), UnifiedFreeList::addReg(), StorageSpace::addSymbol(), PseudoInst::addsymbol(), InstructionQueue< Impl >::addToDependents(), DRAMCtrl::addToReadQueue(), DRAMCtrl::addToWriteQueue(), ActivityRecorder::advance(), TimingSimpleCPU::advanceInst(), Checker< Impl >::advancePC(), ComputeUnit::AllAtBarrier(), DirectoryMemory::allocate(), CacheMemory::allocate(), Cache::allocateBlock(), StridePrefetcher::PCTable::allocateNewContext(), BaseCache::allocateWriteBuffer(), SwitchAllocator::arbitrate_outports(), X86KvmCPU::archIsDrained(), MessageBuffer::areNSlotsAvailable(), AlphaProcess::argsInit(), MipsProcess::argsInit(), PowerProcess::argsInit(), RiscvProcess::argsInit(), SparcProcess::argsInit(), ArmProcess::argsInit(), X86ISA::X86Process::argsInit(), PosixKvmTimer::arm(), PseudoInst::arm(), ElasticTrace::assignRobDep(), GPUCoalescer::atomicCallback(), EtherTapStub::attach(), LTAGE::baseUpdate(), CxxConfigManager::bindObjectPorts(), CxxConfigManager::bindPort(), DefaultDecode< Impl >::block(), DefaultRename< Impl >::block(), DefaultIEW< Impl >::block(), BrigObject::BrigObject(), LTAGE::btbUpdate(), DefaultFetch< Impl >::buildInst(), DefaultRename< Impl >::calcFreeLQEntries(), DefaultRename< Impl >::calcFreeSQEntries(), StridePrefetcher::calculatePrefetch(), Minor::LSQ::StoreBuffer::canForwardDataToLoad(), Minor::Scoreboard::canInstIssue(), Check::changeAddress(), AlphaISA::Kernel::Statistics::changeMode(), Minor::Fetch1::changeStream(), CopyEngine::CopyEngineChannel::channelWrite(), Trace::ArmNativeTrace::check(), StoreSet::checkClear(), Cache::CacheReqPacketQueue::checkConflictingSnoop(), FlashDevice::checkDrain(), UFSHostDevice::checkDrain(), IGbE::checkDrain(), DRAMCtrl::Rank::checkDrainDone(), StoreSet::checkInst(), Minor::Execute::checkInterrupts(), X86ISA::Interrupts::checkInterrupts(), AbstractMemory::checkLockedAddrList(), DefaultIEW< Impl >::checkMisprediction(), ArmISA::TLB::checkPermissions(), ArmISA::TLB::checkPermissions64(), VncServer::checkProtocolVersion(), CacheMemory::checkResourceAvailable(), VncServer::checkSecurity(), DefaultDecode< Impl >::checkSignalsAndUpdate(), DefaultIEW< Impl >::checkSignalsAndUpdate(), DefaultRename< Impl >::checkSignalsAndUpdate(), DefaultFetch< Impl >::checkSignalsAndUpdate(), LSQUnit< Impl >::checkSnoop(), DefaultDecode< Impl >::checkStall(), DefaultIEW< Impl >::checkStall(), DefaultRename< Impl >::checkStall(), DefaultFetch< Impl >::checkStall(), CheckTable::CheckTable(), LSQUnit< Impl >::checkViolations(), Trace::X86NativeTrace::checkXMM(), IGbE::chkInterrupt(), DRAMCtrl::chooseNext(), Cache::cleanEvictBlk(), FullO3CPU< Impl >::cleanUpRemovedInsts(), IntrControl::clear(), MipsISA::Interrupts::clear(), AlphaISA::Interrupts::clear(), SparcISA::Interrupts::clear(), ArmISA::Interrupts::clear(), MipsISA::Interrupts::clearAll(), AlphaISA::Interrupts::clearAll(), ArmISA::Interrupts::clearAll(), BaseCache::CacheSlavePort::clearBlocked(), BaseCache::clearBlocked(), TsunamiCChip::clearDRIR(), Minor::Scoreboard::clearInstDests(), PciHost::DeviceInterface::clearInt(), MuxingKvmGic::clearInt(), UFSHostDevice::clearInterrupt(), MaltaCChip::clearIntr(), MaltaIO::clearIntr(), TsunamiCChip::clearIPI(), TsunamiCChip::clearITI(), AbstractCacheEntry::clearLocked(), CacheMemory::clearLocked(), Minor::LSQ::clearMemBarrier(), TsunamiIO::clearPIC(), MuxingKvmGic::clearPPInt(), Pl390::clearPPInt(), BaseRemoteGDB::clearTempBreakpoint(), SrcClockDomain::clockPeriod(), BaseRemoteGDB::cmd_clr_hw_bkpt(), BaseRemoteGDB::cmd_set_hw_bkpt(), BaseRemoteGDB::cmd_unsupported(), KvmVM::coalesceMMIO(), IndirectPredictor::commit(), InstructionQueue< Impl >::commit(), DefaultCommit< Impl >::commit(), Minor::Execute::commit(), DefaultCommit< Impl >::commitHead(), Minor::Execute::commitInst(), DefaultCommit< Impl >::commitInsts(), LSQUnit< Impl >::commitLoad(), LSQUnit< Impl >::commitStores(), CommMonitor::CommMonitor(), ThreadContext::compare(), ElasticTrace::compDelayPhysRegDep(), ElasticTrace::compDelayRob(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::completeAcc(), HsailISA::AtomicInst< MemDataType, AddrOperandType, NumSrcOperands, HasDst >::completeAcc(), MemDepUnit< MemDepPred, Impl >::completeBarrier(), MemDepUnit< MemDepPred, Impl >::completed(), LSQUnit< Impl >::completeDataAccess(), ArmISA::TableWalker::completeDrain(), TimingSimpleCPU::completeIfetch(), GPUCoalescer::completeIssue(), TraceCPU::ElasticDataGen::completeMemAccess(), InstructionQueue< Impl >::completeMemInst(), MemChecker::completeRead(), GarnetSyntheticTraffic::completeRequest(), MemTest::completeRequest(), LSQUnit< Impl >::completeStore(), MemChecker::completeWrite(), IGbE::TxDescCache::completionWriteback(), DRAMCtrl::Rank::computeStats(), MipsISA::ISA::configCP(), TCPIface::connect(), VirtIO9PSocket::connectSocket(), Terminal::console_in(), VirtQueue::consumeDescriptor(), AlphaISA::Kernel::Statistics::context(), MuxingKvmGic::copyCpuRegister(), MuxingKvmGic::copyDistRegister(), Sp804::Timer::counterAtZero(), X86ISA::I8254::counterInterrupt(), Intel8254Timer::counterInterrupt(), ArchTimer::counterLimitReached(), PL031::counterMatch(), IGbE::cpuClearInt(), Sinic::Base::cpuInterrupt(), NSGigE::cpuInterrupt(), Sinic::Base::cpuIntrClear(), NSGigE::cpuIntrClear(), Sinic::Base::cpuIntrPost(), NSGigE::cpuIntrPost(), IGbE::cpuPostInt(), PhysicalMemory::createBackingStore(), Cache::createMissPacket(), VncServer::data(), Pl011::dataAvailable(), TraceCPU::dcacheRecvTimingResp(), TraceCPU::dcacheRetryRecvd(), ActivityRecorder::deactivateStage(), DefaultIEW< Impl >::deactivateStage(), FullO3CPU< Impl >::deactivateThread(), CacheMemory::deallocate(), Queue< WriteQueueEntry >::deallocate(), PseudoInst::debugbreak(), Check::debugPrint(), DefaultDecode< Impl >::decode(), DRAMCtrl::decodeAddr(), DefaultDecode< Impl >::decodeInsts(), OutputUnit::decrement_credit(), DefaultBTB::DefaultBTB(), DefaultCommit< Impl >::DefaultCommit(), DefaultFetch< Impl >::DefaultFetch(), KvmVM::delayedStartup(), CxxConfigManager::deleteObjects(), Minor::LSQ::StoreBuffer::deleteRequest(), X86KvmCPU::deliverInterrupts(), SparcISA::TLB::demapAll(), SparcISA::TLB::demapContext(), SparcISA::TLB::demapPage(), MessageBuffer::dequeue(), SimpleMemory::dequeue(), EtherTapStub::detach(), VncServer::detach(), Sinic::Device::devIntrChangeMask(), NSGigE::devIntrChangeMask(), Sinic::Device::devIntrClear(), NSGigE::devIntrClear(), Sinic::Device::devIntrPost(), NSGigE::devIntrPost(), PosixKvmTimer::disarm(), FunctionRefOperand::disassemble(), DefaultIEW< Impl >::dispatch(), Shader::dispatch_workgroups(), IdeController::dispatchAccess(), DefaultIEW< Impl >::dispatchInsts(), DistEtherLink::DistEtherLink(), DistIface::DistIface(), DmaPort::dmaAction(), TsunamiPChip::dmaAddr(), Pl111::dmaDone(), IdeDisk::dmaPrdReadDone(), IdeDisk::dmaWriteDone(), X86ISA::Decoder::doDisplacementState(), IdeDisk::doDmaDataRead(), IdeDisk::doDmaDataWrite(), IdeDisk::doDmaRead(), IdeDisk::doDmaTransfer(), IdeDisk::doDmaWrite(), DRAMCtrl::doDRAMAccess(), X86ISA::Decoder::doFromCacheState(), X86ISA::Decoder::doImmediateState(), ArmISA::TableWalker::doL1Descriptor(), ArmISA::TableWalker::doL1DescriptorWrapper(), ArmISA::TableWalker::doL2Descriptor(), ArmISA::TableWalker::doL2DescriptorWrapper(), ArmISA::TableWalker::doLongDescriptor(), ArmISA::TableWalker::doLongDescriptorWrapper(), SparcISA::TLB::doMmuRegRead(), SparcISA::TLB::doMmuRegWrite(), X86ISA::Decoder::doModRMState(), X86ISA::Decoder::doOneByteOpcodeState(), X86ISA::Decoder::doPrefixState(), X86ISA::Decoder::doResetState(), PCEventQueue::doService(), X86ISA::Decoder::doSIBState(), ROB< Impl >::doSquash(), DefaultRename< Impl >::doSquash(), InstructionQueue< Impl >::doSquash(), DefaultFetch< Impl >::doSquash(), X86ISA::Decoder::doThreeByte0F38OpcodeState(), X86ISA::Decoder::doThreeByte0F3AOpcodeState(), Cache::doTimingSupplyResponse(), X86ISA::Decoder::doTwoByteOpcodeState(), X86ISA::Decoder::doVexOpcodeState(), FlashDevice::drain(), BaseKvmCPU::drain(), CopyEngine::CopyEngineChannel::drain(), BaseXBar::Layer< SrcType, DstType >::drain(), Minor::Pipeline::drain(), DmaPort::drain(), MinorCPU::drain(), RubyPort::drain(), UFSHostDevice::drain(), SimpleMemory::drain(), AtomicSimpleCPU::drain(), PacketQueue::drain(), TimingSimpleCPU::drain(), FullO3CPU< Impl >::drain(), Minor::Execute::drain(), IGbE::drain(), DistIface::drain(), ArmISA::TableWalker::drain(), DRAMCtrl::drain(), BaseKvmCPU::drainResume(), CopyEngine::CopyEngineChannel::drainResume(), Minor::Pipeline::drainResume(), MinorCPU::drainResume(), AtomicSimpleCPU::drainResume(), TimingSimpleCPU::drainResume(), Minor::Execute::drainResume(), FullO3CPU< Impl >::drainResume(), IGbE::drainResume(), DistIface::drainResume(), DefaultFetch< Impl >::drainStall(), DRAMCtrl::DRAMCtrl(), DRAMSim2::DRAMSim2(), Pl390::driveIrqEn(), Pl390::driveLegIRQ(), Pl390::driveSPI(), VirtDescriptor::dump(), Minor::Fetch2::dumpAllInput(), VirtIO9PBase::dumpMsg(), PseudoInst::dumpresetstats(), PseudoInst::dumpstats(), TraceCPU::ElasticDataGen::ElasticDataGen(), DefaultIEW< Impl >::emptyRenameInsts(), ArmISA::EndBitUnion(), MessageBuffer::enqueue(), CacheRecorder::enqueueNextFetchRequest(), CacheRecorder::enqueueNextFlushRequest(), TrafficGen::enterState(), SnoopFilter::eraseIfNullEntry(), TCPIface::establishConnection(), IGbE::ethRxPkt(), IGbE::ethTxDone(), Minor::Pipeline::evaluate(), Minor::Decode::evaluate(), Minor::Fetch2::evaluate(), Minor::Execute::evaluate(), Minor::Fetch1::evaluate(), LocalMemPipeline::exec(), GlobalMemPipeline::exec(), GpuDispatcher::exec(), Wavefront::exec(), Minor::ExecContext::ExecContext(), Minor::Scoreboard::execSeqNumToWaitFor(), HsailISA::LdInst< MemDataType, DestDataType, AddrOperandType >::execute(), TraceCPU::ElasticDataGen::execute(), HsailISA::Ret::execute(), HsailISA::StInst< MemDataType, SrcDataType, AddrOperandType >::execute(), DefaultIEW< Impl >::executeInsts(), LSQUnit< Impl >::executeLoad(), Minor::Execute::executeMemRefInst(), TraceCPU::ElasticDataGen::executeMemReq(), LSQUnit< Impl >::executeStore(), FetchUnit::fetch(), TimingSimpleCPU::fetch(), DefaultFetch< Impl >::fetch(), Minor::Fetch1::Fetch1(), CopyEngine::CopyEngineChannel::fetchAddrComplete(), DefaultFetch< Impl >::fetchCacheLine(), IGbE::DescCache< T >::fetchComplete(), CopyEngine::CopyEngineChannel::fetchDescComplete(), CopyEngine::CopyEngineChannel::fetchDescriptor(), ArmISA::TableWalker::fetchDescriptor(), IGbE::DescCache< T >::fetchDescriptors(), IGbE::DescCache< T >::fetchDescriptors1(), Minor::Fetch1::fetchLine(), CopyEngine::CopyEngineChannel::fetchNextAddr(), MipsISA::ISA::filterCP0Write(), UFSHostDevice::finalUTP(), CxxConfigManager::findObject(), CxxConfigManager::findObjectParams(), BaseXBar::findPort(), Minor::LSQ::findResponse(), RandomRepl::findVictim(), LRU::findVictim(), SnoopFilter::finishRequest(), DefaultFetch< Impl >::finishTranslation(), AlphaSystem::fixFuncEventAddr(), AlphaISA::TLB::flushAddr(), X86ISA::TLB::flushAll(), AlphaISA::TLB::flushAll(), RiscvISA::TLB::flushAll(), MipsISA::TLB::flushAll(), PowerISA::TLB::flushAll(), ArmISA::TLB::flushAllNs(), ArmISA::TLB::flushAllSecurity(), ArmISA::TLB::flushAsid(), BaseKvmCPU::flushCoalescedMMIO(), ArmISA::TLB::flushMva(), ArmISA::TLB::flushMvaAsid(), X86ISA::TLB::flushNonGlobal(), AlphaISA::TLB::flushProcesses(), Minor::LSQ::StoreBuffer::forwardStoreData(), CoherentXBar::forwardTiming(), FullO3CPU< Impl >::FullO3CPU(), Cache::functionalAccess(), RubySystem::functionalRead(), RubySystem::functionalWrite(), GarnetSyntheticTraffic::GarnetSyntheticTraffic(), Pl011::generateInterrupt(), Pl050::generateInterrupt(), Pl111::generateInterrupt(), UFSHostDevice::generateInterrupt(), Iob::generateIpi(), GarnetSyntheticTraffic::generatePkt(), DefaultCommit< Impl >::generateTCEvent(), DefaultCommit< Impl >::generateTrapEvent(), X86ISA::RegOpBase::genFlags(), RubyPort::PioSlavePort::getAddrRanges(), GpuDispatcher::getAddrRanges(), BasicPioDevice::getAddrRanges(), BaseXBar::getAddrRanges(), X86ISA::PageTableOps::getBasePtr(), CheckTable::getCheck(), StubSlavePortHandler::getExternalPort(), DefaultCommit< Impl >::getInsts(), MipsISA::Interrupts::getInterrupt(), AlphaISA::Interrupts::getInterrupt(), X86ISA::Interrupts::getInterrupt(), ExternalMaster::getMasterPort(), X86KvmCPU::getMsrIntersection(), LinearGen::getNextPacket(), RandomGen::getNextPacket(), DramGen::getNextPacket(), DramRotGen::getNextPacket(), TraceGen::getNextPacket(), QueuedPrefetcher::getPacket(), IGbE::TxDescCache::getPacketData(), IGbE::TxDescCache::getPacketSize(), PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), AlphaISA::RemoteGDB::AlphaGdbRegCache::getRegs(), MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), RiscvISA::RemoteGDB::RiscvGdbRegCache::getRegs(), ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), X86ISA::RemoteGDB::X86GdbRegCache::getRegs(), SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), X86ISA::RemoteGDB::AMD64GdbRegCache::getRegs(), ArmISA::TLB::getResultTe(), ExternalSlave::getSlavePort(), ListOperand::getSrcOperand(), ArmISA::TLB::getTE(), X86ISA::I8259::getVector(), O3ThreadContext< class >::halt(), FullO3CPU< Impl >::haltContext(), ArmISA::PMU::handleEvent(), Cache::handleFill(), X86ISA::GpuTLB::handleFuncTranslationReturn(), DefaultCommit< Impl >::handleInterrupt(), BaseKvmCPU::handleKvmExit(), X86KvmCPU::handleKvmExitIO(), MipsISA::handleLockedRead(), RiscvISA::handleLockedRead(), ArmISA::handleLockedRead(), ArmISA::handleLockedSnoop(), RiscvISA::handleLockedSnoop(), ArmISA::handleLockedSnoopHit(), MipsISA::handleLockedWrite(), RiscvISA::handleLockedWrite(), ArmISA::handleLockedWrite(), Minor::Execute::handleMemResponse(), Checker< Impl >::handlePendingInt(), DmaPort::handleResp(), MSHR::handleSnoop(), Cache::handleSnoop(), Minor::Fetch1::handleTLBResponse(), X86ISA::GpuTLB::handleTranslationReturn(), BaseRemoteGDB::HardBreakpoint::HardBreakpoint(), IGbE::TxDescCache::headerComplete(), RubyPort::MemSlavePort::hitCallback(), RubyDirectedTester::hitCallback(), RubyTester::hitCallback(), Sequencer::hitCallback(), GPUCoalescer::hitCallback(), TraceCPU::icacheRetryRecvd(), Terminal::in(), OutputUnit::increment_credit(), CopyEngine::CopyEngineChannel::inDrain(), MemChecker::ByteTracker::inExpectedData(), StoreSet::init(), LSQUnit< Impl >::init(), MemDepUnit< MemDepPred, Impl >::init(), BaseRegOperand::init(), TraceCPU::init(), TrafficGen::init(), DistEtherLink::init(), HsailCode::init(), ImmOperand< T >::init(), CoherentXBar::init(), TraceCPU::FixedRetryGen::init(), ListOperand::init(), TraceCPU::ElasticDataGen::init(), BaseRegOperand::init_from_vect(), FlashDevice::initializeFlash(), Prefetcher::initializeStream(), SeriesRequestGenerator::initiate(), InvalidateGenerator::initiate(), Check::initiate(), GPUDynInst::initiateAcc(), Check::initiateAction(), Check::initiateCheck(), FetchUnit::initiateFetch(), Check::initiateFlush(), Check::initiatePrefetch(), PseudoInst::initParam(), LinuxArmSystem::initState(), MultiLevelPageTable< ISAOps >::initState(), TrafficGen::initState(), CxxConfigManager::initState(), System::initState(), BaseDynInst< Impl >::initVars(), AlphaISA::TLB::insert(), QueuedPrefetcher::insert(), MemDepUnit< MemDepPred, Impl >::insert(), SparcISA::TLB::insert(), InstructionQueue< Impl >::insert(), ArmISA::TLB::insert(), Minor::LSQ::StoreBuffer::insert(), RiscvISA::TLB::insertAt(), MipsISA::TLB::insertAt(), MemDepUnit< MemDepPred, Impl >::insertBarrier(), BaseRemoteGDB::insertHardBreak(), ROB< Impl >::insertInst(), GPUCoalescer::insertKernel(), LSQUnit< Impl >::insertLoad(), MemDepUnit< MemDepPred, Impl >::insertNonSpec(), InstructionQueue< Impl >::insertNonSpec(), GPUCoalescer::insertRequest(), StoreSet::insertStore(), LSQUnit< Impl >::insertStore(), ArmISA::TableWalker::insertTableEntry(), FullO3CPU< Impl >::insertThread(), CxxConfigManager::instantiate(), InstructionQueue< Impl >::InstructionQueue(), DefaultIEW< Impl >::instToCommit(), MipsISA::Interrupts::interruptsPending(), IdeDisk::intrClear(), Uart8250::IntrEvent::IntrEvent(), IdeDisk::intrPost(), X86ISA::GpuTLB::invalidateAll(), X86ISA::GpuTLB::invalidateNonGlobal(), VIPERCoalescer::invL1(), FaultBase::invoke(), X86ISA::X86FaultBase::invoke(), MipsISA::MipsFaultBase::invoke(), MipsISA::ResetFault::invoke(), ArmISA::ArmFault::invoke(), MipsISA::TlbFault< TlbInvalidFault >::invoke(), X86ISA::InitInterrupt::invoke(), ArmISA::AbortFault< T >::invoke(), X86ISA::StartupInterrupt::invoke(), ArmISA::FlushPipe::invoke(), ArmISA::ArmSev::invoke(), ArmISA::ArmFault::invoke64(), ioctlFunc(), LSQ< Impl >::isDrained(), Minor::Pipeline::isDrained(), DefaultIEW< Impl >::isDrained(), FullO3CPU< Impl >::isDrained(), Minor::Fetch1::isDrained(), AbstractCacheEntry::isLocked(), CacheMemory::isLocked(), MemDepUnit< MemDepPred, Impl >::issue(), Minor::Execute::issue(), StoreSet::issued(), DMASequencer::issueNext(), Prefetcher::issueNextPrefetch(), X86ISA::GpuTLB::issueTLBLookup(), CacheMemory::isTagPresent(), AlphaISA::kernel_pte_lookup(), PciVirtIO::kick(), BaseArmKvmCPU::kvmRun(), X86KvmCPU::kvmRun(), ArmKvmCPU::kvmRun(), BaseKvmCPU::kvmRun(), X86KvmCPU::kvmRunDrain(), EtherSwitch::Interface::learnSenderAddr(), Terminal::listen(), VncServer::listen(), TapListener::listen(), GDBListener::listen(), ElfObject::loadSomeSymbols(), SimObject::loadState(), PseudoInst::loadsymbol(), LocalBP::LocalBP(), IndirectPredictor::lookup(), DirectoryMemory::lookup(), RiscvISA::TLB::lookup(), LTAGE::lookup(), MipsISA::TLB::lookup(), LocalBP::lookup(), AlphaISA::TLB::lookup(), SparcISA::TLB::lookup(), PowerISA::TLB::lookup(), MultiLevelPageTable< ISAOps >::lookup(), ArmISA::TLB::lookup(), DefaultFetch< Impl >::lookupAndUpdateNextPC(), EtherSwitch::Interface::lookupDestPort(), X86ISA::GpuTLB::lookupIt(), SnoopFilter::lookupRequest(), SnoopFilter::lookupSnoop(), LTAGE::loopUpdate(), X86ISA::I8259::lowerInterruptPin(), LSQ< Impl >::LSQ(), LTAGE::LTAGE(), PseudoInst::m5checkpoint(), PseudoInst::m5exit(), PseudoInst::m5fail(), X86ISA::m5PageFault(), X86ISA::m5Syscall(), DMASequencer::makeRequest(), VIPERCoalescer::makeRequest(), Sequencer::makeRequest(), UFSHostDevice::manageReadTransfer(), UFSHostDevice::manageWriteTransfer(), MultiLevelPageTable< ISAOps >::map(), FuncPageTable::map(), DefaultCommit< Impl >::markCompletedInsts(), BaseDynInst< Impl >::markSrcRegReady(), Minor::Scoreboard::markupInstDests(), ArmISA::TableWalker::memAttrs(), ArmISA::TableWalker::memAttrsAArch64(), ArmISA::TableWalker::memAttrsLPAE(), MemDepUnit< MemDepPred, Impl >::MemDepEntry::MemDepEntry(), MemDepUnit< MemDepPred, Impl >::MemDepUnit(), RubyPort::MemMasterPort::MemMasterPort(), RubyPort::MemSlavePort::MemSlavePort(), RubySystem::memWriteback(), MinorCPU::memWriteback(), Shader::mmap(), X86ISA::Decoder::moreBytes(), MemDepUnit< MemDepPred, Impl >::moveToReady(), Serializable::ScopedCheckpointSection::nameOut(), Trace::NativeTrace::NativeTrace(), Minor::LSQ::needsToTick(), TraceCPU::FixedRetryGen::nextExecute(), LinearGen::nextPacketTick(), RandomGen::nextPacketTick(), TraceGen::nextPacketTick(), MemDepUnit< MemDepPred, Impl >::nonSpecInstReady(), QueuedPrefetcher::notify(), GpuDispatcher::notifyWgCompl(), IGbE::TxDescCache::nullCallback(), LSQUnit< Impl >::numFreeLoadEntries(), LSQUnit< Impl >::numFreeStoreEntries(), Prefetcher::observeMiss(), Prefetcher::observePfHit(), Prefetcher::observePfMiss(), BaseXBar::Layer< SrcType, DstType >::occupyLayer(), NoMaliGpu::onInterrupt(), ArmKvmCPU::onKvmExitHypercall(), VirtQueue::onNotify(), VirtIODeviceBase::onNotify(), VirtIOConsole::TermTransQueue::onNotifyDescriptor(), VirtIO9PBase::FSQueue::onNotifyDescriptor(), VirtIOBlock::RequestQueue::onNotifyDescriptor(), NoMaliGpu::onReset(), PerfectSwitch::operateMessageBuffer(), Throttle::operateVnet(), Terminal::out(), DistIface::packetOut(), X86ISA::Walker::WalkerState::pageFault(), TrafficGen::parseConfig(), CxxConfigManager::parsePort(), CheckerThreadContext< TC >::pcState(), CheckerCPU::pcState(), StridePrefetcher::pcTableHit(), StridePrefetcher::pcTableVictim(), MessageBuffer::peek(), VoltageDomain::perfLevel(), DVFSHandler::perfLevel(), SrcClockDomain::perfLevel(), Check::performCallback(), X86ISA::X86StaticInst::pick(), Check::pickInitiatingNode(), RubyPort::PioMasterPort::PioMasterPort(), RubyPort::PioSlavePort::PioSlavePort(), DefaultFetch< Impl >::pipelineIcacheAccesses(), IGbE::RxDescCache::pktComplete(), IGbE::TxDescCache::pktComplete(), IGbE::RxDescCache::pktSplitDone(), ArmISA::PMU::PMU(), Wavefront::popFromReconvergenceStack(), Minor::LSQ::popResponse(), IntrControl::post(), MipsISA::Interrupts::post(), AlphaISA::Interrupts::post(), ArmISA::Interrupts::post(), SparcISA::Interrupts::post(), TsunamiCChip::postDRIR(), PciHost::DeviceInterface::postInt(), IGbE::postInterrupt(), MaltaCChip::postIntr(), MaltaIO::postIntr(), VGic::postMaintInt(), TsunamiIO::postPIC(), TsunamiCChip::postRTC(), VGic::postVInt(), DRAMCtrl::Rank::powerDownSleep(), DRAMCtrl::prechargeBank(), DrainManager::preCheckpointRestore(), BPredUnit::predict(), LTAGE::predict(), Minor::Fetch2::predictBranch(), BaseSimpleCPU::preExecute(), DRAMCtrl::printQs(), TraceCPU::ElasticDataGen::printReadyList(), StackDistCalc::printStack(), ArmISA::TLB::printTlb(), RiscvISA::TLB::probeEntry(), MipsISA::TLB::probeEntry(), PowerISA::TLB::probeEntry(), SkipFuncEvent::process(), EndQuiesceEvent::process(), MC146818::RTCEvent::process(), LinuxAlphaSystem::PrintThreadInfo::process(), LinuxMipsSystem::PrintThreadInfo::process(), MC146818::RTCTickEvent::process(), Uart8250::IntrEvent::process(), ArmISA::Decoder::process(), TLBCoalescer::IssueProbeEvent::process(), TLBCoalescer::CleanupEvent::process(), BaseRemoteGDB::HardBreakpoint::process(), ComputeUnit::DataPort::MemReqEvent::process(), ComputeUnit::DataPort::MemRespEvent::process(), DefaultFetch< Impl >::processCacheCompletion(), IGbE::TxDescCache::processContextDesc(), X86ISA::PS2Mouse::processData(), X86ISA::PS2Keyboard::processData(), BrigObject::processDirectives(), FetchUnit::processFetchReturn(), InstructionQueue< Impl >::processFUCompletion(), SparcISA::ISA::processHSTickCompare(), FullO3CPU< Impl >::processInterrupts(), DRAMCtrl::processNextReqEvent(), DRAMCtrl::Rank::processPowerEvent(), DRAMCtrl::Rank::processPrechargeEvent(), DRAMCtrl::Rank::processRefreshEvent(), DRAMCtrl::processRespondEvent(), Minor::Fetch1::processResponse(), BaseCache::CacheSlavePort::processSendRetry(), SparcISA::ISA::processSTickCompare(), ArmISA::TableWalker::processWalk(), ArmISA::TableWalker::processWalkAArch64(), ArmISA::TableWalker::processWalkLPAE(), ArmISA::TableWalker::processWalkWrapper(), VirtQueue::produceDescriptor(), DefaultFetch< Impl >::profileStall(), Cache::promoteWholeLineWrites(), PseudoInst::pseudoInst(), EtherSwitch::Interface::PortFifo::push(), Serializable::ScopedCheckpointSection::pushName(), DistIface::RecvScheduler::pushPacket(), Minor::LSQ::pushRequest(), HDLcd::pxlFrameDone(), HDLcd::pxlUnderrun(), HDLcd::pxlVSyncBegin(), HDLcd::pxlVSyncEnd(), ThreadContext::quiesce(), PseudoInst::quiesce(), PseudoInst::quiesceCycles(), PseudoInst::quiesceNs(), PseudoInst::quiesceSkip(), ThreadContext::quiesceTick(), PseudoInst::quiesceTime(), IGbE::radvProcess(), ArmISA::PMU::raiseInterrupt(), X86ISA::I8259::raiseInterruptPin(), IGbE::rdtrProcess(), PciVirtIO::read(), SimpleDisk::read(), MmDisk::read(), Pl011::read(), AmbaFake::read(), X86ISA::Speaker::read(), VectorRegisterFile::read(), IsaFake::read(), TsunamiPChip::read(), RawDiskImage::read(), X86ISA::I8259::read(), TsunamiCChip::read(), Uart8250::read(), HDLcd::read(), Gicv2m::read(), AlphaBackdoor::read(), PL031::read(), Sp804::Timer::read(), TsunamiIO::read(), EnergyCtrl::read(), CowDiskImage::read(), CpuLocalTimer::Timer::read(), VirtIOBlock::read(), Sp804::read(), GpuDispatcher::read(), Pl050::read(), RealViewCtrl::read(), CpuLocalTimer::read(), VirtDescriptor::read(), CopyEngine::read(), RealViewOsc::read(), X86ISA::Interrupts::read(), VncServer::read(), BaseRemoteGDB::read(), Sinic::Device::read(), GenericPciHost::read(), GenericTimerMem::read(), NSGigE::read(), Pl111::read(), LSQUnit< Impl >::read(), IGbE::read(), GPUCoalescer::readCallback(), UFSHostDevice::readCallback(), PhysRegFile::readCCReg(), SimpleThread::readCCReg(), IdeDisk::readCommand(), DRAMSim2::readComplete(), IdeController::readConfig(), PciDevice::readConfig(), IdeDisk::readControl(), CopyEngine::CopyEngineChannel::readCopyBytes(), CopyEngine::CopyEngineChannel::readCopyBytesComplete(), Pl390::readCpu(), VGic::readCtrl(), UFSHostDevice::readDevice(), Pl390::readDistributor(), UFSHostDevice::readDone(), PseudoInst::readfile(), PhysRegFile::readFloatReg(), SimpleThread::readFloatReg(), PhysRegFile::readFloatRegBits(), SimpleThread::readFloatRegBits(), Pl111::readFramebuffer(), DefaultRename< Impl >::readFreeEntries(), UFSHostDevice::readGarbage(), AmbaDevice::readId(), PhysRegFile::readIntReg(), SimpleThread::readIntReg(), RiscvISA::ISA::readMiscReg(), MipsISA::ISA::readMiscReg(), ArmISA::PMU::readMiscReg(), ArmISA::ISA::readMiscReg(), SparcISA::ISA::readMiscReg(), RiscvISA::ISA::readMiscRegNoEffect(), MipsISA::ISA::readMiscRegNoEffect(), SparcISA::ISA::readMiscRegNoEffect(), TraceCPU::ElasticDataGen::readNextWindow(), DRAMCtrl::readQueueFull(), NoMaliGpu::readReg(), X86ISA::I82094AA::readReg(), X86ISA::Cmos::readRegister(), VGic::readVCpu(), Wavefront::ready(), DistIface::readyToCkpt(), DistIface::readyToExit(), ComputeUnit::ReadyWorkgroup(), MessageBuffer::reanalyzeAllMessages(), MessageBuffer::reanalyzeMessages(), Iob::receiveDeviceInterrupt(), Iob::receiveJBusInterrupt(), CacheMemory::recordCacheContents(), IndirectPredictor::recordIndirect(), DirectoryMemory::recordRequestType(), DMASequencer::recordRequestType(), Sequencer::recordRequestType(), CacheMemory::recordRequestType(), GPUCoalescer::recordRequestType(), IndirectPredictor::recordTarget(), BaseRemoteGDB::recv(), StubSlavePort::recvAtomic(), NoncoherentXBar::recvAtomic(), CoherentXBar::recvAtomic(), Cache::recvAtomic(), DRAMCtrl::recvAtomic(), AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(), CoherentXBar::recvAtomicSnoop(), VncServer::recvCutText(), RubyPort::MemSlavePort::recvFunctional(), TLBCoalescer::CpuSidePort::recvFunctional(), NoncoherentXBar::recvFunctional(), MemCheckerMonitor::recvFunctional(), X86ISA::GpuTLB::CpuSidePort::recvFunctional(), CoherentXBar::recvFunctional(), AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(), MemCheckerMonitor::recvFunctionalSnoop(), CoherentXBar::recvFunctionalSnoop(), TCPIface::recvHeader(), VncServer::recvKeyboardInput(), X86ISA::Interrupts::recvMessage(), EtherSwitch::Interface::recvPacket(), Sinic::Device::recvPacket(), NSGigE::recvPacket(), VncServer::recvPointerInput(), BaseXBar::recvRangeChange(), EtherTapStub::recvReal(), TrafficGen::recvReqRetry(), Minor::Fetch1::recvReqRetry(), ComputeUnit::DataPort::recvReqRetry(), ComputeUnit::SQCPort::recvReqRetry(), ComputeUnit::DTLBPort::recvReqRetry(), BaseKvmCPU::KVMCpuPort::recvReqRetry(), ComputeUnit::ITLBPort::recvReqRetry(), ComputeUnit::LDSPort::recvReqRetry(), Minor::LSQ::recvReqRetry(), X86ISA::Interrupts::recvResponse(), DRAMSim2::recvRespRetry(), MemTest::recvRetry(), LSQUnit< Impl >::recvRetry(), EtherTapBase::recvSimulated(), RubyPort::MemSlavePort::recvTimingReq(), HMCController::recvTimingReq(), TLBCoalescer::CpuSidePort::recvTimingReq(), NoncoherentXBar::recvTimingReq(), SerialLink::SerialLinkSlavePort::recvTimingReq(), Bridge::BridgeSlavePort::recvTimingReq(), DRAMSim2::recvTimingReq(), MemCheckerMonitor::recvTimingReq(), CommMonitor::recvTimingReq(), X86ISA::GpuTLB::CpuSidePort::recvTimingReq(), CoherentXBar::recvTimingReq(), Cache::recvTimingReq(), DRAMCtrl::recvTimingReq(), RubyPort::MemMasterPort::recvTimingResp(), RubyPort::PioMasterPort::recvTimingResp(), FullO3CPU< Impl >::IcachePort::recvTimingResp(), NoncoherentXBar::recvTimingResp(), TimingSimpleCPU::IcachePort::recvTimingResp(), MemCheckerMonitor::recvTimingResp(), TimingSimpleCPU::DcachePort::recvTimingResp(), CommMonitor::recvTimingResp(), CoherentXBar::recvTimingResp(), LSQ< Impl >::recvTimingResp(), SerialLink::SerialLinkMasterPort::recvTimingResp(), Bridge::BridgeMasterPort::recvTimingResp(), X86ISA::GpuTLB::MemSidePort::recvTimingResp(), Cache::recvTimingResp(), Minor::Fetch1::recvTimingResp(), ComputeUnit::DataPort::recvTimingResp(), ComputeUnit::DTLBPort::recvTimingResp(), BaseKvmCPU::KVMCpuPort::recvTimingResp(), ComputeUnit::ITLBPort::recvTimingResp(), Minor::LSQ::recvTimingResp(), CoherentXBar::recvTimingSnoopReq(), LSQ< Impl >::recvTimingSnoopReq(), Cache::recvTimingSnoopReq(), CoherentXBar::recvTimingSnoopResp(), Cache::recvTimingSnoopResp(), MessageBuffer::recycle(), PciHost::registerDevice(), MemDepUnit< MemDepPred, Impl >::regsReady(), BaseXBar::Layer< SrcType, DstType >::releaseLayer(), FlashDevice::remap(), MultiLevelPageTable< ISAOps >::remap(), FuncPageTable::remap(), PCEventQueue::remove(), DefaultRename< Impl >::removeFromHistory(), FullO3CPU< Impl >::removeFrontInst(), BaseRemoteGDB::removeHardBreak(), FullO3CPU< Impl >::removeInstsNotInROB(), FullO3CPU< Impl >::removeInstsUntil(), FullO3CPU< Impl >::removeThread(), SimpleRenameMap::rename(), DefaultRename< Impl >::rename(), DefaultRename< Impl >::renameDestRegs(), DefaultRename< Impl >::renameInsts(), DefaultRename< Impl >::renameSrcRegs(), DRAMCtrl::reorderQueue(), replaceUpgrade(), MemDepUnit< MemDepPred, Impl >::replay(), TsunamiCChip::reqIPI(), VncServer::requestFbUpdate(), UFSHostDevice::requestHandler(), X86ISA::I8259::requestInterrupt(), X86ISA::Interrupts::requestInterrupt(), InstructionQueue< Impl >::rescheduleMemInst(), NoMaliGpu::reset(), IGbE::DescCache< T >::reset(), PseudoInst::resetstats(), Sp804::Timer::restartCounter(), CpuLocalTimer::Timer::restartTimerCounter(), CpuLocalTimer::Timer::restartWatchdogCounter(), DrainManager::resume(), DmaReadFifo::resumeFillFunctional(), PL031::resyncMatch(), ROB< Impl >::retireHead(), EtherTapBase::retransmit(), PacketQueue::retry(), SerialLink::SerialLinkSlavePort::retryStalledReq(), Bridge::BridgeSlavePort::retryStalledReq(), ROB< Impl >::ROB(), PseudoInst::rpns(), MC146818::RTCEvent::RTCEvent(), RubyPort::ruby_eviction_callback(), RubyPort::ruby_hit_callback(), Sinic::Device::rxDmaDone(), NSGigE::rxDmaReadDone(), NSGigE::rxDmaWriteDone(), DistEtherLink::RxLink::rxDone(), Sinic::Device::rxFilter(), NSGigE::rxFilter(), Sinic::Device::rxKick(), NSGigE::rxKick(), NSGigE::rxReset(), IGbE::rxStateMachine(), VoltageDomain::sanitiseVoltages(), Cache::satisfyRequest(), TraceCPU::schedDcacheNext(), TraceCPU::schedDcacheNextEvent(), TraceCPU::schedIcacheNext(), BaseCache::CacheMasterPort::schedSendEvent(), PacketQueue::schedSendEvent(), PacketQueue::schedSendTiming(), PCEventQueue::schedule(), Uart8250::IntrEvent::scheduleIntr(), InstructionQueue< Impl >::scheduleNonSpec(), DRAMCtrl::Rank::schedulePowerEvent(), InstructionQueue< Impl >::scheduleReadyInsts(), DRAMCtrl::Rank::scheduleWakeUpEvent(), UFSHostDevice::UFSSCSIDevice::SCSICMDHandle(), UFSHostDevice::SCSIResume(), UFSHostDevice::SCSIStart(), EtherBus::send(), BaseRemoteGDB::send(), TCPIface::sendCmd(), DmaPort::sendDma(), TimingSimpleCPU::sendFetch(), VncServer::sendFrameBufferResized(), VncServer::sendFrameBufferUpdate(), MuxingKvmGic::sendInt(), Pl390::sendInt(), Cache::sendMSHRQueuePacket(), MuxingKvmGic::sendPPInt(), Pl390::sendPPInt(), ComputeUnit::sendRequest(), DRAMSim2::sendResponse(), VirtIO9PBase::sendRMsg(), VncServer::sendServerInit(), EtherTapBase::sendSimulated(), Minor::LSQ::sendStoreToStoreBuffer(), ComputeUnit::sendSyncRequest(), ComputeUnit::LDSPort::sendTimingReq(), Cache::sendWriteQueuePacket(), Pl011::serialize(), ArmISA::PMU::serialize(), HDLcd::serialize(), Sp804::Timer::serialize(), PL031::serialize(), CpuLocalTimer::Timer::serialize(), I2CBus::serialize(), VGic::serialize(), TrafficGen::serialize(), ArmISA::TLB::serialize(), ArmISA::ISA::serialize(), Pl390::serialize(), Pl111::serialize(), PhysicalMemory::serializeStore(), BaseKvmCPU::serializeThread(), SRegOperand::set(), DRegOperand::set(), CRegOperand::set(), ListOperand::set(), ROB< Impl >::setActiveThreads(), BaseCache::CacheSlavePort::setBlocked(), BaseCache::setBlocked(), NoMaliGpu::setCallback(), PhysRegFile::setCCReg(), SimpleThread::setCCReg(), MessageBuffer::setConsumer(), ArchTimer::setControl(), ArmISA::PMU::setControlReg(), ArmISA::PMU::setCounterTypeRegister(), VirtIODeviceBase::setDeviceStatus(), VncInput::setDirty(), Minor::Execute::setDrainState(), VncServer::setEncodings(), MipsISA::MipsFaultBase::setExceptionState(), PhysRegFile::setFloatReg(), SimpleThread::setFloatReg(), PhysRegFile::setFloatRegBits(), SimpleThread::setFloatRegBits(), SparcISA::ISA::setFSReg(), VirtIODeviceBase::setGuestFeatures(), PhysRegFile::setIntReg(), SimpleThread::setIntReg(), AbstractCacheEntry::setLocked(), CacheMemory::setLocked(), MipsISA::ISA::setMiscReg(), ArmISA::PMU::setMiscReg(), ArmISA::ISA::setMiscReg(), SparcISA::ISA::setMiscReg(), CheckerThreadContext< TC >::setMiscReg(), CheckerCPU::setMiscReg(), RiscvISA::ISA::setMiscRegNoEffect(), MipsISA::ISA::setMiscRegNoEffect(), ArmISA::ISA::setMiscRegNoEffect(), SparcISA::ISA::setMiscRegNoEffect(), CheckerThreadContext< TC >::setMiscRegNoEffect(), CheckerCPU::setMiscRegNoEffect(), CxxConfigManager::setParam(), CxxConfigManager::setParamVector(), VncServer::setPixelFormat(), Scoreboard::setReg(), MipsISA::ISA::setRegMask(), PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), AlphaISA::RemoteGDB::AlphaGdbRegCache::setRegs(), RiscvISA::RemoteGDB::RiscvGdbRegCache::setRegs(), ArmISA::RemoteGDB::AArch32GdbRegCache::setRegs(), X86ISA::RemoteGDB::X86GdbRegCache::setRegs(), ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), X86ISA::RemoteGDB::AMD64GdbRegCache::setRegs(), BaseRemoteGDB::setTempBreakpoint(), Intel8254Timer::Counter::CounterEvent::setTo(), BaseKvmCPU::setupCounters(), BaseSimpleCPU::setupFetchRequest(), Topology::shortest_path_to_node(), DrainManager::signalDrainDone(), MinorCPU::signalDrainDone(), X86ISA::I8259::signalInterrupt(), X86ISA::I82094AA::signalInterrupt(), X86ISA::X86StaticInst::signedPick(), DefaultDecode< Impl >::skidInsert(), DefaultIEW< Impl >::skidInsert(), DefaultRename< Impl >::skidInsert(), Pl390::softInt(), IndirectPredictor::squash(), StoreSet::squash(), BPredUnit::squash(), MemDepUnit< MemDepPred, Impl >::squash(), LSQUnit< Impl >::squash(), DefaultIEW< Impl >::squash(), DefaultDecode< Impl >::squash(), DefaultRename< Impl >::squash(), ROB< Impl >::squash(), InstructionQueue< Impl >::squash(), DefaultFetch< Impl >::squash(), LTAGE::squash(), DefaultCommit< Impl >::squashAfter(), DefaultIEW< Impl >::squashDueToBranch(), DefaultIEW< Impl >::squashDueToMemOrder(), DefaultFetch< Impl >::squashFromDecode(), DefaultCommit< Impl >::squashFromSquashAfter(), DefaultCommit< Impl >::squashFromTC(), DefaultCommit< Impl >::squashFromTrap(), FullO3CPU< Impl >::squashInstIt(), UFSHostDevice::UFSSCSIDevice::SSDReadDone(), UFSHostDevice::UFSSCSIDevice::SSDWriteDone(), UFSHostDevice::UFSSCSIDevice::SSDWriteStart(), AbstractController::stallBuffer(), MessageBuffer::stallMessage(), X86ISA::Walker::start(), IdeDisk::startCommand(), MemChecker::startRead(), ArmV8KvmCPU::startup(), RubySystem::startup(), MinorCPU::startup(), DistEtherLink::startup(), CxxConfigManager::startup(), DistIface::startup(), X86ISA::Walker::startWalkWrapper(), ComputeUnit::startWavefront(), MemChecker::startWrite(), Minor::LSQ::StoreBuffer::step(), Minor::Fetch1::stepQueues(), X86ISA::Walker::WalkerState::stepWalk(), LSQUnit< Impl >::storePostSend(), StoreSet::StoreSet(), O3ThreadContext< class >::suspend(), BaseKvmCPU::suspendContext(), MinorCPU::suspendContext(), AtomicSimpleCPU::suspendContext(), TimingSimpleCPU::suspendContext(), FullO3CPU< Impl >::suspendContext(), PseudoInst::switchcpu(), BaseKvmCPU::switchOut(), MinorCPU::switchOut(), FullO3CPU< Impl >::switchOut(), DefaultFetch< Impl >::switchToActive(), DefaultFetch< Impl >::switchToInactive(), FullO3CPU< Impl >::syscall(), IGbE::tadvProcess(), Minor::Execute::takeInterrupt(), BaseKvmCPU::takeOverFrom(), MinorCPU::takeOverFrom(), UFSHostDevice::taskStart(), TCPIface::TCPIface(), CacheMemory::testCacheAccess(), RubyPort::testDrainComplete(), AtomicSimpleCPU::threadSnoop(), AtomicSimpleCPU::tick(), MemTest::tick(), IGbE::tick(), DefaultDecode< Impl >::tick(), DefaultRename< Impl >::tick(), DefaultCommit< Impl >::tick(), BaseKvmCPU::tick(), DefaultIEW< Impl >::tick(), FullO3CPU< Impl >::tick(), DefaultFetch< Impl >::tick(), IGbE::tidvProcess(), CpuLocalTimer::Timer::timerAtZero(), Root::timeSync(), X86ISA::GpuTLB::tlbLookup(), PseudoInst::togglesync(), AbstractMemory::trackLoadLocked(), Sinic::Device::transferDone(), NSGigE::transferDone(), UFSHostDevice::transferDone(), UFSHostDevice::transferHandler(), UFSHostDevice::transferStart(), X86ISA::TLB::translate(), PageTableBase::translate(), X86ISA::GpuTLB::translate(), ArmISA::TLB::translateComplete(), AlphaISA::TLB::translateData(), SparcISA::TLB::translateData(), ArmISA::TLB::translateFs(), SparcISA::TLB::translateInst(), PowerISA::TLB::translateInst(), X86ISA::TLB::translateInt(), X86ISA::GpuTLB::translateInt(), X86ISA::GpuTLB::translationReturn(), EtherLink::Link::transmit(), DistEtherLink::TxLink::transmit(), EtherSwitch::Interface::transmit(), Sinic::Device::transmit(), NSGigE::transmit(), BaseRemoteGDB::trap(), CacheMemory::tryCacheAccess(), AtomicSimpleCPU::tryCompleteDrain(), TimingSimpleCPU::tryCompleteDrain(), DrainManager::tryDrain(), FullO3CPU< Impl >::tryDrain(), BaseKvmCPU::tryDrain(), TraceCPU::FixedRetryGen::tryNext(), Minor::Execute::tryPCEvents(), VirtIOConsole::TermRecvQueue::trySend(), RubyPort::trySendRetries(), SerialLink::SerialLinkSlavePort::trySendTiming(), Bridge::BridgeSlavePort::trySendTiming(), SerialLink::SerialLinkMasterPort::trySendTiming(), Bridge::BridgeMasterPort::trySendTiming(), DmaPort::trySendTimingReq(), Minor::Execute::tryToBranch(), Minor::Fetch1::tryToSend(), Minor::LSQ::tryToSend(), Minor::Fetch1::tryToSendToTransfers(), Minor::LSQ::tryToSendToTransfers(), EtherLink::Link::txComplete(), Sinic::Device::txDmaDone(), NSGigE::txDmaReadDone(), NSGigE::txDmaWriteDone(), EtherBus::txDone(), EtherLink::Link::txDone(), Sinic::Device::txKick(), NSGigE::txKick(), NSGigE::txReset(), IGbE::txStateMachine(), IGbE::txWire(), UFSHostDevice::UFSHostDevice(), UFSHostDevice::UFSSCSIDevice::UFSSCSIDevice(), DefaultDecode< Impl >::unblock(), DefaultRename< Impl >::unblock(), DefaultIEW< Impl >::unblock(), LTAGE::uncondBranch(), UnifiedFreeList::UnifiedFreeList(), MultiLevelPageTable< ISAOps >::unmap(), FuncPageTable::unmap(), VGic::unPostMaintInt(), VGic::unPostVInt(), Pl011::unserialize(), ArmISA::PMU::unserialize(), HDLcd::unserialize(), Sp804::Timer::unserialize(), PL031::unserialize(), CpuLocalTimer::Timer::unserialize(), I2CBus::unserialize(), VGic::unserialize(), ArmISA::TLB::unserialize(), Pl390::unserialize(), ArmISA::ISA::unserialize(), Pl111::unserialize(), Event::unserialize(), PhysicalMemory::unserializeStore(), BaseKvmCPU::unserializeThread(), LTAGE::update(), LocalBP::update(), TrafficGen::update(), BPredUnit::update(), VirtDescriptor::update(), Minor::Execute::updateBranchData(), Minor::Fetch2::updateBranchPrediction(), DerivedClockDomain::updateClockPeriod(), ArmISA::PMU::updateCounter(), Minor::Fetch1::updateExpectedSeqNums(), DefaultFetch< Impl >::updateFetchStatus(), LTAGE::updateGHist(), LTAGE::updateHistories(), X86ISA::Interrupts::updateIntrInfo(), Pl390::updateIntState(), ArmV8KvmCPU::updateKvmState(), ArmKvmCPU::updateKvmState(), X86KvmCPU::updateKvmState(), ArmKvmCPU::updateKvmStateCore(), updateKvmStateFPUCommon(), ArmKvmCPU::updateKvmStateMisc(), X86KvmCPU::updateKvmStateMSRs(), ArmISA::TLB::updateMiscReg(), X86ISA::Decoder::updateNPC(), X86ISA::Decoder::updateOffsetState(), TLBCoalescer::updatePhysAddresses(), SnoopFilter::updateResponse(), SnoopFilter::updateSnoopForward(), SnoopFilter::updateSnoopResponse(), IdeDisk::updateState(), DefaultDecode< Impl >::updateStatus(), DefaultIEW< Impl >::updateStatus(), DefaultRename< Impl >::updateStatus(), DefaultCommit< Impl >::updateStatus(), ArmV8KvmCPU::updateThreadContext(), ArmKvmCPU::updateThreadContext(), X86KvmCPU::updateThreadContext(), updateThreadContextFPUCommon(), X86KvmCPU::updateThreadContextMSRs(), Checker< Impl >::validateExecution(), Checker< Impl >::verify(), StoreSet::violation(), MemDepUnit< MemDepPred, Impl >::violation(), VncServer::VncServer(), DVFSHandler::voltageAtPerfLevel(), X86ISA::vtophys(), SparcISA::vtophys(), AlphaISA::vtophys(), PseudoInst::wakeCPU(), FullO3CPU< Impl >::wakeCPU(), MemDepUnit< MemDepPred, Impl >::wakeDependents(), InstructionQueue< Impl >::wakeDependents(), DefaultFetch< Impl >::wakeFromQuiesce(), CrossbarSwitch::wakeup(), Throttle::wakeup(), Router::wakeup(), NetworkInterface::wakeup(), BaseSimpleCPU::wakeup(), BaseKvmCPU::wakeup(), MinorCPU::wakeup(), FullO3CPU< Impl >::wakeup(), Minor::Fetch1::wakeupFetch(), MinorCPU::wakeupOnEvent(), MultiLevelPageTable< ISAOps >::walk(), ArmISA::TableWalker::walk(), CpuLocalTimer::Timer::watchdogAtZero(), IGbE::DescCache< T >::wbComplete(), VIPERCoalescer::wbL1(), PseudoInst::workbegin(), PseudoInst::workend(), System::workItemEnd(), PciVirtIO::write(), MmDisk::write(), Pl011::write(), X86ISA::Speaker::write(), TsunamiPChip::write(), VectorRegisterFile::write(), IsaFake::write(), RawDiskImage::write(), X86ISA::I8259::write(), TsunamiCChip::write(), Uart8250::write(), HDLcd::write(), Gicv2m::write(), Sp804::Timer::write(), PL031::write(), TsunamiIO::write(), EnergyCtrl::write(), CowDiskImage::write(), CpuLocalTimer::Timer::write(), VirtIOBlock::write(), GpuDispatcher::write(), Pl050::write(), Sp804::write(), RealViewCtrl::write(), CpuLocalTimer::write(), CopyEngine::write(), RealViewOsc::write(), VirtDescriptor::write(), X86ISA::Interrupts::write(), BaseRemoteGDB::write(), VncServer::write(), X86ISA::I8042::write(), Sinic::Device::write(), GenericPciHost::write(), GenericTimerMem::write(), NSGigE::write(), Pl111::write(), LSQUnit< Impl >::write(), IGbE::write(), LSQUnit< Impl >::writeback(), IGbE::DescCache< T >::writeback(), IGbE::DescCache< T >::writeback1(), Cache::writebackBlk(), DefaultIEW< Impl >::writebackInsts(), LSQ< Impl >::writebackStores(), LSQUnit< Impl >::writebackStores(), GPUCoalescer::writeCallback(), IdeDisk::writeCommand(), DRAMSim2::writeComplete(), CopyEngine::CopyEngineChannel::writeCompletionStatus(), IdeController::writeConfig(), PciDevice::writeConfig(), IdeDisk::writeControl(), CopyEngine::CopyEngineChannel::writeCopyBytes(), CopyEngine::CopyEngineChannel::writeCopyBytesComplete(), Pl390::writeCpu(), VGic::writeCtrl(), X86ISA::I8042::writeData(), UFSHostDevice::writeDevice(), Pl390::writeDistributor(), UFSHostDevice::writeDone(), PseudoInst::writefile(), Iob::writeIob(), Iob::writeJBus(), IGbE::RxDescCache::writePacket(), DRAMCtrl::writeQueueFull(), NoMaliGpu::writeReg(), X86ISA::I82094AA::writeReg(), HDLcd::writeReg(), X86ISA::Cmos::writeRegister(), SparcISA::TLB::writeSfsr(), CopyEngine::CopyEngineChannel::writeStatusComplete(), SparcISA::TLB::writeTagAccess(), VGic::writeVCpu(), BaseDynInst< Impl >::~BaseDynInst(), FlashDevice::~FlashDevice(), MemDepUnit< MemDepPred, Impl >::MemDepEntry::~MemDepEntry(), and Serializable::ScopedCheckpointSection::~ScopedCheckpointSection().

#define DPRINTFN

(

...

)

do {} while (0)

Definition at line 216 of file trace.hh.

Referenced by Terminal::accept(), RiscvProcess::argsInit(), BaseRemoteGDB::attach(), Trace::NativeTrace::checkReg(), Terminal::detach(), BaseRemoteGDB::detach(), DumbTOD::DumbTOD(), SparcISA::TLB::dumpAll(), HsailISA::Call::MagicPrintLane(), HsailISA::Call::MagicPrintLane64(), HsailISA::Call::MagicPrintWF32(), HsailISA::Call::MagicPrintWF32ID(), HsailISA::Call::MagicPrintWF64(), HsailISA::Call::MagicPrintWFFloat(), HsailISA::Call::MagicPrintWFID64(), HsailISA::Call::MagicSimBreak(), MC146818::MC146818(), Linux::DebugPrintkEvent::process(), BreakPCEvent::process(), Terminal::read(), ComputeUnit::DTLBPort::recvTimingResp(), Event::trace(), and BaseRemoteGDB::write().

#define DPRINTFNR

(

...

)

do {} while (0)

Definition at line 217 of file trace.hh.

Referenced by BaseRemoteGDB::read(), and BaseRemoteGDB::write().

#define DPRINTFR

(

...

)

do {} while (0)

Definition at line 214 of file trace.hh.

Referenced by ElasticTrace::addCommittedInst(), ProbeManager::addListener(), ProbeManager::addPoint(), ElasticTrace::addSquashedInst(), AoutObject::AoutObject(), TraceCPU::ElasticDataGen::checkAndIssue(), EcoffObject::EcoffObject(), ElfObject::ElfObject(), TraceCPU::ElasticDataGen::execute(), ElasticTrace::fetchReqTrace(), RubyTester::hitCallback(), Sequencer::hitCallback(), TraceCPU::ElasticDataGen::HardwareResource::isAvailable(), Sequencer::issueRequest(), GPUCoalescer::issueRequest(), Linux::openSpecialFile(), osf_setsysinfoFunc(), TraceCPU::ElasticDataGen::HardwareResource::printOccupancy(), TraceCPU::ElasticDataGen::printReadyList(), RawObject::RawObject(), ElasticTrace::recordExecTick(), GPUCoalescer::recordMissLatency(), ElasticTrace::recordToCommTick(), TraceCPU::ElasticDataGen::HardwareResource::release(), ProbeManager::removeListener(), TraceCPU::ElasticDataGen::GraphNode::removeRegDep(), ElasticTrace::removeRegDepMapEntry(), TraceCPU::ElasticDataGen::GraphNode::removeRobDep(), sys_setsysinfoFunc(), SimpleTrace::traceCommit(), SimpleTrace::traceFetch(), ElfObject::tryFile(), ElasticTrace::updateRegDep(), ElasticTrace::writeDepTrace(), TraceCPU::ElasticDataGen::GraphNode::writeElementAsTrace(), and BaseO3DynInst< Impl >::~BaseO3DynInst().

#define DPRINTFS	(		x,
			...
	)		do {} while (0)

Definition at line 213 of file trace.hh.

Referenced by Minor::FUPipeline::findTiming(), Minor::LSQ::SingleDataRequest::finish(), Minor::LSQ::SplitDataRequest::finish(), Minor::FUPipeline::FUPipeline(), Minor::LSQ::SplitDataRequest::makeFragmentPackets(), Minor::LSQ::SplitDataRequest::makeFragmentRequests(), Minor::LSQ::SingleDataRequest::retireResponse(), Minor::LSQ::SplitDataRequest::retireResponse(), Minor::LSQ::SplitDataRequest::sendNextFragmentToTranslation(), Minor::LSQ::LSQRequest::setState(), and Minor::LSQ::SingleDataRequest::startAddrTranslation().

#define DTRACE

(

x

)

(false)

Definition at line 210 of file trace.hh.

Referenced by RiscvProcess::argsInit(), Minor::Scoreboard::canInstIssue(), Minor::Execute::commit(), DefaultCommit< Impl >::commitHead(), TimingSimpleCPU::completeIfetch(), TraceCPU::ElasticDataGen::completeMemAccess(), LSQUnit< Impl >::completeStore(), DefaultDecode< Impl >::decodeInsts(), EventQueue::deschedule(), VirtDescriptor::dump(), VirtQueue::dump(), VirtDescriptor::dumpChain(), VirtIO9PBase::dumpMsg(), Minor::Pipeline::evaluate(), Minor::Fetch2::evaluate(), TraceCPU::ElasticDataGen::execute(), DefaultFetch< Impl >::fetch(), Minor::FUPipeline::FUPipeline(), Minor::Fetch1::handleTLBResponse(), TraceCPU::ElasticDataGen::init(), Minor::Execute::issue(), Terminal::out(), IGbE::TxDescCache::pktComplete(), Linux::DebugPrintkEvent::process(), BaseRemoteGDB::read(), StubSlavePort::recvAtomic(), Minor::Fetch1::recvTimingResp(), EventQueue::reschedule(), Sinic::Device::rxKick(), NSGigE::rxKick(), EventQueue::schedule(), BaseKvmCPU::serializeThread(), DefaultRename< Impl >::sortInsts(), AtomicSimpleCPU::tick(), Sinic::Device::transmit(), NSGigE::transmit(), DrainManager::tryDrain(), IGbE::txWire(), DefaultIEW< Impl >::updateExeInstStats(), X86KvmCPU::updateKvmState(), ArmKvmCPU::updateKvmStateCore(), ArmKvmCPU::updateKvmStateMisc(), ArmKvmCPU::updateTCStateCore(), ArmKvmCPU::updateTCStateMisc(), X86KvmCPU::updateThreadContext(), BaseRemoteGDB::write(), and BaseO3DynInst< Impl >::~BaseO3DynInst().

Function Documentation

const std::string& name

(

)

Definition at line 49 of file trace.cc.

Referenced by TraceCPU::checkAndSchedExitEvent(), OutputDirectory::createSubdirectory(), AddrOperandBase::disassemble(), Event::dump(), ArmKvmCPU::dumpKvmStateCoProc(), FullO3CPU< Impl >::FullO3CPU(), StubSlavePortHandler::getExternalPort(), BrigObject::getFunction(), gethostnameFunc(), MSHR::handleSnoop(), CheckerCPU::init(), TraceCPU::init(), BaseRegOperand::initWithStrOffset(), OutputDirectory::open(), AddrOperandBase::parseAddr(), BrigObject::processDirectives(), ThreadContext::quiesce(), LabelMap::refLabel(), BaseKvmCPU::regStats(), LSQUnit< Impl >::regStats(), MemDepUnit< MemDepPred, Impl >::regStats(), DefaultDecode< Impl >::regStats(), Ticked::regStats(), InstructionQueue< Impl >::regStats(), MinorCPU::regStats(), BaseSimpleCPU::regStats(), DefaultIEW< Impl >::regStats(), DefaultRename< Impl >::regStats(), DefaultCommit< Impl >::regStats(), DefaultFetch< Impl >::regStats(), FullO3CPU< Impl >::regStats(), ROB< Impl >::regStats(), TraceCPU::regStats(), OutputDirectory::resolve(), CxxConfigManager::SimObjectResolver::resolveSimObject(), TimerTable::setDescription(), SparcISA::unameFunc(), unameFunc(), unameFunc32(), unameFunc64(), Event::unserialize(), and TraceCPU::updateNumOps().