base.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
 * All rights reserved.
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2003-2005 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Erik Hallnor
 *          Steve Reinhardt
 *          Ron Dreslinski
 */

#ifndef __MEM_CACHE_BASE_HH__
#define __MEM_CACHE_BASE_HH__

#include <algorithm>
#include <list>
#include <string>
#include <vector>

#include "base/misc.hh"
#include "base/statistics.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "debug/Cache.hh"
#include "debug/CachePort.hh"
#include "mem/cache/mshr_queue.hh"
#include "mem/cache/write_queue.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/qport.hh"
#include "mem/request.hh"
#include "params/BaseCache.hh"
#include "sim/eventq.hh"
#include "sim/full_system.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"

class BaseCache : public MemObject
{
  protected:
    enum MSHRQueueIndex {
        MSHRQueue_MSHRs,
        MSHRQueue_WriteBuffer
    };

  public:
    enum BlockedCause {
        Blocked_NoMSHRs = MSHRQueue_MSHRs,
        Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
        Blocked_NoTargets,
        NUM_BLOCKED_CAUSES
    };

  protected:

    class CacheMasterPort : public QueuedMasterPort
    {

      public:

        void schedSendEvent(Tick time)
        {
            DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
            reqQueue.schedSendEvent(time);
        }

      protected:

        CacheMasterPort(const std::string &_name, BaseCache *_cache,
                        ReqPacketQueue &_reqQueue,
                        SnoopRespPacketQueue &_snoopRespQueue) :
            QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
        { }

        virtual bool isSnooping() const { return true; }
    };

    class CacheSlavePort : public QueuedSlavePort
    {

      public:

        void setBlocked();

        void clearBlocked();

        bool isBlocked() const { return blocked; }

      protected:

        CacheSlavePort(const std::string &_name, BaseCache *_cache,
                       const std::string &_label);

        RespPacketQueue queue;

        bool blocked;

        bool mustSendRetry;

      private:

        void processSendRetry();

        EventWrapper<CacheSlavePort,
                     &CacheSlavePort::processSendRetry> sendRetryEvent;

    };

    CacheSlavePort *cpuSidePort;
    CacheMasterPort *memSidePort;

  protected:

    MSHRQueue mshrQueue;

    WriteQueue writeBuffer;

    void markInService(MSHR *mshr, bool pending_modified_resp)
    {
        bool wasFull = mshrQueue.isFull();
        mshrQueue.markInService(mshr, pending_modified_resp);

        if (wasFull && !mshrQueue.isFull()) {
            clearBlocked(Blocked_NoMSHRs);
        }
    }

    void markInService(WriteQueueEntry *entry)
    {
        bool wasFull = writeBuffer.isFull();
        writeBuffer.markInService(entry);

        if (wasFull && !writeBuffer.isFull()) {
            clearBlocked(Blocked_NoWBBuffers);
        }
    }

    virtual bool allocOnFill(MemCmd cmd) const = 0;

    virtual void memWriteback() = 0;
    virtual void memInvalidate() = 0;
    virtual bool isDirty() const = 0;

    bool inRange(Addr addr) const;

    const unsigned blkSize;

    const Cycles lookupLatency;

    const Cycles dataLatency;

    const Cycles forwardLatency;

    const Cycles fillLatency;

    const Cycles responseLatency;

    const int numTarget;

    bool forwardSnoops;

    const bool isReadOnly;

    uint8_t blocked;

    uint64_t order;

    Cycles blockedCycle;

    MSHR *noTargetMSHR;

    Counter missCount;

    const AddrRangeList addrRanges;

  public:
    System *system;

    // Statistics
    Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
    Stats::Formula demandHits;
    Stats::Formula overallHits;

    Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
    Stats::Formula demandMisses;
    Stats::Formula overallMisses;

    Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
    Stats::Formula demandMissLatency;
    Stats::Formula overallMissLatency;

    Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
    Stats::Formula demandAccesses;
    Stats::Formula overallAccesses;

    Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
    Stats::Formula demandMissRate;
    Stats::Formula overallMissRate;

    Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
    Stats::Formula demandAvgMissLatency;
    Stats::Formula overallAvgMissLatency;

    Stats::Vector blocked_cycles;
    Stats::Vector blocked_causes;

    Stats::Formula avg_blocked;

    Stats::Scalar unusedPrefetches;

    Stats::Vector writebacks;

    Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
    Stats::Formula demandMshrHits;
    Stats::Formula overallMshrHits;

    Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
    Stats::Formula demandMshrMisses;
    Stats::Formula overallMshrMisses;

    Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
    Stats::Formula overallMshrUncacheable;

    Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
    Stats::Formula demandMshrMissLatency;
    Stats::Formula overallMshrMissLatency;

    Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
    Stats::Formula overallMshrUncacheableLatency;

#if 0

    Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
    Stats::Formula demandMshrAccesses;
    Stats::Formula overallMshrAccesses;
#endif

    Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
    Stats::Formula demandMshrMissRate;
    Stats::Formula overallMshrMissRate;

    Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
    Stats::Formula demandAvgMshrMissLatency;
    Stats::Formula overallAvgMshrMissLatency;

    Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
    Stats::Formula overallAvgMshrUncacheableLatency;

    virtual void regStats();

  public:
    BaseCache(const BaseCacheParams *p, unsigned blk_size);
    ~BaseCache() {}

    virtual void init();

    virtual BaseMasterPort &getMasterPort(const std::string &if_name,
                                          PortID idx = InvalidPortID);
    virtual BaseSlavePort &getSlavePort(const std::string &if_name,
                                        PortID idx = InvalidPortID);

    unsigned
    getBlockSize() const
    {
        return blkSize;
    }

    const AddrRangeList &getAddrRanges() const { return addrRanges; }

    MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
    {
        MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
                                        pkt, time, order++,
                                        allocOnFill(pkt->cmd));

        if (mshrQueue.isFull()) {
            setBlocked((BlockedCause)MSHRQueue_MSHRs);
        }

        if (sched_send) {
            // schedule the send
            schedMemSideSendEvent(time);
        }

        return mshr;
    }

    void allocateWriteBuffer(PacketPtr pkt, Tick time)
    {
        // should only see writes or clean evicts here
        assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);

        Addr blk_addr = pkt->getBlockAddr(blkSize);

        WriteQueueEntry *wq_entry =
            writeBuffer.findMatch(blk_addr, pkt->isSecure());
        if (wq_entry && !wq_entry->inService) {
            DPRINTF(Cache, "Potential to merge writeback %s", pkt->print());
        }

        writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);

        if (writeBuffer.isFull()) {
            setBlocked((BlockedCause)MSHRQueue_WriteBuffer);
        }

        // schedule the send
        schedMemSideSendEvent(time);
    }

    bool isBlocked() const
    {
        return blocked != 0;
    }

    void setBlocked(BlockedCause cause)
    {
        uint8_t flag = 1 << cause;
        if (blocked == 0) {
            blocked_causes[cause]++;
            blockedCycle = curCycle();
            cpuSidePort->setBlocked();
        }
        blocked |= flag;
        DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
    }

    void clearBlocked(BlockedCause cause)
    {
        uint8_t flag = 1 << cause;
        blocked &= ~flag;
        DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
        if (blocked == 0) {
            blocked_cycles[cause] += curCycle() - blockedCycle;
            cpuSidePort->clearBlocked();
        }
    }

    void schedMemSideSendEvent(Tick time)
    {
        memSidePort->schedSendEvent(time);
    }

    virtual bool inCache(Addr addr, bool is_secure) const = 0;

    virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;

    void incMissCount(PacketPtr pkt)
    {
        assert(pkt->req->masterId() < system->maxMasters());
        misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
        pkt->req->incAccessDepth();
        if (missCount) {
            --missCount;
            if (missCount == 0)
                exitSimLoop("A cache reached the maximum miss count");
        }
    }
    void incHitCount(PacketPtr pkt)
    {
        assert(pkt->req->masterId() < system->maxMasters());
        hits[pkt->cmdToIndex()][pkt->req->masterId()]++;

    }

};

#endif //__MEM_CACHE_BASE_HH__