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gem5
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A cache master port is used for the memory-side port of the cache, and in addition to the basic timing port that only sends response packets through a transmit list, it also offers the ability to schedule and send request packets (requests & writebacks). More...
#include <base.hh>
Public Member Functions | |
| void | schedSendEvent (Tick time) |
| Schedule a send of a request packet (from the MSHR). More... | |
 Public Member Functions inherited from QueuedMasterPort | |
| QueuedMasterPort (const std::string &name, MemObject *owner, ReqPacketQueue &req_queue, SnoopRespPacketQueue &snoop_resp_queue, PortID id=InvalidPortID) | |
| Create a QueuedPort with a given name, owner, and a supplied implementation of two packet queues. More... | |
| virtual | ~QueuedMasterPort () |
| void | schedTimingReq (PacketPtr pkt, Tick when) |
| Schedule the sending of a timing request. More... | |
| void | schedTimingSnoopResp (PacketPtr pkt, Tick when, bool force_order=false) |
| Schedule the sending of a timing snoop response. More... | |
| bool | checkFunctional (PacketPtr pkt) |
| Check the list of buffered packets against the supplied functional request. More... | |
| Public Member Functions inherited from MasterPort | |
| MasterPort (const std::string &name, MemObject *owner, PortID id=InvalidPortID) | |
| Master port. More... | |
| virtual | ~MasterPort () |
| void | bind (BaseSlavePort &slave_port) |
| Bind this master port to a slave port. More... | |
| void | unbind () |
| Unbind this master port and the associated slave port. More... | |
| Tick | sendAtomic (PacketPtr pkt) |
| Send an atomic request packet, where the data is moved and the state is updated in zero time, without interleaving with other memory accesses. More... | |
| void | sendFunctional (PacketPtr pkt) |
| Send a functional request packet, where the data is instantly updated everywhere in the memory system, without affecting the current state of any block or moving the block. More... | |
| bool | sendTimingReq (PacketPtr pkt) |
| Attempt to send a timing request to the slave port by calling its corresponding receive function. More... | |
| bool | sendTimingSnoopResp (PacketPtr pkt) |
| Attempt to send a timing snoop response packet to the slave port by calling its corresponding receive function. More... | |
| virtual void | sendRetryResp () |
| Send a retry to the slave port that previously attempted a sendTimingResp to this master port and failed. More... | |
| AddrRangeList | getAddrRanges () const |
| Get the address ranges of the connected slave port. More... | |
| void | printAddr (Addr a) |
| Inject a PrintReq for the given address to print the state of that address throughout the memory system. More... | |
| Public Member Functions inherited from BaseMasterPort | |
| BaseSlavePort & | getSlavePort () const |
| bool | isConnected () const |
| Public Member Functions inherited from Port | |
| const std::string | name () const |
| Return port name (for DPRINTF). More... | |
| PortID | getId () const |
| Get the port id. More... | |
Protected Member Functions | |
| CacheMasterPort (const std::string &_name, BaseCache *_cache, ReqPacketQueue &_reqQueue, SnoopRespPacketQueue &_snoopRespQueue) | |
| virtual bool | isSnooping () const |
| Memory-side port always snoops. More... | |
| Protected Member Functions inherited from QueuedMasterPort | |
| void | recvReqRetry () |
| Called by the slave port if sendTimingReq was called on this master port (causing recvTimingReq to be called on the slave port) and was unsuccesful. More... | |
| void | recvRetrySnoopResp () |
| Called by the slave port if sendTimingSnoopResp was called on this master port (causing recvTimingSnoopResp to be called on the slave port) and was unsuccesful. More... | |
| Protected Member Functions inherited from MasterPort | |
| virtual Tick | recvAtomicSnoop (PacketPtr pkt) |
| Receive an atomic snoop request packet from the slave port. More... | |
| virtual void | recvFunctionalSnoop (PacketPtr pkt) |
| Receive a functional snoop request packet from the slave port. More... | |
| virtual bool | recvTimingResp (PacketPtr pkt)=0 |
| Receive a timing response from the slave port. More... | |
| virtual void | recvTimingSnoopReq (PacketPtr pkt) |
| Receive a timing snoop request from the slave port. More... | |
| virtual void | recvRangeChange () |
| Called to receive an address range change from the peer slave port. More... | |
| Protected Member Functions inherited from BaseMasterPort | |
| BaseMasterPort (const std::string &name, MemObject *owner, PortID id=InvalidPortID) | |
| virtual | ~BaseMasterPort () |
| Protected Member Functions inherited from Port | |
| Port (const std::string &_name, MemObject &_owner, PortID _id) | |
| Abstract base class for ports. More... | |
| virtual | ~Port () |
| Virtual destructor due to inheritance. More... | |
Additional Inherited Members | |
| Protected Attributes inherited from QueuedMasterPort | |
| ReqPacketQueue & | reqQueue |
| Packet queue used to store outgoing requests. More... | |
| SnoopRespPacketQueue & | snoopRespQueue |
| Packet queue used to store outgoing snoop responses. More... | |
| Protected Attributes inherited from BaseMasterPort | |
| BaseSlavePort * | _baseSlavePort |
| Protected Attributes inherited from Port | |
| const PortID | id |
| A numeric identifier to distinguish ports in a vector, and set to InvalidPortID in case this port is not part of a vector. More... | |
| MemObject & | owner |
| A reference to the MemObject that owns this port. More... | |
A cache master port is used for the memory-side port of the cache, and in addition to the basic timing port that only sends response packets through a transmit list, it also offers the ability to schedule and send request packets (requests & writebacks).
The send event is scheduled through schedSendEvent, and the sendDeferredPacket of the timing port is modified to consider both the transmit list and the requests from the MSHR.
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Schedule a send of a request packet (from the MSHR).
Note that we could already have a retry outstanding.
Definition at line 121 of file base.hh.
References DPRINTF, QueuedMasterPort::reqQueue, and PacketQueue::schedSendEvent().
Referenced by BaseCache::schedMemSideSendEvent().