gem5
|
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the three different level of transport functions. More...
#include <port.hh>
Public Member Functions | |
MasterPort (const std::string &name, MemObject *owner, PortID id=InvalidPortID) | |
Master port. More... | |
virtual | ~MasterPort () |
void | bind (BaseSlavePort &slave_port) |
Bind this master port to a slave port. More... | |
void | unbind () |
Unbind this master port and the associated slave port. More... | |
Tick | sendAtomic (PacketPtr pkt) |
Send an atomic request packet, where the data is moved and the state is updated in zero time, without interleaving with other memory accesses. More... | |
void | sendFunctional (PacketPtr pkt) |
Send a functional request packet, where the data is instantly updated everywhere in the memory system, without affecting the current state of any block or moving the block. More... | |
bool | sendTimingReq (PacketPtr pkt) |
Attempt to send a timing request to the slave port by calling its corresponding receive function. More... | |
bool | sendTimingSnoopResp (PacketPtr pkt) |
Attempt to send a timing snoop response packet to the slave port by calling its corresponding receive function. More... | |
virtual void | sendRetryResp () |
Send a retry to the slave port that previously attempted a sendTimingResp to this master port and failed. More... | |
virtual bool | isSnooping () const |
Determine if this master port is snooping or not. More... | |
AddrRangeList | getAddrRanges () const |
Get the address ranges of the connected slave port. More... | |
void | printAddr (Addr a) |
Inject a PrintReq for the given address to print the state of that address throughout the memory system. More... | |
![]() | |
BaseSlavePort & | getSlavePort () const |
bool | isConnected () const |
![]() | |
const std::string | name () const |
Return port name (for DPRINTF). More... | |
PortID | getId () const |
Get the port id. More... | |
Protected Member Functions | |
virtual Tick | recvAtomicSnoop (PacketPtr pkt) |
Receive an atomic snoop request packet from the slave port. More... | |
virtual void | recvFunctionalSnoop (PacketPtr pkt) |
Receive a functional snoop request packet from the slave port. More... | |
virtual bool | recvTimingResp (PacketPtr pkt)=0 |
Receive a timing response from the slave port. More... | |
virtual void | recvTimingSnoopReq (PacketPtr pkt) |
Receive a timing snoop request from the slave port. More... | |
virtual void | recvReqRetry ()=0 |
Called by the slave port if sendTimingReq was called on this master port (causing recvTimingReq to be called on the slave port) and was unsuccesful. More... | |
virtual void | recvRetrySnoopResp () |
Called by the slave port if sendTimingSnoopResp was called on this master port (causing recvTimingSnoopResp to be called on the slave port) and was unsuccesful. More... | |
virtual void | recvRangeChange () |
Called to receive an address range change from the peer slave port. More... | |
![]() | |
BaseMasterPort (const std::string &name, MemObject *owner, PortID id=InvalidPortID) | |
virtual | ~BaseMasterPort () |
![]() | |
Port (const std::string &_name, MemObject &_owner, PortID _id) | |
Abstract base class for ports. More... | |
virtual | ~Port () |
Virtual destructor due to inheritance. More... | |
Private Attributes | |
SlavePort * | _slavePort |
Friends | |
class | SlavePort |
Additional Inherited Members | |
![]() | |
BaseSlavePort * | _baseSlavePort |
![]() | |
const PortID | id |
A numeric identifier to distinguish ports in a vector, and set to InvalidPortID in case this port is not part of a vector. More... | |
MemObject & | owner |
A reference to the MemObject that owns this port. More... | |
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the three different level of transport functions.
In addition to the basic functionality of sending packets, it also has functions to receive range changes or determine if the port is snooping or not.
MasterPort::MasterPort | ( | const std::string & | name, |
MemObject * | owner, | ||
PortID | id = InvalidPortID |
||
) |
|
virtual |
Bind this master port to a slave port.
This also does the mirror action and binds the slave port to the master port.
Implements BaseMasterPort.
Definition at line 128 of file port.cc.
References BaseMasterPort::_baseSlavePort, _slavePort, SlavePort::bind(), fatal, and Port::name().
Referenced by TraceCPU::takeOverFrom().
AddrRangeList MasterPort::getAddrRanges | ( | ) | const |
Get the address ranges of the connected slave port.
Definition at line 160 of file port.cc.
References _slavePort, and SlavePort::getAddrRanges().
Referenced by MemCheckerMonitor::getAddrRanges(), and CommMonitor::getAddrRanges().
|
inlinevirtual |
Determine if this master port is snooping or not.
The default implementation returns false and thus tells the neighbour we are not snooping. Any master port that wants to receive snoop requests (e.g. a cache connected to a bus) has to override this function.
Reimplemented in TraceCPU::DcachePort, TimingSimpleCPU::DcachePort, FullO3CPU< Impl >::DcachePort, CoherentXBar::CoherentXBarMasterPort, CommMonitor::MonitorMasterPort, AtomicSimpleCPU::AtomicCPUDPort, AddrMapper::MapperMasterPort, BaseCache::CacheMasterPort, MemCheckerMonitor::MonitorMasterPort, and Minor::LSQ::DcachePort.
Definition at line 254 of file port.hh.
Referenced by SlavePort::isSnooping().
void MasterPort::printAddr | ( | Addr | a | ) |
Inject a PrintReq for the given address to print the state of that address throughout the memory system.
For debugging.
Definition at line 200 of file port.cc.
References Request::funcMasterId, MemCmd::PrintReq, Packet::senderState, and sendFunctional().
Referenced by GarnetSyntheticTraffic::printAddr(), AtomicSimpleCPU::printAddr(), and TimingSimpleCPU::printAddr().
Receive an atomic snoop request packet from the slave port.
Reimplemented in TrafficGen::TrafficGenPort, CoherentXBar::CoherentXBarMasterPort, AtomicSimpleCPU::AtomicCPUDPort, CommMonitor::MonitorMasterPort, AddrMapper::MapperMasterPort, MemTest::CpuPort, and MemCheckerMonitor::MonitorMasterPort.
Definition at line 271 of file port.hh.
References Port::name(), and panic.
Referenced by SlavePort::sendAtomicSnoop().
|
inlineprotectedvirtual |
Receive a functional snoop request packet from the slave port.
Reimplemented in TraceCPU::DcachePort, TimingSimpleCPU::DcachePort, CoherentXBar::CoherentXBarMasterPort, TrafficGen::TrafficGenPort, FullO3CPU< Impl >::DcachePort, AtomicSimpleCPU::AtomicCPUDPort, CommMonitor::MonitorMasterPort, AddrMapper::MapperMasterPort, MemTest::CpuPort, Minor::LSQ::DcachePort, and MemCheckerMonitor::MonitorMasterPort.
Definition at line 280 of file port.hh.
References Port::name(), and panic.
Referenced by SlavePort::sendFunctionalSnoop().
|
inlineprotectedvirtual |
Called to receive an address range change from the peer slave port.
The default implementation ignores the change and does nothing. Override this function in a derived class if the owner needs to be aware of the address ranges, e.g. in an interconnect component like a bus.
Reimplemented in ComputeUnit::LDSPort, ComputeUnit::ITLBPort, ComputeUnit::DTLBPort, ComputeUnit::SQCPort, ComputeUnit::DataPort, X86ISA::GpuTLB::MemSidePort, TLBCoalescer::MemSidePort, CoherentXBar::CoherentXBarMasterPort, NoncoherentXBar::NoncoherentXBarMasterPort, CommMonitor::MonitorMasterPort, GpuDispatcher::TLBPort, AddrMapper::MapperMasterPort, MemCheckerMonitor::MonitorMasterPort, RubyPort::PioMasterPort, and RubyPort::MemMasterPort.
Definition at line 322 of file port.hh.
Referenced by SlavePort::sendRangeChange().
|
protectedpure virtual |
Called by the slave port if sendTimingReq was called on this master port (causing recvTimingReq to be called on the slave port) and was unsuccesful.
Implemented in ComputeUnit::LDSPort, ComputeUnit::ITLBPort, BaseKvmCPU::KVMCpuPort, ComputeUnit::DTLBPort, ComputeUnit::SQCPort, ComputeUnit::DataPort, X86ISA::GpuTLB::MemSidePort, Bridge::BridgeMasterPort, TraceCPU::DcachePort, SerialLink::SerialLinkMasterPort, TraceCPU::IcachePort, CoherentXBar::SnoopRespPort, TimingSimpleCPU::DcachePort, CoherentXBar::CoherentXBarMasterPort, TLBCoalescer::MemSidePort, TimingSimpleCPU::IcachePort, FullO3CPU< Impl >::DcachePort, TrafficGen::TrafficGenPort, CommMonitor::MonitorMasterPort, NoncoherentXBar::NoncoherentXBarMasterPort, FullO3CPU< Impl >::IcachePort, AddrMapper::MapperMasterPort, GpuDispatcher::TLBPort, MemCheckerMonitor::MonitorMasterPort, AtomicSimpleCPU::AtomicCPUPort, DmaPort, QueuedMasterPort, MemTest::CpuPort, GarnetSyntheticTraffic::CpuPort, Minor::LSQ::DcachePort, System::SystemPort, RubyTester::CpuPort, Minor::Fetch1::IcachePort, X86ISA::Walker::WalkerPort, and RubyDirectedTester::CpuPort.
Referenced by SlavePort::sendRetryReq().
|
inlineprotectedvirtual |
Called by the slave port if sendTimingSnoopResp was called on this master port (causing recvTimingSnoopResp to be called on the slave port) and was unsuccesful.
Reimplemented in CommMonitor::MonitorMasterPort, and QueuedMasterPort.
Definition at line 310 of file port.hh.
References Port::name(), and panic.
Referenced by SlavePort::sendRetrySnoopResp().
|
protectedpure virtual |
Receive a timing response from the slave port.
Implemented in ComputeUnit::LDSPort, ComputeUnit::ITLBPort, BaseKvmCPU::KVMCpuPort, ComputeUnit::DTLBPort, ComputeUnit::SQCPort, ComputeUnit::DataPort, X86ISA::GpuTLB::MemSidePort, Bridge::BridgeMasterPort, SerialLink::SerialLinkMasterPort, TraceCPU::DcachePort, TraceCPU::IcachePort, CoherentXBar::SnoopRespPort, TimingSimpleCPU::DcachePort, AbstractController::MemoryPort, TLBCoalescer::MemSidePort, TimingSimpleCPU::IcachePort, TrafficGen::TrafficGenPort, FullO3CPU< Impl >::DcachePort, CoherentXBar::CoherentXBarMasterPort, NoncoherentXBar::NoncoherentXBarMasterPort, FullO3CPU< Impl >::IcachePort, CommMonitor::MonitorMasterPort, GpuDispatcher::TLBPort, DmaPort, AtomicSimpleCPU::AtomicCPUPort, AddrMapper::MapperMasterPort, MemCheckerMonitor::MonitorMasterPort, RubyPort::PioMasterPort, MemTest::CpuPort, GarnetSyntheticTraffic::CpuPort, System::SystemPort, Minor::LSQ::DcachePort, MessageMasterPort, RubyTester::CpuPort, Minor::Fetch1::IcachePort, X86ISA::Walker::WalkerPort, RubyPort::MemMasterPort, and RubyDirectedTester::CpuPort.
Referenced by SlavePort::sendTimingResp().
|
inlineprotectedvirtual |
Receive a timing snoop request from the slave port.
Reimplemented in TraceCPU::DcachePort, TraceCPU::IcachePort, TimingSimpleCPU::DcachePort, TrafficGen::TrafficGenPort, CoherentXBar::CoherentXBarMasterPort, FullO3CPU< Impl >::DcachePort, CommMonitor::MonitorMasterPort, AddrMapper::MapperMasterPort, MemCheckerMonitor::MonitorMasterPort, MemTest::CpuPort, and Minor::LSQ::DcachePort.
Definition at line 293 of file port.hh.
References Port::name(), and panic.
Referenced by SlavePort::sendTimingSnoopReq().
Send an atomic request packet, where the data is moved and the state is updated in zero time, without interleaving with other memory accesses.
pkt | Packet to send. |
Definition at line 166 of file port.cc.
References _slavePort, Packet::isRequest(), and SlavePort::recvAtomic().
Referenced by Cache::doWritebacksAtomic(), ArmISA::Stage2MMU::readDataUntimed(), AtomicSimpleCPU::readMem(), SerialLink::SerialLinkSlavePort::recvAtomic(), Bridge::BridgeSlavePort::recvAtomic(), MemCheckerMonitor::recvAtomic(), AddrMapper::recvAtomic(), CommMonitor::recvAtomic(), Cache::recvAtomic(), DmaPort::sendDma(), X86ISA::IntDevice::IntMasterPort::sendMessage(), AtomicSimpleCPU::tick(), and AtomicSimpleCPU::writeMem().
void MasterPort::sendFunctional | ( | PacketPtr | pkt | ) |
Send a functional request packet, where the data is instantly updated everywhere in the memory system, without affecting the current state of any block or moving the block.
pkt | Packet to send. |
Definition at line 173 of file port.cc.
References _slavePort, Packet::isRequest(), and SlavePort::recvFunctional().
Referenced by FetchUnit::fetch(), ArmISA::TableWalker::fetchDescriptor(), Cache::functionalAccess(), AbstractController::functionalMemoryRead(), AbstractController::functionalMemoryWrite(), Shader::functionalTLBAccess(), FetchUnit::initiateFetch(), printAddr(), AbstractController::queueMemoryRead(), AbstractController::queueMemoryWrite(), PortProxy::readBlob(), ArmISA::Stage2MMU::readDataUntimed(), CheckerCPU::readMem(), SerialLink::SerialLinkSlavePort::recvFunctional(), MemCheckerMonitor::recvFunctional(), AddrMapper::recvFunctional(), Bridge::BridgeSlavePort::recvFunctional(), CommMonitor::recvFunctional(), MemTest::tick(), Cache::writebackVisitor(), and PortProxy::writeBlob().
|
virtual |
Send a retry to the slave port that previously attempted a sendTimingResp to this master port and failed.
Note that this is virtual so that the "fake" snoop response port in the coherent crossbar can override the behaviour.
Reimplemented in CoherentXBar::SnoopRespPort.
Definition at line 194 of file port.cc.
References _slavePort, and SlavePort::recvRespRetry().
Referenced by MemCheckerMonitor::recvRespRetry(), AddrMapper::recvRespRetry(), CommMonitor::recvRespRetry(), and BaseXBar::RespLayer::sendRetry().
bool MasterPort::sendTimingReq | ( | PacketPtr | pkt | ) |
Attempt to send a timing request to the slave port by calling its corresponding receive function.
If the send does not succeed, as indicated by the return value, then the sender must wait for a recvReqRetry at which point it can re-issue a sendTimingReq.
pkt | Packet to send. |
Definition at line 180 of file port.cc.
References _slavePort, Packet::isRequest(), and SlavePort::recvTimingReq().
Referenced by GarnetSyntheticTraffic::doRetry(), TraceCPU::ElasticDataGen::execute(), TraceCPU::ElasticDataGen::executeMemReq(), FetchUnit::fetch(), TimingSimpleCPU::handleReadPacket(), TimingSimpleCPU::handleWritePacket(), InvalidateGenerator::initiate(), SeriesRequestGenerator::initiate(), Check::initiateAction(), Check::initiateCheck(), FetchUnit::initiateFetch(), Check::initiateFlush(), Check::initiatePrefetch(), TrafficGen::recvReqRetry(), TimingSimpleCPU::IcachePort::recvReqRetry(), TimingSimpleCPU::DcachePort::recvReqRetry(), ComputeUnit::LDSPort::recvReqRetry(), MemTest::recvRetry(), MemCheckerMonitor::recvTimingReq(), AddrMapper::recvTimingReq(), CommMonitor::recvTimingReq(), Cache::recvTimingReq(), TraceCPU::FixedRetryGen::send(), TimingSimpleCPU::sendFetch(), Cache::sendMSHRQueuePacket(), X86ISA::Walker::sendTiming(), ReqPacketQueue::sendTiming(), ComputeUnit::LDSPort::sendTimingReq(), Cache::sendWriteQueuePacket(), TraceCPU::FixedRetryGen::tryNext(), DmaPort::trySendTimingReq(), Minor::Fetch1::tryToSend(), Minor::LSQ::tryToSend(), and TrafficGen::update().
bool MasterPort::sendTimingSnoopResp | ( | PacketPtr | pkt | ) |
Attempt to send a timing snoop response packet to the slave port by calling its corresponding receive function.
If the send does not succeed, as indicated by the return value, then the sender must wait for a recvRetrySnoop at which point it can re-issue a sendTimingSnoopResp.
pkt | Packet to send. |
Definition at line 187 of file port.cc.
References _slavePort, Packet::isResponse(), and SlavePort::recvTimingSnoopResp().
Referenced by MemCheckerMonitor::recvTimingSnoopResp(), AddrMapper::recvTimingSnoopResp(), CommMonitor::recvTimingSnoopResp(), and SnoopRespPacketQueue::sendTiming().
|
virtual |
Unbind this master port and the associated slave port.
Implements BaseMasterPort.
Definition at line 149 of file port.cc.
References BaseMasterPort::_baseSlavePort, _slavePort, Port::name(), panic, and SlavePort::unbind().
|
private |
Definition at line 174 of file port.hh.
Referenced by bind(), getAddrRanges(), sendAtomic(), sendFunctional(), sendRetryResp(), sendTimingReq(), sendTimingSnoopResp(), and unbind().