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gem5
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gem5
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IcachePort class that interfaces with L1 Instruction Cache. More...
#include <trace_cpu.hh>
Public Member Functions | |
| IcachePort (TraceCPU *_cpu) | |
| Default constructor. More... | |
| bool | recvTimingResp (PacketPtr pkt) |
| Receive the timing reponse and simply delete the packet since instruction fetch requests are issued as per the timing in the trace and responses are ignored. More... | |
| void | recvTimingSnoopReq (PacketPtr pkt) |
| Required functionally but do nothing. More... | |
| void | recvReqRetry () |
| Handle a retry signalled by the cache if instruction read failed in the first attempt. More... | |
 Public Member Functions inherited from MasterPort | |
| MasterPort (const std::string &name, MemObject *owner, PortID id=InvalidPortID) | |
| Master port. More... | |
| virtual | ~MasterPort () |
| void | bind (BaseSlavePort &slave_port) |
| Bind this master port to a slave port. More... | |
| void | unbind () |
| Unbind this master port and the associated slave port. More... | |
| Tick | sendAtomic (PacketPtr pkt) |
| Send an atomic request packet, where the data is moved and the state is updated in zero time, without interleaving with other memory accesses. More... | |
| void | sendFunctional (PacketPtr pkt) |
| Send a functional request packet, where the data is instantly updated everywhere in the memory system, without affecting the current state of any block or moving the block. More... | |
| bool | sendTimingReq (PacketPtr pkt) |
| Attempt to send a timing request to the slave port by calling its corresponding receive function. More... | |
| bool | sendTimingSnoopResp (PacketPtr pkt) |
| Attempt to send a timing snoop response packet to the slave port by calling its corresponding receive function. More... | |
| virtual void | sendRetryResp () |
| Send a retry to the slave port that previously attempted a sendTimingResp to this master port and failed. More... | |
| virtual bool | isSnooping () const |
| Determine if this master port is snooping or not. More... | |
| AddrRangeList | getAddrRanges () const |
| Get the address ranges of the connected slave port. More... | |
| void | printAddr (Addr a) |
| Inject a PrintReq for the given address to print the state of that address throughout the memory system. More... | |
| Public Member Functions inherited from BaseMasterPort | |
| BaseSlavePort & | getSlavePort () const |
| bool | isConnected () const |
| Public Member Functions inherited from Port | |
| const std::string | name () const |
| Return port name (for DPRINTF). More... | |
| PortID | getId () const |
| Get the port id. More... | |
Private Attributes | |
| TraceCPU * | owner |
Additional Inherited Members | |
| Protected Member Functions inherited from MasterPort | |
| virtual Tick | recvAtomicSnoop (PacketPtr pkt) |
| Receive an atomic snoop request packet from the slave port. More... | |
| virtual void | recvFunctionalSnoop (PacketPtr pkt) |
| Receive a functional snoop request packet from the slave port. More... | |
| virtual void | recvRetrySnoopResp () |
| Called by the slave port if sendTimingSnoopResp was called on this master port (causing recvTimingSnoopResp to be called on the slave port) and was unsuccesful. More... | |
| virtual void | recvRangeChange () |
| Called to receive an address range change from the peer slave port. More... | |
| Protected Member Functions inherited from BaseMasterPort | |
| BaseMasterPort (const std::string &name, MemObject *owner, PortID id=InvalidPortID) | |
| virtual | ~BaseMasterPort () |
| Protected Member Functions inherited from Port | |
| Port (const std::string &_name, MemObject &_owner, PortID _id) | |
| Abstract base class for ports. More... | |
| virtual | ~Port () |
| Virtual destructor due to inheritance. More... | |
| Protected Attributes inherited from BaseMasterPort | |
| BaseSlavePort * | _baseSlavePort |
| Protected Attributes inherited from Port | |
| const PortID | id |
| A numeric identifier to distinguish ports in a vector, and set to InvalidPortID in case this port is not part of a vector. More... | |
| MemObject & | owner |
| A reference to the MemObject that owns this port. More... | |
IcachePort class that interfaces with L1 Instruction Cache.
Definition at line 228 of file trace_cpu.hh.
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inline |
Default constructor.
Definition at line 232 of file trace_cpu.hh.
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virtual |
Handle a retry signalled by the cache if instruction read failed in the first attempt.
Implements MasterPort.
Definition at line 1235 of file trace_cpu.cc.
References TraceCPU::icacheRetryRecvd(), and TraceCPU::ElasticDataGen::owner.
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virtual |
Receive the timing reponse and simply delete the packet since instruction fetch requests are issued as per the timing in the trace and responses are ignored.
| pkt | Pointer to packet received |
Implements MasterPort.
Definition at line 1224 of file trace_cpu.cc.
References Packet::req.
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inlinevirtual |
Required functionally but do nothing.
| pkt | Pointer to packet received |
Reimplemented from MasterPort.
Definition at line 253 of file trace_cpu.hh.
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private |
Definition at line 262 of file trace_cpu.hh.