53 instMasterID(params->
system->getMasterId(
name() +
".inst")),
54 dataMasterID(params->
system->getMasterId(
name() +
".data")),
55 instTraceFile(params->instTraceFile),
56 dataTraceFile(params->dataTraceFile),
57 icacheGen(*this,
".iside", icachePort, instMasterID, instTraceFile),
58 dcacheGen(*this,
".dside", dcachePort, dataMasterID, dataTraceFile,
60 icacheNextEvent(this),
61 dcacheNextEvent(this),
62 oneTraceComplete(false),
64 execCompleteEvent(nullptr),
65 enableEarlyExit(params->enableEarlyExit),
66 progressMsgInterval(params->progressMsgInterval),
67 progressMsgThreshold(params->progressMsgInterval)
74 fatal_if(params->sizeROB > UINT16_MAX,
"ROB size set to %d exceeds the "
75 "max. value of %d.\n", params->sizeROB, UINT16_MAX);
76 fatal_if(params->sizeStoreBuffer > UINT16_MAX,
"ROB size set to %d "
77 "exceeds the max. value of %d.\n", params->sizeROB,
79 fatal_if(params->sizeLoadBuffer > UINT16_MAX,
"Load buffer size set to"
80 " %d exceeds the max. value of %d.\n",
81 params->sizeLoadBuffer, UINT16_MAX);
90 TraceCPUParams::create()
110 assert(oldCPU->getInstPort().isConnected());
111 BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
112 oldCPU->getInstPort().unbind();
116 assert(oldCPU->getDataPort().isConnected());
117 BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort();
118 oldCPU->getDataPort().unbind();
125 DPRINTF(TraceCPUInst,
"Instruction fetch request trace file is \"%s\"."
127 DPRINTF(TraceCPUData,
"Data memory request trace file is \"%s\".\n",
139 traceOffset = std::min(first_icache_tick, first_dcache_tick);
140 inform(
"%s: Time offset (tick) found as min of both traces is %lli.\n",
168 DPRINTF(TraceCPUInst,
"IcacheGen event.\n");
174 DPRINTF(TraceCPUInst,
"Scheduling next icacheGen event "
193 DPRINTF(TraceCPUData,
"DcacheGen event.\n");
196 numCycles = clockEdge() / clockPeriod();
232 .
name(
name() +
".numSchedDcacheEvent")
233 .
desc(
"Number of events scheduled to trigger data request generator")
237 .
name(
name() +
".numSchedIcacheEvent")
238 .
desc(
"Number of events scheduled to trigger instruction request generator")
243 .
desc(
"Number of micro-ops simulated by the Trace CPU")
248 .
desc(
"Cycles per micro-op used as a proxy for CPI")
260 using namespace Stats;
264 .
desc(
"Max number of dependents observed on a node")
269 .
desc(
"Max size of the ready list observed")
274 .
desc(
"Number of first attempts to send a request")
279 .
desc(
"Number of successful first attempts")
284 .
desc(
"Number of failed first attempts")
288 .
name(
name() +
".numRetrySucceeded")
289 .
desc(
"Number of successful retries")
294 .
desc(
"Number of split requests")
299 .
desc(
"Number of strictly ordered loads")
304 .
desc(
"Number of strictly ordered stores")
309 .
desc(
"Last tick simulated from the elastic data trace")
316 DPRINTF(TraceCPUData,
"Initializing data memory request generator "
317 "DcacheGen: elastic issue with retry.\n");
320 panic(
"Trace has %d elements. It must have at least %d elements.\n",
322 DPRINTF(TraceCPUData,
"After 1st read, depGraph size:%d.\n",
326 panic(
"Trace has %d elements. It must have at least %d elements.\n",
328 DPRINTF(TraceCPUData,
"After 2st read, depGraph size:%d.\n",
332 if (
DTRACE(TraceCPUData)) {
336 DPRINTF(TraceCPUData,
"Execute tick of the first dependency free node %lli"
337 " is %d.\n", free_itr->seqNum, free_itr->execTick);
340 return (free_itr->execTick);
346 free_node.execTick -=
offset;
361 DPRINTF(TraceCPUData,
"Reading next window from file.\n");
369 DPRINTF(TraceCPUData,
"Start read: Size of depGraph is %d.\n",
372 uint32_t num_read = 0;
382 DPRINTF(TraceCPUData,
"\tTrace complete!\n");
404 DPRINTF(TraceCPUData,
"End read: Size of depGraph is %d.\n",
409 template<
typename T>
void
411 T& dep_array, uint8_t& num_dep)
413 for (
auto& a_dep : dep_array) {
421 auto parent_itr =
depGraph.find(a_dep);
426 parent_itr->second->dependents.push_back(new_node);
427 auto num_depts = parent_itr->second->dependents.size();
442 DPRINTF(TraceCPUData,
"Execute start occupancy:\n");
443 DPRINTFR(TraceCPUData,
"\tdepGraph = %d, readyList = %d, "
460 DPRINTF(TraceCPUData,
"Removing from depFreeQueue: seq. num "
475 graph_itr =
depGraph.find(free_itr->seqNum);
476 assert(graph_itr !=
depGraph.end());
484 panic(
"Retry packet's seqence number does not match "
485 "the first node in the readyList.\n");
491 }
else if (node_ptr->isLoad() || node_ptr->isStore()) {
512 if (node_ptr->isLoad() && !node_ptr->isStrictlyOrdered()) {
514 DPRINTF(TraceCPUData,
"Node seq. num %lli sent. Waking up "
515 "dependents..\n", node_ptr->seqNum);
517 auto child_itr = (node_ptr->dependents).begin();
518 while (child_itr != (node_ptr->dependents).end()) {
521 if (!(*child_itr)->isStore() &&
522 (*child_itr)->removeRobDep(node_ptr->seqNum)) {
525 if ((*child_itr)->numRobDep == 0 &&
526 (*child_itr)->numRegDep == 0) {
534 child_itr = node_ptr->dependents.erase(child_itr);
545 DPRINTF(TraceCPUData,
"Node seq. num %lli done. Waking"
546 " up dependents..\n", node_ptr->seqNum);
548 for (
auto child : node_ptr->dependents) {
551 if (child->removeDepOnInst(node_ptr->seqNum)) {
568 if (!node_ptr->isLoad() || node_ptr->isStrictlyOrdered()) {
572 (node_ptr->dependents).
clear();
585 if (
DTRACE(TraceCPUData)) {
587 DPRINTF(TraceCPUData,
"Execute end occupancy:\n");
588 DPRINTFR(TraceCPUData,
"\tdepGraph = %d, readyList = %d, "
595 DPRINTF(TraceCPUData,
"Not scheduling an event as expecting a retry"
596 "event from the cache for seq. num %lli.\n",
613 DPRINTF(TraceCPUData,
"Attempting to schedule @%lli.\n",
618 DPRINTF(TraceCPUData,
"Attempting to schedule @%lli.\n",
627 DPRINTF(TraceCPUData,
"\tExecution Complete!\n");
637 DPRINTF(TraceCPUData,
"Executing memory request %lli (phys addr %d, "
638 "virt addr %d, pc %#x, size %d, flags %d).\n",
646 DPRINTF(TraceCPUData,
"Skipping strictly ordered request %lli.\n",
657 unsigned blk_size =
owner.cacheLineSize();
659 if (!(blk_offset + node_ptr->
size <= blk_size)) {
660 node_ptr->
size = blk_size - blk_offset;
679 uint8_t* pkt_data =
new uint8_t[req->
getSize()];
684 memset(pkt_data, 0xA, req->
getSize());
696 DPRINTF(TraceCPUData,
"Send failed. Saving packet for retry.\n");
713 DPRINTFR(TraceCPUData,
"\t\tseq. num %lli(%s) with rob num %lli is now"
721 DPRINTFR(TraceCPUData,
"\t\tResources available for seq. num %lli. Adding"
722 " to readyList, occupying resources.\n", node_ptr->
seqNum);
734 DPRINTFR(TraceCPUData,
"\t\tResources unavailable for seq. num %lli."
735 " Adding to depFreeQueue.\n", node_ptr->
seqNum);
738 DPRINTFR(TraceCPUData,
"\t\tResources unavailable for seq. num %lli. "
739 "Still pending issue.\n", node_ptr->
seqNum);
760 assert(graph_itr !=
depGraph.end());
766 DPRINTF(TraceCPUData,
"Load seq. num %lli response received. Waking up"
767 " dependents..\n", node_ptr->seqNum);
769 for (
auto child : node_ptr->dependents) {
770 if (child->removeDepOnInst(node_ptr->seqNum)) {
776 (node_ptr->dependents).
clear();
785 if (
DTRACE(TraceCPUData)) {
806 DPRINTF(TraceCPUData,
"Attempting to schedule @%lli.\n",
817 ready_node.
seqNum = seq_num;
842 while (!found && itr !=
readyList.end()) {
845 if (exec_tick < itr->execTick)
849 else if (exec_tick == itr->execTick) {
852 if (seq_num < itr->seqNum)
874 DPRINTF(TraceCPUData,
"readyList is empty.\n");
877 DPRINTF(TraceCPUData,
"Printing readyList:\n");
879 auto graph_itr =
depGraph.find(itr->seqNum);
881 DPRINTFR(TraceCPUData,
"\t%lld(%s), %lld\n", itr->seqNum,
882 node_ptr->typeToStr(), itr->execTick);
888 uint16_t max_rob, uint16_t max_stores, uint16_t max_loads)
890 sizeStoreBuffer(max_stores),
891 sizeLoadBuffer(max_loads),
892 oldestInFlightRobNum(UINT64_MAX),
904 oldestInFlightRobNum = inFlightNodes.begin()->second;
909 }
else if (new_node->
isStore()) {
919 assert(!inFlightNodes.empty());
920 DPRINTFR(TraceCPUData,
"\tClearing done seq. num %d from inFlightNodes..\n",
923 assert(inFlightNodes.find(done_node->
seqNum) != inFlightNodes.end());
924 inFlightNodes.erase(done_node->
seqNum);
926 if (inFlightNodes.empty()) {
929 oldestInFlightRobNum = UINT64_MAX;
933 oldestInFlightRobNum = inFlightNodes.begin()->second;
936 DPRINTFR(TraceCPUData,
"\tCleared. inFlightNodes.size() = %d, "
937 "oldestInFlightRobNum = %d\n", inFlightNodes.size(),
938 oldestInFlightRobNum);
944 if (done_node->
isLoad()) {
945 assert(numInFlightLoads != 0);
953 releaseStoreBuffer();
960 assert(numInFlightStores != 0);
968 uint16_t num_in_flight_nodes;
969 if (inFlightNodes.empty()) {
970 num_in_flight_nodes = 0;
971 DPRINTFR(TraceCPUData,
"\t\tChecking resources to issue seq. num %lli:"
972 " #in-flight nodes = 0", new_node->
seqNum);
973 }
else if (new_node->
robNum > oldestInFlightRobNum) {
977 num_in_flight_nodes = new_node->
robNum - oldestInFlightRobNum;
978 DPRINTFR(TraceCPUData,
"\t\tChecking resources to issue seq. num %lli:"
979 " #in-flight nodes = %d - %d = %d", new_node->
seqNum,
980 new_node->
robNum, oldestInFlightRobNum, num_in_flight_nodes);
987 num_in_flight_nodes = 0;
988 DPRINTFR(TraceCPUData,
"\t\tChecking resources to issue seq. num %lli:"
989 " new oldestInFlightRobNum = %d, #in-flight nodes ignored",
992 DPRINTFR(TraceCPUData,
", LQ = %d/%d, SQ = %d/%d.\n",
993 numInFlightLoads, sizeLoadBuffer,
994 numInFlightStores, sizeStoreBuffer);
996 if (num_in_flight_nodes >= sizeROB) {
999 if (new_node->
isLoad() && numInFlightLoads >= sizeLoadBuffer) {
1002 if (new_node->
isStore() && numInFlightStores >= sizeStoreBuffer) {
1011 return (numInFlightStores != 0 || numInFlightLoads != 0);
1016 DPRINTFR(TraceCPUData,
"oldestInFlightRobNum = %d, "
1017 "LQ = %d/%d, SQ = %d/%d.\n",
1018 oldestInFlightRobNum,
1019 numInFlightLoads, sizeLoadBuffer,
1020 numInFlightStores, sizeStoreBuffer);
1026 using namespace Stats;
1029 .
name(
name() +
".numSendAttempted")
1030 .
desc(
"Number of first attempts to send a request")
1034 .
name(
name() +
".numSendSucceeded")
1035 .
desc(
"Number of successful first attempts")
1040 .
desc(
"Number of failed first attempts")
1044 .
name(
name() +
".numRetrySucceeded")
1045 .
desc(
"Number of successful retries")
1050 .
desc(
"Last tick simulated from the fixed inst trace")
1057 DPRINTF(TraceCPUInst,
"Initializing instruction fetch request generator"
1058 " IcacheGen: fixed issue with retry.\n");
1060 if (nextExecute()) {
1061 DPRINTF(TraceCPUInst,
"\tFirst tick = %d.\n", currElement.tick);
1062 return currElement.tick;
1064 panic(
"Read of first message in the trace failed.\n");
1075 DPRINTF(TraceCPUInst,
"Trying to send retry packet.\n");
1079 DPRINTF(TraceCPUInst,
"Retry packet sending failed.\n");
1085 DPRINTF(TraceCPUInst,
"Trying to send packet for currElement.\n");
1088 assert(currElement.isValid());
1092 if (!send(currElement.addr, currElement.blocksize,
1093 currElement.cmd, currElement.flags, currElement.pc)) {
1094 DPRINTF(TraceCPUInst,
"currElement sending failed.\n");
1105 DPRINTF(TraceCPUInst,
"Packet sent successfully, trying to read next "
1110 Tick last_tick = currElement.tick;
1111 if (nextExecute()) {
1112 assert(currElement.tick >= last_tick);
1113 delta = currElement.tick - last_tick;
1134 currElement.clear();
1145 DPRINTF(TraceCPUInst,
"inst fetch: %c addr %d pc %#x size %d tick %d\n",
1146 currElement.cmd.isRead() ?
'r' :
'w',
1149 currElement.blocksize,
1170 uint8_t* pkt_data =
new uint8_t[req->
getSize()];
1174 memset(pkt_data, 0xA, req->
getSize());
1192 DPRINTF(TraceCPUInst,
"Icache retry received. Scheduling next IcacheGen"
1193 " event @%lli.\n",
curTick());
1202 DPRINTF(TraceCPUData,
"Dcache retry received. Scheduling next DcacheGen"
1203 " event @%lli.\n",
curTick());
1211 DPRINTF(TraceCPUData,
"Scheduling next DcacheGen event at %lli.\n",
1216 DPRINTF(TraceCPUData,
"Re-scheduling next dcache event from %lli"
1243 DPRINTF(TraceCPUData,
"Received timing response from Dcache.\n");
1268 const std::string& filename,
1269 const double time_multiplier)
1271 timeMultiplier(time_multiplier),
1275 ProtoMessage::InstDepRecordHeader header_msg;
1277 panic(
"Failed to read packet header from %s\n", filename);
1280 panic(
"Trace %s was recorded with a different tick frequency %d\n",
1281 header_msg.tick_freq());
1299 ProtoMessage::InstDepRecord pkt_msg;
1302 element->
seqNum = pkt_msg.seq_num();
1303 element->
type = pkt_msg.type();
1305 element->
compDelay = pkt_msg.comp_delay() * timeMultiplier;
1310 for (
int i = 0;
i < (pkt_msg.rob_dep()).
size();
i++) {
1318 for (
int i = 0;
i < (pkt_msg.reg_dep()).
size();
i++) {
1322 bool duplicate =
false;
1324 duplicate |= (pkt_msg.reg_dep(
i) == element->
robDep[
j]);
1333 if (pkt_msg.has_p_addr())
1334 element->
physAddr = pkt_msg.p_addr();
1338 if (pkt_msg.has_v_addr())
1339 element->
virtAddr = pkt_msg.v_addr();
1343 if (pkt_msg.has_asid())
1344 element->
asid = pkt_msg.asid();
1348 if (pkt_msg.has_size())
1349 element->
size = pkt_msg.size();
1353 if (pkt_msg.has_flags())
1354 element->
flags = pkt_msg.flags();
1358 if (pkt_msg.has_pc())
1359 element->
pc = pkt_msg.pc();
1365 if (pkt_msg.has_weight()) {
1366 microOpCount += pkt_msg.weight();
1368 element->
robNum = microOpCount;
1379 for (
auto& own_reg_dep : regDep) {
1380 if (own_reg_dep == reg_dep) {
1383 assert(numRegDep > 0);
1385 DPRINTFR(TraceCPUData,
"\tFor %lli: Marking register dependency %lli "
1386 "done.\n", seqNum, reg_dep);
1398 for (
auto& own_rob_dep : robDep) {
1399 if (own_rob_dep == rob_dep) {
1402 assert(numRobDep > 0);
1404 DPRINTFR(TraceCPUData,
"\tFor %lli: Marking ROB dependency %lli "
1405 "done.\n", seqNum, rob_dep);
1414 for (
auto& own_reg_dep : regDep) {
1422 for (
auto& own_rob_dep : robDep) {
1432 if (!removeRobDep(done_seq_num)) {
1436 bool regdep_found
M5_VAR_USED = removeRegDep(done_seq_num);
1437 assert(regdep_found);
1440 return (numRobDep == 0 && numRegDep == 0);
1446 DPRINTFR(TraceCPUData,
"%lli", seqNum);
1447 DPRINTFR(TraceCPUData,
",%s", typeToStr());
1448 if (isLoad() || isStore()) {
1451 DPRINTFR(TraceCPUData,
",%i", flags);
1453 DPRINTFR(TraceCPUData,
",%lli", compDelay);
1456 while (robDep[i] != 0) {
1457 DPRINTFR(TraceCPUData,
",%lli", robDep[i]);
1462 while (regDep[i] != 0) {
1463 DPRINTFR(TraceCPUData,
",%lli", regDep[i]);
1466 auto child_itr = dependents.begin();
1467 DPRINTFR(TraceCPUData,
"dependents:");
1468 while (child_itr != dependents.end()) {
1469 DPRINTFR(TraceCPUData,
":%lli", (*child_itr)->seqNum);
1479 return Record::RecordType_Name(
type);
1486 ProtoMessage::PacketHeader header_msg;
1488 panic(
"Failed to read packet header from %s\n", filename);
1491 panic(
"Trace %s was recorded with a different tick frequency %d\n",
1492 header_msg.tick_freq());
1508 element->
cmd = pkt_msg.
cmd();
1509 element->
addr = pkt_msg.addr();
1511 element->
tick = pkt_msg.tick();
1512 element->
flags = pkt_msg.has_flags() ? pkt_msg.flags() : 0;
1513 element->
pc = pkt_msg.has_pc() ? pkt_msg.pc() : 0;
InputStream trace
Input stream used for reading the input trace file.
void execute()
This is the main execute function which consumes nodes from the sorted readyList. ...
Struct to store a ready-to-execute node and its execution tick.
Counter value() const
Return the current value of this stat as its base type.
void schedDcacheNext()
This is the control flow that uses the functionality of the dcacheGen to replay the trace...
MasterPort & getDataPort()
Used to get a reference to the dcache port.
Stats::Scalar maxReadyListSize
const uint64_t progressMsgInterval
Interval of committed instructions specified by the user at which a progress info message is printed...
bool send(Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags, Addr pc)
Creates a new request assigning the request parameters passed by the arguments.
Addr blocksize
The size of the access for the request.
Stats::Scalar dataLastTick
Tick when ElasticDataGen completes execution.
TraceCPU & owner
Reference of the TraceCPU.
Cycles is a wrapper class for representing cycle counts, i.e.
NodeSeqNum seqNum
The sequence number of the ready node.
void exit()
Exit the FixedRetryGen.
void recvReqRetry()
Handle a retry signalled by the cache if data access failed in the first attempt. ...
bool isTraceComplete()
Returns the traceComplete variable which is set when end of the input trace file is reached...
const std::string & name()
bool removeRegDep(NodeSeqNum reg_dep)
Remove completed instruction from register dependency array.
std::list< ReadyNode > readyList
List of nodes that are ready to execute.
Request::Flags flags
Request flags if any.
RecordType type
Type of the node corresponding to the instruction modelled by it.
PacketPtr retryPkt
PacketPtr used to store the packet to retry.
Stats::Scalar numSchedIcacheEvent
bool nextExecute()
Reads a line of the trace file.
void updateNumOps(uint64_t rob_num)
HardwareResource(uint16_t max_rob, uint16_t max_stores, uint16_t max_loads)
Constructor that initializes the sizes of the structures.
PacketPtr executeMemReq(GraphNode *node_ptr)
Creates a new request for a load or store assigning the request parameters.
Request::FlagsType flags
Potential request flags to use.
Stats::Scalar numSOStores
void completeMemAccess(PacketPtr pkt)
When a load writeback is received, that is when the load completes, release the dependents on it...
Tick traceOffset
This stores the time offset in the trace, which is taken away from the ready times of requests...
bool scheduled() const
Determine if the current event is scheduled.
std::string instTraceFile
File names for input instruction and data traces.
void exit()
Exit the ElasticDataGen.
uint32_t asid
The address space id which is set if the virtual address is set.
static const uint8_t maxRobDep
The maximum no.
bool recvTimingResp(PacketPtr pkt)
Receive the timing reponse and simply delete the packet since instruction fetch requests are issued a...
void checkAndSchedExitEvent()
This is called when either generator finishes executing from the trace.
void setContext(ContextID context_id)
Set up Context numbers.
bool oneTraceComplete
Set to true when one of the generators finishes replaying its trace.
void schedIcacheNext()
This is the control flow that uses the functionality of the icacheGen to replay the trace...
Stats::Scalar numSchedDcacheEvent
MemCmd cmd
Specifies if the request is to be a read or a write.
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the slave port by calling its corresponding receive function...
void clearRobDep()
Initialize register dependency array to all zeroes.
uint64_t NodeSeqNum
Node sequence number type.
bool readNextWindow()
Reads a line of the trace file.
Stats::Scalar maxDependents
Stats for data memory accesses replayed.
uint8_t numRegDep
Number of register dependencies.
Tick Frequency
The simulated frequency of curTick(). (In ticks per second)
bool execComplete
Set true when execution of trace is complete.
void addDepsOnParent(GraphNode *new_node, T &dep_array, uint8_t &num_dep)
Iterate over the dependencies of a new node and add the new node to the list of dependents of the par...
Stats::Scalar numSendSucceeded
EventWrapper< TraceCPU,&TraceCPU::schedIcacheNext > icacheNextEvent
Event for the control flow method schedIcacheNext()
A BaseSlavePort is a protocol-agnostic slave port, responsible only for the structural connection to ...
bool traceComplete
Set to true when end of trace is reached.
Tick init()
Called from TraceCPU init().
void clearRegDep()
Initialize register dependency array to all zeroes.
const uint32_t windowSize
Window size within which to check for dependencies.
std::queue< const GraphNode * > depFreeQueue
Queue of dependency-free nodes that are pending issue because resources are not available.
bool isAvailable(const GraphNode *new_node) const
Check if structures required to issue a node are free.
CountedExitEvent * execCompleteEvent
A CountedExitEvent which when serviced decrements the counter.
Tick curTick()
The current simulated tick.
bool isExecComplete() const
Returns the execComplete variable which is set when the last node is executed.
The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model...
uint64_t progressMsgThreshold
NodeRobNum robNum
ROB occupancy number.
bool isStrictlyOrdered() const
Return true if node has a request which is strictly ordered.
TraceCPU(TraceCPUParams *params)
Tick when() const
Get the time that the event is scheduled.
uint64_t Tick
Tick count type.
const bool enableEarlyExit
Exit when any one Trace CPU completes its execution.
The struct GraphNode stores an instruction in the trace file.
bool nextRead
Set to true when the next window of instructions need to be read.
This struct stores a line in the trace file.
const RequestPtr req
A pointer to the original request.
void dcacheRetryRecvd()
When data cache port receives a retry, schedule event dcacheNextEvent.
FixedRetryGen icacheGen
Instance of FixedRetryGen to replay instruction read requests.
void recvReqRetry()
Handle a retry signalled by the cache if instruction read failed in the first attempt.
void writeElementAsTrace() const
Write out element in trace-compatible format using debug flag TraceCPUData.
const std::string & name() const
Returns name of the ElasticDataGen instance.
void setReqInstSeqNum(const InstSeqNum seq_num)
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
void release(const GraphNode *done_node)
Release appropriate structures for a completed node.
Derived & precision(int _precision)
Set the precision and marks this stat to print at the end of simulation.
uint64_t compDelay
Computational delay.
MasterPort & port
Reference of the port to be used to issue memory requests.
static int numTraceCPUs
Number of Trace CPUs in the system used as a shared variable and passed to the CountedExitEvent event...
Stats::Formula cpi
Stat for the CPI.
void dcacheRecvTimingResp(PacketPtr pkt)
When data cache port receives a response, this calls the dcache generator method handle to complete t...
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
InstSeqNum getReqInstSeqNum() const
Tick execTick
The tick at which the ready node must be executed.
static const int NumArgumentRegs M5_VAR_USED
Derived & name(const std::string &name)
Set the name and marks this stat to print at the end of simulation.
Stats::Scalar numOps
Stat for number of simulated micro-ops.
bool checkAndIssue(const GraphNode *node_ptr, bool first=true)
Attempts to issue a node once the node's source dependencies are complete.
const MasterID masterID
MasterID used for the requests being sent.
Tick tick
The time at which the request should be sent.
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
bool recvTimingResp(PacketPtr pkt)
Receive the timing reponse and call dcacheRecvTimingResp() method of the dcacheGen to handle completi...
uint8_t numRobDep
Number of order dependencies.
Stats::Scalar numSendFailed
void schedDcacheNextEvent(Tick when)
Schedule event dcacheNextEvent at the given tick.
EventWrapper< TraceCPU,&TraceCPU::schedDcacheNext > dcacheNextEvent
Event for the control flow method schedDcacheNext()
std::string dataTraceFile
Stats::Scalar numSendAttempted
ElasticDataGen dcacheGen
Instance of ElasticDataGen to replay data read and write requests.
bool isLoad() const
Is the node a load.
Addr virtAddr
The virtual address for the request if any.
uint32_t size
Size of request if any.
void printReadyList()
Print readyList for debugging using debug flag TraceCPUData.
void setVirt(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid, Addr pc)
Set up a virtual (e.g., CPU) request in a previously allocated Request object.
void releaseStoreBuffer()
Release store buffer entry for a completed store.
void adjustInitTraceOffset(Tick &offset)
Adjust traceOffset based on what TraceCPU init() determines on comparing the offsets in the fetch req...
void occupy(const GraphNode *new_node)
Occupy appropriate structures for an issued node.
RegDepArray regDep
Array of register dependencies (incoming) if any.
Stats::Scalar numRetrySucceeded
void bind(BaseSlavePort &slave_port)
Bind this master port to a slave port.
static PacketPtr createRead(const RequestPtr req)
Constructor-like methods that return Packets based on Request objects.
std::string typeToStr() const
Return string specifying the type of the node.
void dataDynamic(T *p)
Set the data pointer to a value that should have delete [] called on it.
Addr addr
The address for the request.
Tick init()
Called from TraceCPU init().
bool isStore() const
Is the node a store.
void icacheRetryRecvd()
When instruction cache port receives a retry, schedule event icacheNextEvent.
std::unordered_map< NodeSeqNum, GraphNode * > depGraph
Store the depGraph of GraphNodes.
Addr physAddr
The address for the request if any.
Derived & desc(const std::string &_desc)
Set the description and marks this stat to print at the end of simulation.
bool awaitingResponse() const
Check if there are any outstanding requests, i.e.
Stats::Scalar numSplitReqs
void printOccupancy()
Print resource occupancy for debugging.
void addToSortedReadyList(NodeSeqNum seq_num, Tick exec_tick)
Add a ready node to the readyList.
fatal_if(p->js_features.size() > 16,"Too many job slot feature registers specified (%i)\n", p->js_features.size())
static PacketPtr createWrite(const RequestPtr req)
void setPaddr(Addr paddr)
Set just the physical address.
RobDepArray robDep
Array of order dependencies.
void takeOverFrom(BaseCPU *oldCPU)
int ContextID
Globally unique thread context ID.
const FlagsType init
This Stat is Initialized.
NodeSeqNum seqNum
Instruction sequence number.
InputStream trace
Input stream used for reading the input trace file.
bool removeRobDep(NodeSeqNum rob_dep)
Remove completed instruction from order dependency array.
HardwareResource hwResource
Hardware resources required to contain in-flight nodes and to throttle issuing of new nodes when reso...
bool removeDepOnInst(NodeSeqNum done_seq_num)
Check for all dependencies on completed inst.
ProbePointArg< PacketInfo > Packet
Packet probe point.
MasterPort & getInstPort()
Used to get a reference to the icache port.
bool tryNext()
This tries to send current or retry packet and returns true if successfull.