trace_cpu.hh

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/*
 * Copyright (c) 2013 - 2016 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Radhika Jagtap
 *          Andreas Hansson
 *          Thomas Grass
 */

#ifndef __CPU_TRACE_TRACE_CPU_HH__
#define __CPU_TRACE_TRACE_CPU_HH__

#include <array>
#include <cstdint>
#include <queue>
#include <set>
#include <unordered_map>

#include "arch/registers.hh"
#include "base/statistics.hh"
#include "cpu/base.hh"
#include "debug/TraceCPUData.hh"
#include "debug/TraceCPUInst.hh"
#include "params/TraceCPU.hh"
#include "proto/inst_dep_record.pb.h"
#include "proto/packet.pb.h"
#include "proto/protoio.hh"
#include "sim/sim_events.hh"

class TraceCPU : public BaseCPU
{

  public:
    TraceCPU(TraceCPUParams *params);
    ~TraceCPU();

    void init();

    Counter totalInsts() const
    {
        return 0;
    }

    Counter totalOps() const
    {
        return numOps.value();
    }

    /*
     * Set the no. of ops when elastic data generator completes executing a
     * node.
     */
    void updateNumOps(uint64_t rob_num);

    /* Pure virtual function in BaseCPU. Do nothing. */
    void wakeup(ThreadID tid = 0)
    {
        return;
    }

    /*
     * When resuming from checkpoint in FS mode, the TraceCPU takes over from
     * the old cpu. This function overrides the takeOverFrom() function in the
     * BaseCPU. It unbinds the ports of the old CPU and binds the ports of the
     * TraceCPU.
     */
    void takeOverFrom(BaseCPU *oldCPU);

    void icacheRetryRecvd();

    void dcacheRetryRecvd();

    void dcacheRecvTimingResp(PacketPtr pkt);

    void schedDcacheNextEvent(Tick when);

  protected:

    class IcachePort : public MasterPort
    {
      public:
        IcachePort(TraceCPU* _cpu)
            : MasterPort(_cpu->name() + ".icache_port", _cpu),
                         owner(_cpu)
        { }

      public:
        bool recvTimingResp(PacketPtr pkt);

        void recvTimingSnoopReq(PacketPtr pkt) { }

        void recvReqRetry();

      private:
        TraceCPU* owner;
    };

    class DcachePort : public MasterPort
    {

      public:
        DcachePort(TraceCPU* _cpu)
            : MasterPort(_cpu->name() + ".dcache_port", _cpu),
                         owner(_cpu)
        { }

      public:

        bool recvTimingResp(PacketPtr pkt);

        void recvTimingSnoopReq(PacketPtr pkt)
        { }

        void recvFunctionalSnoop(PacketPtr pkt)
        { }

        void recvReqRetry();

        bool isSnooping() const { return true; }

      private:
        TraceCPU* owner;
    };

    IcachePort icachePort;

    DcachePort dcachePort;

    const MasterID instMasterID;

    const MasterID dataMasterID;

    std::string instTraceFile, dataTraceFile;

    class FixedRetryGen
    {

      private:

        struct TraceElement {

            MemCmd cmd;

            Addr addr;

            Addr blocksize;

            Tick tick;

            Request::FlagsType flags;

            Addr pc;

            bool isValid() const {
                return cmd != MemCmd::InvalidCmd;
            }

            void clear() {
                cmd = MemCmd::InvalidCmd;
            }
        };

        class InputStream
        {

          private:

            // Input file stream for the protobuf trace
            ProtoInputStream trace;

          public:

            InputStream(const std::string& filename);

            void reset();

            bool read(TraceElement* element);
        };

        public:
        /* Constructor */
        FixedRetryGen(TraceCPU& _owner, const std::string& _name,
                   MasterPort& _port, MasterID master_id,
                   const std::string& trace_file)
            : owner(_owner),
              port(_port),
              masterID(master_id),
              trace(trace_file),
              genName(owner.name() + ".fixedretry" + _name),
              retryPkt(nullptr),
              delta(0),
              traceComplete(false)
        {
        }

        Tick init();

        bool tryNext();

        const std::string& name() const { return genName; }

        bool send(Addr addr, unsigned size, const MemCmd& cmd,
              Request::FlagsType flags, Addr pc);

        void exit();

        bool nextExecute();

        bool isTraceComplete() { return traceComplete; }

        int64_t tickDelta() { return delta; }

        void regStats();

      private:

        TraceCPU& owner;

        MasterPort& port;

        const MasterID masterID;

        InputStream trace;

        std::string genName;

        PacketPtr retryPkt;

        int64_t delta;

        bool traceComplete;

        TraceElement currElement;

        Stats::Scalar numSendAttempted;
        Stats::Scalar numSendSucceeded;
        Stats::Scalar numSendFailed;
        Stats::Scalar numRetrySucceeded;
        Stats::Scalar instLastTick;

    };

    class ElasticDataGen
    {

      private:

        typedef uint64_t NodeSeqNum;

        typedef uint64_t NodeRobNum;

        typedef ProtoMessage::InstDepRecord::RecordType RecordType;
        typedef ProtoMessage::InstDepRecord Record;

        class GraphNode {

          public:
            static const uint8_t maxRobDep = 2;

            typedef std::array<NodeSeqNum, maxRobDep> RobDepArray;

            typedef std::array<NodeSeqNum, TheISA::MaxInstSrcRegs> RegDepArray;

            NodeSeqNum seqNum;

            NodeRobNum robNum;

            RecordType type;

            Addr physAddr;

            Addr virtAddr;

            uint32_t asid;

            uint32_t size;

            Request::Flags flags;

            Addr pc;

            RobDepArray robDep;

            uint8_t numRobDep;

            uint64_t compDelay;

            RegDepArray regDep;

            uint8_t numRegDep;

            std::vector<GraphNode *> dependents;

            bool isLoad() const { return (type == Record::LOAD); }

            bool isStore() const { return (type == Record::STORE); }

            bool isComp() const { return (type == Record::COMP); }

            void clearRegDep();

            void clearRobDep();

            bool removeRegDep(NodeSeqNum reg_dep);

            bool removeRobDep(NodeSeqNum rob_dep);

            bool removeDepOnInst(NodeSeqNum done_seq_num);

            bool isStrictlyOrdered() const {
                return (flags.isSet(Request::STRICT_ORDER));
            }
            void writeElementAsTrace() const;

            std::string typeToStr() const;
        };

        struct ReadyNode
        {
            NodeSeqNum seqNum;

            Tick execTick;
        };

        class HardwareResource
        {
          public:
            HardwareResource(uint16_t max_rob, uint16_t max_stores,
                                uint16_t max_loads);

            void occupy(const GraphNode* new_node);

            void release(const GraphNode* done_node);

            void releaseStoreBuffer();

            bool isAvailable(const GraphNode* new_node) const;

            bool awaitingResponse() const;

            void printOccupancy();

          private:
            const uint16_t sizeROB;

            const uint16_t sizeStoreBuffer;

            const uint16_t sizeLoadBuffer;

            std::map<NodeSeqNum, NodeRobNum> inFlightNodes;

            NodeRobNum oldestInFlightRobNum;

            uint16_t numInFlightLoads;

            uint16_t numInFlightStores;
        };

        class InputStream
        {

          private:

            ProtoInputStream trace;

            const double timeMultiplier;

            uint64_t microOpCount;

            uint32_t windowSize;
          public:

            InputStream(const std::string& filename,
                        const double time_multiplier);

            void reset();

            bool read(GraphNode* element);

            uint32_t getWindowSize() const { return windowSize; }

            uint64_t getMicroOpCount() const { return microOpCount; }
        };

        public:
        /* Constructor */
        ElasticDataGen(TraceCPU& _owner, const std::string& _name,
                   MasterPort& _port, MasterID master_id,
                   const std::string& trace_file, TraceCPUParams *params)
            : owner(_owner),
              port(_port),
              masterID(master_id),
              trace(trace_file, 1.0 / params->freqMultiplier),
              genName(owner.name() + ".elastic" + _name),
              retryPkt(nullptr),
              traceComplete(false),
              nextRead(false),
              execComplete(false),
              windowSize(trace.getWindowSize()),
              hwResource(params->sizeROB, params->sizeStoreBuffer,
                         params->sizeLoadBuffer)
        {
            DPRINTF(TraceCPUData, "Window size in the trace is %d.\n",
                    windowSize);
        }

        Tick init();

        void adjustInitTraceOffset(Tick& offset);

        const std::string& name() const { return genName; }

        void exit();

        bool readNextWindow();

        template<typename T> void addDepsOnParent(GraphNode *new_node,
                                                    T& dep_array,
                                                    uint8_t& num_dep);

        void execute();

        PacketPtr executeMemReq(GraphNode* node_ptr);

        void addToSortedReadyList(NodeSeqNum seq_num, Tick exec_tick);

        void printReadyList();

        void completeMemAccess(PacketPtr pkt);

        bool isExecComplete() const { return execComplete; }

        bool checkAndIssue(const GraphNode* node_ptr, bool first = true);

        uint64_t getMicroOpCount() const { return trace.getMicroOpCount(); }

        void regStats();

      private:

        TraceCPU& owner;

        MasterPort& port;

        const MasterID masterID;

        InputStream trace;

        std::string genName;

        PacketPtr retryPkt;

        bool traceComplete;

        bool nextRead;

        bool execComplete;

        const uint32_t windowSize;

        HardwareResource hwResource;

        std::unordered_map<NodeSeqNum, GraphNode*> depGraph;

        std::queue<const GraphNode*> depFreeQueue;

        std::list<ReadyNode> readyList;

        Stats::Scalar maxDependents;
        Stats::Scalar maxReadyListSize;
        Stats::Scalar numSendAttempted;
        Stats::Scalar numSendSucceeded;
        Stats::Scalar numSendFailed;
        Stats::Scalar numRetrySucceeded;
        Stats::Scalar numSplitReqs;
        Stats::Scalar numSOLoads;
        Stats::Scalar numSOStores;
        Stats::Scalar dataLastTick;
    };

    FixedRetryGen icacheGen;

    ElasticDataGen dcacheGen;

    void schedIcacheNext();

    void schedDcacheNext();

    EventWrapper<TraceCPU, &TraceCPU::schedIcacheNext> icacheNextEvent;

    EventWrapper<TraceCPU, &TraceCPU::schedDcacheNext> dcacheNextEvent;

    void checkAndSchedExitEvent();

    bool oneTraceComplete;

    Tick traceOffset;

    static int numTraceCPUs;

    CountedExitEvent *execCompleteEvent;

    const bool enableEarlyExit;

    const uint64_t progressMsgInterval;

    /*
     * The progress msg threshold is kept updated to the next multiple of the
     * progress msg interval. As soon as the threshold is reached, an info
     * message is printed.
     */
    uint64_t progressMsgThreshold;

    Stats::Scalar numSchedDcacheEvent;
    Stats::Scalar numSchedIcacheEvent;

    Stats::Scalar numOps;
    Stats::Formula cpi;

  public:

    MasterPort &getInstPort() { return icachePort; }

    MasterPort &getDataPort() { return dcachePort; }

    void regStats();
};
#endif // __CPU_TRACE_TRACE_CPU_HH__