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TraceCPU::DcachePort Class Reference

DcachePort class that interfaces with L1 Data Cache. More...

#include <trace_cpu.hh>

Inheritance diagram for TraceCPU::DcachePort:
MasterPort BaseMasterPort Port

Public Member Functions

 DcachePort (TraceCPU *_cpu)
 Default constructor. More...
 
bool recvTimingResp (PacketPtr pkt)
 Receive the timing reponse and call dcacheRecvTimingResp() method of the dcacheGen to handle completing the load. More...
 
void recvTimingSnoopReq (PacketPtr pkt)
 Required functionally but do nothing. More...
 
void recvFunctionalSnoop (PacketPtr pkt)
 Required functionally but do nothing. More...
 
void recvReqRetry ()
 Handle a retry signalled by the cache if data access failed in the first attempt. More...
 
bool isSnooping () const
 Required functionally. More...
 
- Public Member Functions inherited from MasterPort
 MasterPort (const std::string &name, MemObject *owner, PortID id=InvalidPortID)
 Master port. More...
 
virtual ~MasterPort ()
 
void bind (BaseSlavePort &slave_port)
 Bind this master port to a slave port. More...
 
void unbind ()
 Unbind this master port and the associated slave port. More...
 
Tick sendAtomic (PacketPtr pkt)
 Send an atomic request packet, where the data is moved and the state is updated in zero time, without interleaving with other memory accesses. More...
 
void sendFunctional (PacketPtr pkt)
 Send a functional request packet, where the data is instantly updated everywhere in the memory system, without affecting the current state of any block or moving the block. More...
 
bool sendTimingReq (PacketPtr pkt)
 Attempt to send a timing request to the slave port by calling its corresponding receive function. More...
 
bool sendTimingSnoopResp (PacketPtr pkt)
 Attempt to send a timing snoop response packet to the slave port by calling its corresponding receive function. More...
 
virtual void sendRetryResp ()
 Send a retry to the slave port that previously attempted a sendTimingResp to this master port and failed. More...
 
AddrRangeList getAddrRanges () const
 Get the address ranges of the connected slave port. More...
 
void printAddr (Addr a)
 Inject a PrintReq for the given address to print the state of that address throughout the memory system. More...
 
- Public Member Functions inherited from BaseMasterPort
BaseSlavePortgetSlavePort () const
 
bool isConnected () const
 
- Public Member Functions inherited from Port
const std::string name () const
 Return port name (for DPRINTF). More...
 
PortID getId () const
 Get the port id. More...
 

Private Attributes

TraceCPUowner
 

Additional Inherited Members

- Protected Member Functions inherited from MasterPort
virtual Tick recvAtomicSnoop (PacketPtr pkt)
 Receive an atomic snoop request packet from the slave port. More...
 
virtual void recvRetrySnoopResp ()
 Called by the slave port if sendTimingSnoopResp was called on this master port (causing recvTimingSnoopResp to be called on the slave port) and was unsuccesful. More...
 
virtual void recvRangeChange ()
 Called to receive an address range change from the peer slave port. More...
 
- Protected Member Functions inherited from BaseMasterPort
 BaseMasterPort (const std::string &name, MemObject *owner, PortID id=InvalidPortID)
 
virtual ~BaseMasterPort ()
 
- Protected Member Functions inherited from Port
 Port (const std::string &_name, MemObject &_owner, PortID _id)
 Abstract base class for ports. More...
 
virtual ~Port ()
 Virtual destructor due to inheritance. More...
 
- Protected Attributes inherited from BaseMasterPort
BaseSlavePort_baseSlavePort
 
- Protected Attributes inherited from Port
const PortID id
 A numeric identifier to distinguish ports in a vector, and set to InvalidPortID in case this port is not part of a vector. More...
 
MemObjectowner
 A reference to the MemObject that owns this port. More...
 

Detailed Description

DcachePort class that interfaces with L1 Data Cache.

Definition at line 268 of file trace_cpu.hh.

Constructor & Destructor Documentation

TraceCPU::DcachePort::DcachePort ( TraceCPU _cpu)
inline

Default constructor.

Definition at line 273 of file trace_cpu.hh.

Member Function Documentation

bool TraceCPU::DcachePort::isSnooping ( ) const
inlinevirtual

Required functionally.

Returns
true since we have to snoop

Reimplemented from MasterPort.

Definition at line 316 of file trace_cpu.hh.

void TraceCPU::DcachePort::recvFunctionalSnoop ( PacketPtr  pkt)
inlinevirtual

Required functionally but do nothing.

Parameters
pktPointer to packet received

Reimplemented from MasterPort.

Definition at line 302 of file trace_cpu.hh.

void TraceCPU::DcachePort::recvReqRetry ( )
virtual

Handle a retry signalled by the cache if data access failed in the first attempt.

Implements MasterPort.

Definition at line 1262 of file trace_cpu.cc.

References TraceCPU::dcacheRetryRecvd(), and TraceCPU::ElasticDataGen::owner.

bool TraceCPU::DcachePort::recvTimingResp ( PacketPtr  pkt)
virtual

Receive the timing reponse and call dcacheRecvTimingResp() method of the dcacheGen to handle completing the load.

Parameters
pktPointer to packet received
Returns
true

Implements MasterPort.

Definition at line 1248 of file trace_cpu.cc.

References TraceCPU::dcacheRecvTimingResp(), TraceCPU::ElasticDataGen::owner, and Packet::req.

void TraceCPU::DcachePort::recvTimingSnoopReq ( PacketPtr  pkt)
inlinevirtual

Required functionally but do nothing.

Parameters
pktPointer to packet received

Reimplemented from MasterPort.

Definition at line 294 of file trace_cpu.hh.

Member Data Documentation

TraceCPU* TraceCPU::DcachePort::owner
private

Definition at line 319 of file trace_cpu.hh.


The documentation for this class was generated from the following files:

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