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InvalidateGenerator.cc
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1 /*
2  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3  * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
4  * All rights reserved.
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29 
31 
32 #include "base/trace.hh"
35 #include "debug/DirectedTest.hh"
36 
39 {
40  //
41  // First, issue loads to bring the block into S state
42  //
43  m_status = InvalidateGeneratorStatus_Load_Waiting;
46  m_address = 0x0;
47  m_addr_increment_size = p->addr_increment_size;
48 }
49 
51 {
52 }
53 
54 bool
56 {
57  MasterPort* port;
58  Request::Flags flags;
59  PacketPtr pkt;
60  Packet::Command cmd;
61 
62  // For simplicity, requests are assumed to be 1 byte-sized
63  Request *req = new Request(m_address, 1, flags, masterId);
64 
65  //
66  // Based on the current state, issue a load or a store
67  //
68  if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
69  DPRINTF(DirectedTest, "initiating read\n");
70  cmd = MemCmd::ReadReq;
72  pkt = new Packet(req, cmd);
73  } else if (m_status == InvalidateGeneratorStatus_Inv_Waiting) {
74  DPRINTF(DirectedTest, "initiating invalidating write\n");
75  cmd = MemCmd::WriteReq;
77  pkt = new Packet(req, cmd);
78  } else {
79  panic("initiate was unexpectedly called\n");
80  }
81  pkt->allocate();
82 
83  if (port->sendTimingReq(pkt)) {
84  DPRINTF(DirectedTest, "initiating request - successful\n");
85  if (m_status == InvalidateGeneratorStatus_Load_Waiting) {
86  m_status = InvalidateGeneratorStatus_Load_Pending;
87  } else {
88  m_status = InvalidateGeneratorStatus_Inv_Pending;
89  }
90  return true;
91  } else {
92  // If the packet did not issue, must delete
93  // Note: No need to delete the data, the packet destructor
94  // will delete it
95  delete pkt->req;
96  delete pkt;
97 
98  DPRINTF(DirectedTest, "failed to issue request - sequencer not ready\n");
99  return false;
100  }
101 }
102 
103 void
105 {
106  assert(m_address == address);
107 
108  if (m_status == InvalidateGeneratorStatus_Load_Pending) {
109  assert(m_active_read_node == proc);
111  //
112  // Once all cpus have the block in S state, issue the invalidate
113  //
115  m_status = InvalidateGeneratorStatus_Inv_Waiting;
116  m_active_read_node = 0;
117  } else {
118  m_status = InvalidateGeneratorStatus_Load_Waiting;
119  }
120  } else if (m_status == InvalidateGeneratorStatus_Inv_Pending) {
121  assert(m_active_inv_node == proc);
123  if (m_active_inv_node == m_num_cpus) {
125  m_active_inv_node = 0;
126  }
127  //
128  // Invalidate completed, send that info to the tester and restart
129  // the cycle
130  //
132  m_status = InvalidateGeneratorStatus_Load_Waiting;
133  }
134 
135 }
136 
138 InvalidateGeneratorParams::create()
139 {
140  return new InvalidateGenerator(this);
141 }
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
Definition: port.hh:167
#define DPRINTF(x,...)
Definition: trace.hh:212
MasterPort * getCpuPort(int idx)
#define panic(...)
Definition: misc.hh:153
void performCallback(uint32_t proc, Addr address)
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the slave port by calling its corresponding receive function...
Definition: port.cc:180
InvalidateGeneratorStatus m_status
InvalidateGenerator(const Params *p)
DirectedGeneratorParams Params
const RequestPtr req
A pointer to the original request.
Definition: packet.hh:304
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:245
RubyDirectedTester * m_directed_tester
Command
List of all commands associated with a packet.
Definition: packet.hh:81
Bitfield< 0 > p
void allocate()
Allocate memory for the packet.
Definition: packet.hh:1082
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:102

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