gem5
 All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Groups Pages
RubyDirectedTester.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2012 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
15  * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
16  * All rights reserved.
17  *
18  * Redistribution and use in source and binary forms, with or without
19  * modification, are permitted provided that the following conditions are
20  * met: redistributions of source code must retain the above copyright
21  * notice, this list of conditions and the following disclaimer;
22  * redistributions in binary form must reproduce the above copyright
23  * notice, this list of conditions and the following disclaimer in the
24  * documentation and/or other materials provided with the distribution;
25  * neither the name of the copyright holders nor the names of its
26  * contributors may be used to endorse or promote products derived from
27  * this software without specific prior written permission.
28  *
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40  */
41 
43 
44 #include "base/trace.hh"
46 #include "debug/DirectedTest.hh"
47 #include "sim/sim_exit.hh"
48 
50  : MemObject(p), directedStartEvent(this),
51  m_requests_to_complete(p->requests_to_complete),
52  generator(p->generator)
53 {
55 
56  // create the ports
57  for (int i = 0; i < p->port_cpuPort_connection_count; ++i) {
58  ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
59  this, i));
60  }
61 
62  // add the check start event to the event queue
64 }
65 
67 {
68  for (int i = 0; i < ports.size(); i++)
69  delete ports[i];
70 }
71 
72 void
74 {
75  assert(ports.size() > 0);
77 }
78 
80 RubyDirectedTester::getMasterPort(const std::string &if_name, PortID idx)
81 {
82  if (if_name != "cpuPort") {
83  // pass it along to our super class
84  return MemObject::getMasterPort(if_name, idx);
85  } else {
86  if (idx >= static_cast<int>(ports.size())) {
87  panic("RubyDirectedTester::getMasterPort: unknown index %d\n", idx);
88  }
89 
90  return *ports[idx];
91  }
92 }
93 
94 bool
96 {
97  tester->hitCallback(id, pkt->getAddr());
98 
99  //
100  // Now that the tester has completed, delete the packet, then return
101  //
102  delete pkt->req;
103  delete pkt;
104  return true;
105 }
106 
107 MasterPort*
109 {
110  assert(idx >= 0 && idx < ports.size());
111 
112  return ports[idx];
113 }
114 
115 void
117 {
118  DPRINTF(DirectedTest,
119  "completed request for proc: %d addr: 0x%x\n",
120  proc,
121  addr);
122 
123  generator->performCallback(proc, addr);
125 }
126 
127 void
129 {
131  if (!generator->initiate()) {
133  }
134  } else {
135  exitSimLoop("Ruby DirectedTester completed");
136  }
137 }
138 
140 RubyDirectedTesterParams::create()
141 {
142  return new RubyDirectedTester(this);
143 }
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
Definition: port.hh:167
#define DPRINTF(x,...)
Definition: trace.hh:212
Bitfield< 7 > i
Definition: miscregs.hh:1378
MasterPort * getCpuPort(int idx)
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
#define panic(...)
Definition: misc.hh:153
virtual void performCallback(uint32_t proc, Addr address)=0
ip6_addr_t addr
Definition: inet.hh:335
void setDirectedTester(RubyDirectedTester *directed_tester)
unsigned int NodeID
Definition: TypeDefines.hh:34
Tick curTick()
The current simulated tick.
Definition: core.hh:47
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
const RequestPtr req
A pointer to the original request.
Definition: packet.hh:304
virtual BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
std::vector< MasterPort * > ports
virtual bool initiate()=0
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:245
RubyDirectedTesterParams Params
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
Definition: sim_events.cc:83
virtual const std::string name() const
Definition: sim_object.hh:117
DirectedStartEvent directedStartEvent
The MemObject class extends the ClockedObject with accessor functions to get its master and slave por...
Definition: mem_object.hh:60
A BaseMasterPort is a protocol-agnostic master port, responsible only for the structural connection t...
Definition: port.hh:115
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the slave port.
void schedule(Event &event, Tick when)
Definition: eventq.hh:728
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:181
DirectedGenerator * generator
RubyDirectedTester(const Params *p)
Bitfield< 0 > p
void hitCallback(NodeID proc, Addr addr)
virtual BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.
Definition: mem_object.cc:52
Addr getAddr() const
Definition: packet.hh:639

Generated on Fri Jun 9 2017 13:03:44 for gem5 by doxygen 1.8.6