46 #include "debug/DirectedTest.hh"
51 m_requests_to_complete(p->requests_to_complete),
52 generator(p->generator)
57 for (
int i = 0;
i < p->port_cpuPort_connection_count; ++
i) {
68 for (
int i = 0;
i <
ports.size();
i++)
75 assert(
ports.size() > 0);
82 if (if_name !=
"cpuPort") {
86 if (idx >= static_cast<int>(
ports.size())) {
87 panic(
"RubyDirectedTester::getMasterPort: unknown index %d\n", idx);
110 assert(idx >= 0 && idx <
ports.size());
119 "completed request for proc: %d addr: 0x%x\n",
140 RubyDirectedTesterParams::create()
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
RubyDirectedTester * tester
MasterPort * getCpuPort(int idx)
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
virtual void performCallback(uint32_t proc, Addr address)=0
void setDirectedTester(RubyDirectedTester *directed_tester)
uint64_t m_requests_completed
Tick curTick()
The current simulated tick.
std::string csprintf(const char *format, const Args &...args)
const RequestPtr req
A pointer to the original request.
virtual BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
std::vector< MasterPort * > ports
virtual bool initiate()=0
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
RubyDirectedTesterParams Params
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
virtual const std::string name() const
DirectedStartEvent directedStartEvent
The MemObject class extends the ClockedObject with accessor functions to get its master and slave por...
A BaseMasterPort is a protocol-agnostic master port, responsible only for the structural connection t...
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the slave port.
void schedule(Event &event, Tick when)
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
DirectedGenerator * generator
RubyDirectedTester(const Params *p)
uint64_t m_requests_to_complete
void hitCallback(NodeID proc, Addr addr)
virtual BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.