48 #include "debug/MemCheckerMonitor.hh"
54 masterPort(
name() +
"-master", *this),
55 slavePort(
name() +
"-slave", *this),
56 warnOnly(params->warn_only),
57 memchecker(params->memchecker)
64 MemCheckerMonitorParams::create()
74 fatal(
"Communication monitor is not connected on both sides.\n");
80 if (if_name ==
"master" || if_name ==
"mem_side") {
90 if (if_name ==
"slave" || if_name ==
"cpu_side") {
111 "Forwarded functional access: addr = %#llx, size = %d\n",
127 "Received functional snoop: addr = %#llx, size = %d\n",
134 assert(
false &&
"Atomic not supported");
141 assert(
false &&
"Atomic not supported");
157 bool is_write = pkt->
isWrite();
161 std::unique_ptr<uint8_t[]> pkt_data;
164 if (expects_response && is_write) {
168 pkt_data.reset(
new uint8_t[size]);
169 memcpy(pkt_data.get(), pkt->
getConstPtr<uint8_t*>(), size);
176 if (expects_response && (is_read || is_write)) {
185 if (!successful && expects_response && (is_read || is_write)) {
189 if (successful && expects_response) {
209 "Forwarded read request: serial = %d, addr = %#llx, "
212 }
else if (is_write) {
221 "Forwarded write request: serial = %d, addr = %#llx, "
226 "Forwarded non read/write request: addr = %#llx\n", addr);
228 }
else if (successful) {
230 "Forwarded request marked for cache response: addr = %#llx\n",
246 bool is_write = pkt->
isWrite();
250 std::unique_ptr<uint8_t[]> pkt_data;
257 pkt_data.reset(
new uint8_t[size]);
258 memcpy(pkt_data.get(), pkt->
getConstPtr<uint8_t*>(), size);
261 if (is_read || is_write) {
267 "Monitor got a response without monitor sender state\n");
281 "Received read response: serial = %d, addr = %#llx, "
283 received_state->
serial, addr, size);
292 warn(
"%s: read of %#llx @ cycle %d failed:\n%s\n",
300 delete received_state;
301 }
else if (is_write) {
303 "Received write response: serial = %d, addr = %#llx, "
305 received_state->
serial, addr, size);
307 if (is_failed_LLSC) {
319 delete received_state;
322 "Received non read/write response: addr = %#llx\n", addr);
324 }
else if (is_read || is_write) {
~MemCheckerMonitor()
Destructor.
AddrRangeList getAddrRanges() const
Tick recvAtomicSnoop(PacketPtr pkt)
bool recvTimingReq(PacketPtr pkt)
void completeWrite(Serial serial, Tick complete, Addr addr, size_t size)
Completes a previously started write transaction.
const std::string & name()
void abortWrite(Serial serial, Addr addr, size_t size)
Aborts a previously started write transaction.
bool sendTimingSnoopResp(PacketPtr pkt)
Attempt to send a timing snoop response packet to the slave port by calling its corresponding receive...
bool completeRead(Serial serial, Tick complete, Addr addr, size_t size, uint8_t *data)
Completes a previously started read transaction.
Tick sendAtomicSnoop(PacketPtr pkt)
Send an atomic snoop request packet, where the data is moved and the state is updated in zero time...
uint64_t getExtraData() const
Accessor function for store conditional return value.
panic_if(!root,"Invalid expression\n")
Tick recvAtomic(PacketPtr pkt)
void sendFunctionalSnoop(PacketPtr pkt)
Send a functional snoop request packet, where the data is instantly updated everywhere in the memory ...
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the slave port by calling its corresponding receive function...
virtual BaseSlavePort & getSlavePort(const std::string &if_name, PortID idx=InvalidPortID)
Get a slave port with a given name and index.
virtual void sendRetryResp()
Send a retry to the slave port that previously attempted a sendTimingResp to this master port and fai...
A BaseSlavePort is a protocol-agnostic slave port, responsible only for the structural connection to ...
uint64_t Serial
The Serial type is used to be able to uniquely identify a transaction as it passes through the system...
MemCheckerMonitor(Params *params)
Constructor based on the Python params.
MonitorMasterPort masterPort
Instance of master port, facing the memory side.
bool isSnooping() const
Find out if the peer master port is snooping or not.
bool sendTimingResp(PacketPtr pkt)
Attempt to send a timing response to the master port by calling its corresponding receive function...
Tick curTick()
The current simulated tick.
SenderState * predecessor
uint64_t Tick
Tick count type.
void reset()
Resets the entire checker.
const std::string & getErrorMessage() const
In completeRead, if an error is encountered, this does not print nor cause an error, but instead should be handled by the caller.
const RequestPtr req
A pointer to the original request.
MemCheckerMonitorParams Params
Parameters of memchecker monitor.
bool needsResponse() const
void recvFunctionalSnoop(PacketPtr pkt)
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
bool cacheResponding() const
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Implements a MemChecker monitor, to be inserted between two ports.
MonitorSlavePort slavePort
Instance of slave port, i.e.
virtual BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.
void sendRangeChange() const
Called by the owner to send a range change.
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
virtual BaseSlavePort & getSlavePort(const std::string &if_name, PortID idx=InvalidPortID)
Get a slave port with a given name and index.
virtual const std::string name() const
AddrRangeList getAddrRanges() const
Get the address ranges of the connected slave port.
void sendRetryReq()
Send a retry to the master port that previously attempted a sendTimingReq to this slave port and fail...
SenderState * senderState
This packet's sender state.
void recvTimingSnoopReq(PacketPtr pkt)
The MemObject class extends the ClockedObject with accessor functions to get its master and slave por...
A BaseMasterPort is a protocol-agnostic master port, responsible only for the structural connection t...
Serial startWrite(Tick start, Addr addr, size_t size, const uint8_t *data)
Starts a write transaction.
void sendTimingSnoopReq(PacketPtr pkt)
Attempt to send a timing snoop request packet to the master port by calling its corresponding receive...
bool recvTimingSnoopResp(PacketPtr pkt)
void recvFunctional(PacketPtr pkt)
void pushSenderState(SenderState *sender_state)
Push a new sender state to the packet and make the current sender state the predecessor of the new on...
SenderState * popSenderState()
Pop the top of the state stack and return a pointer to it.
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
const T * getConstPtr() const
bool recvTimingResp(PacketPtr pkt)
Tick sendAtomic(PacketPtr pkt)
Send an atomic request packet, where the data is moved and the state is updated in zero time...
Serial startRead(Tick start, Addr addr, size_t size)
Starts a read transaction.
virtual BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.
void sendFunctional(PacketPtr pkt)
Send a functional request packet, where the data is instantly updated everywhere in the memory system...
MemChecker::Serial serial