42 #ifndef __MEM_MEM_CHECKER_MONITOR_HH__
43 #define __MEM_MEM_CHECKER_MONITOR_HH__
48 #include "params/MemCheckerMonitor.hh"
59 typedef MemCheckerMonitorParams
Params;
240 #endif //__MEM_MEM_CHECKER_MONITOR_HH__
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
~MemCheckerMonitor()
Destructor.
AddrRangeList getAddrRanges() const
Tick recvAtomicSnoop(PacketPtr pkt)
bool recvTimingReq(PacketPtr pkt)
MonitorSlavePort(const std::string &_name, MemCheckerMonitor &_mon)
const PortID InvalidPortID
MemCheckerMonitorSenderState(MemChecker::Serial _serial)
Tick recvAtomic(PacketPtr pkt)
bool recvTimingReq(PacketPtr pkt)
Receive a timing request from the master port.
A SlavePort is a specialisation of a port.
This is the master port of the communication monitor.
A BaseSlavePort is a protocol-agnostic slave port, responsible only for the structural connection to ...
Declaration of Statistics objects.
uint64_t Serial
The Serial type is used to be able to uniquely identify a transaction as it passes through the system...
MemCheckerMonitor(Params *params)
Constructor based on the Python params.
const Params * params() const
MonitorMasterPort masterPort
Instance of master port, facing the memory side.
uint64_t Tick
Tick count type.
bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the slave port.
MemCheckerMonitorParams Params
Parameters of memchecker monitor.
void recvTimingSnoopReq(PacketPtr pkt)
Receive a timing snoop request from the slave port.
Tick recvAtomicSnoop(PacketPtr pkt)
Receive an atomic snoop request packet from the slave port.
AddrRangeList getAddrRanges() const
Get a list of the non-overlapping address ranges the owner is responsible for.
void recvFunctionalSnoop(PacketPtr pkt)
void recvRespRetry()
Called by the master port if sendTimingResp was called on this slave port (causing recvTimingResp to ...
Tick recvAtomic(PacketPtr pkt)
Receive an atomic request packet from the master port.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
void recvRangeChange()
Called to receive an address range change from the peer slave port.
Implements a MemChecker monitor, to be inserted between two ports.
MonitorSlavePort slavePort
Instance of slave port, i.e.
virtual BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.
bool recvTimingSnoopResp(PacketPtr pkt)
Receive a timing snoop response from the master port.
A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a MemObject that sees the packet.
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
bool isSnooping() const
Determine if this master port is snooping or not.
virtual BaseSlavePort & getSlavePort(const std::string &if_name, PortID idx=InvalidPortID)
Get a slave port with a given name and index.
void recvReqRetry()
Called by the slave port if sendTimingReq was called on this master port (causing recvTimingReq to be...
void recvFunctionalSnoop(PacketPtr pkt)
Receive a functional snoop request packet from the slave port.
void recvTimingSnoopReq(PacketPtr pkt)
The MemObject class extends the ClockedObject with accessor functions to get its master and slave por...
A BaseMasterPort is a protocol-agnostic master port, responsible only for the structural connection t...
MonitorMasterPort(const std::string &_name, MemCheckerMonitor &_mon)
const SimObjectParams * _params
Cached copy of the object parameters.
bool recvTimingSnoopResp(PacketPtr pkt)
void recvFunctional(PacketPtr pkt)
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
bool recvTimingResp(PacketPtr pkt)
void recvFunctional(PacketPtr pkt)
Receive a functional request packet from the master port.
This is the slave port of the communication monitor.
MemChecker::Serial serial