42 #include "debug/GarnetSyntheticTraffic.hh"
58 tester->completeRequest(pkt);
71 if (!cachePort.sendTimingReq(pkt)) {
80 cachePort(
"GarnetSyntheticTraffic", this),
83 blockSizeBits(p->block_offset),
84 numDestinations(p->num_dest),
85 simCycles(p->sim_cycles),
86 numPacketsMax(p->num_packets_max),
88 singleSender(p->single_sender),
89 singleDest(p->single_dest),
90 trafficType(p->traffic_type),
93 precision(p->precision),
94 responseLimit(p->response_limit),
115 if (if_name ==
"test")
134 "Completed injection of %s packet for address %x\n",
135 pkt->
isWrite() ?
"write" :
"read\n",
156 bool sendAllowedThisCycle;
157 double injRange = pow((
double) 10, (
double)
precision);
159 if (trySending <
injRate*injRange)
160 sendAllowedThisCycle =
true;
162 sendAllowedThisCycle =
false;
165 if (sendAllowedThisCycle) {
166 bool senderEnable =
true;
169 senderEnable =
false;
172 senderEnable =
false;
191 int radix = (int) sqrt(num_destinations);
196 int src_x =
id%radix;
197 int src_y =
id/radix;
205 dest_x = radix - src_x - 1;
206 dest_y = radix - src_y - 1;
207 destination = dest_y*radix + dest_x;
209 unsigned int straight = source;
210 unsigned int reverse = source & 1;
212 int num_bits = (int) log2(num_destinations);
214 for (
int i = 1;
i < num_bits;
i++)
218 reverse |= (straight & 1);
220 destination = reverse;
223 destination = source/2;
225 destination = ((source/2) + (num_destinations/2));
227 dest_x = (src_x + 1) % radix;
229 destination = dest_y*radix + dest_x;
231 if (source < num_destinations/2)
232 destination = source*2;
234 destination = (source*2 - num_destinations + 1);
238 destination = dest_y*radix + dest_x;
240 dest_x = (src_x + (int) ceil(radix/2) - 1) % radix;
242 destination = dest_y*radix + dest_x;
253 unsigned access_size = 1;
289 if (injReqType < 0 || injReqType > 2)
295 if (injReqType == 0) {
299 }
else if (injReqType == 1) {
317 "Generated packet with destination %d, embedded in address %x\n",
321 pkt->dataDynamic(
new uint8_t[req->
getSize()]);
322 pkt->senderState = NULL;
356 GarnetSyntheticTrafficParams::create()
Cycles is a wrapper class for representing cycle counts, i.e.
const std::string & name()
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
bool scheduled() const
Determine if the current event is scheduled.
void completeRequest(PacketPtr pkt)
GarnetSyntheticTraffic(const Params *p)
void setContext(ContextID context_id)
Set up Context numbers.
bool sendTimingReq(PacketPtr pkt)
Attempt to send a timing request to the slave port by calling its corresponding receive function...
Declaration of Statistics objects.
std::enable_if< std::is_integral< T >::value, T >::type random()
Use the SFINAE idiom to choose an implementation based on whether the type is integral or floating po...
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Tick curTick()
The current simulated tick.
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the slave port.
void sendPkt(PacketPtr pkt)
void printAddr(Addr a)
Print state of address in memory system via PrintReq (for debugging).
const RequestPtr req
A pointer to the original request.
GarnetSyntheticTrafficParams Params
std::map< std::string, TrafficType > trafficStringToEnum
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
void printAddr(Addr a)
Inject a PrintReq for the given address to print the state of that address throughout the memory syst...
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
void exitSimLoop(const std::string &message, int exit_code, Tick when, Tick repeat, bool serialize)
Schedule an event to exit the simulation loop (returning to Python) at the end of the current cycle (...
virtual const std::string name() const
Declaration of the Packet class.
The request was an instruction fetch.
virtual BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.
The MemObject class extends the ClockedObject with accessor functions to get its master and slave por...
A BaseMasterPort is a protocol-agnostic master port, responsible only for the structural connection t...
void schedule(Event &event, Tick when)
virtual void recvReqRetry()
Called by the slave port if sendTimingReq was called on this master port (causing recvTimingReq to be...
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
const Cycles responseLimit
Command
List of all commands associated with a packet.
void setPaddr(Addr paddr)
Set just the physical address.
virtual BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.
ProbePointArg< PacketInfo > Packet
Packet probe point.