31 #ifndef __CPU_GARNET_SYNTHETIC_TRAFFIC_HH__
32 #define __CPU_GARNET_SYNTHETIC_TRAFFIC_HH__
39 #include "params/GarnetSyntheticTraffic.hh"
59 typedef GarnetSyntheticTrafficParams
Params;
87 return "GarnetSyntheticTraffic tick";
162 #endif // __CPU_GARNET_SYNTHETIC_TRAFFIC_HH__
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
TickEvent(GarnetSyntheticTraffic *c)
Cycles is a wrapper class for representing cycle counts, i.e.
GarnetSyntheticTraffic * tester
const PortID InvalidPortID
static const Priority CPU_Tick_Pri
CPU ticks must come after other associated CPU events (such as writebacks).
void completeRequest(PacketPtr pkt)
GarnetSyntheticTraffic(const Params *p)
Declaration of Statistics objects.
GarnetSyntheticTrafficSenderState(uint8_t *_data)
Constructor.
virtual void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
virtual bool recvTimingResp(PacketPtr pkt)
Receive a timing response from the slave port.
virtual const char * description() const
Return a C string describing the event.
void sendPkt(PacketPtr pkt)
void printAddr(Addr a)
Print state of address in memory system via PrintReq (for debugging).
uint64_t Tick
Tick count type.
CpuPort(const std::string &_name, GarnetSyntheticTraffic *_tester)
GarnetSyntheticTrafficParams Params
std::map< std::string, TrafficType > trafficStringToEnum
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
A virtual base opaque structure used to hold state associated with the packet (e.g., an MSHR), specific to a MemObject that sees the packet.
friend class MemCompleteEvent
GarnetSyntheticTraffic * cpu
virtual BaseMasterPort & getMasterPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a master port with a given name and index.
The MemObject class extends the ClockedObject with accessor functions to get its master and slave por...
A BaseMasterPort is a protocol-agnostic master port, responsible only for the structural connection t...
virtual void recvReqRetry()
Called by the slave port if sendTimingReq was called on this master port (causing recvTimingReq to be...
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
const Cycles responseLimit