mshr.hh

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/*
 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
 * All rights reserved.
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2002-2005 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Erik Hallnor
 */

#ifndef __MEM_CACHE_MSHR_HH__
#define __MEM_CACHE_MSHR_HH__

#include <list>

#include "base/printable.hh"
#include "mem/cache/queue_entry.hh"

class Cache;

class MSHR : public QueueEntry, public Printable
{

    template<typename Entry>
    friend class Queue;
    friend class MSHRQueue;

  private:

    bool downstreamPending;

    bool pendingModified;

    bool postInvalidate;

    bool postDowngrade;

  public:

    bool isForward;

    class Target {
      public:

        enum Source {
            FromCPU,
            FromSnoop,
            FromPrefetcher
        };

        const Tick recvTime;  
        const Tick readyTime; 
        const Counter order;  
        const PacketPtr pkt;  
        const Source source;  

        bool markedPending;

        const bool allocOnFill;   

        Target(PacketPtr _pkt, Tick _readyTime, Counter _order,
               Source _source, bool _markedPending, bool alloc_on_fill)
            : recvTime(curTick()), readyTime(_readyTime), order(_order),
              pkt(_pkt), source(_source), markedPending(_markedPending),
              allocOnFill(alloc_on_fill)
        {}
    };

    class TargetList : public std::list<Target> {

      public:
        bool needsWritable;
        bool hasUpgrade;
        bool allocOnFill;

        TargetList();

        void updateFlags(PacketPtr pkt, Target::Source source,
                         bool alloc_on_fill);

        void resetFlags() { needsWritable = hasUpgrade = allocOnFill = false; }

        void populateFlags();

        bool isReset() const {
            return !needsWritable && !hasUpgrade && !allocOnFill;
        }

        void add(PacketPtr pkt, Tick readyTime, Counter order,
                 Target::Source source, bool markPending,
                 bool alloc_on_fill);

        void replaceUpgrades();

        void clearDownstreamPending();
        bool checkFunctional(PacketPtr pkt);
        void print(std::ostream &os, int verbosity,
                   const std::string &prefix) const;
    };

    typedef std::list<MSHR *> List;
    typedef List::iterator Iterator;

    bool needsWritable() const { return targets.needsWritable; }

    bool isPendingModified() const {
        assert(inService); return pendingModified;
    }

    bool hasPostInvalidate() const {
        assert(inService); return postInvalidate;
    }

    bool hasPostDowngrade() const {
        assert(inService); return postDowngrade;
    }

    bool sendPacket(Cache &cache);

    bool allocOnFill() const {
        return targets.allocOnFill;
    }
  private:

    Iterator readyIter;

    Iterator allocIter;

    TargetList targets;

    TargetList deferredTargets;

  public:

    void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
                  Tick when_ready, Counter _order, bool alloc_on_fill);

    void markInService(bool pending_modified_resp);

    void clearDownstreamPending();

    void deallocate();

    void allocateTarget(PacketPtr target, Tick when, Counter order,
                        bool alloc_on_fill);
    bool handleSnoop(PacketPtr target, Counter order);

    MSHR();

    int getNumTargets() const
    { return targets.size() + deferredTargets.size(); }

    TargetList extractServiceableTargets(PacketPtr pkt);

    bool hasTargets() const { return !targets.empty(); }

    Target *getTarget()
    {
        assert(hasTargets());
        return &targets.front();
    }

    void popTarget()
    {
        targets.pop_front();
    }

    bool promoteDeferredTargets();

    void promoteWritable();

    bool checkFunctional(PacketPtr pkt);

    void print(std::ostream &os,
               int verbosity = 0,
               const std::string &prefix = "") const;
    std::string print() const;
};

#endif // __MEM_CACHE_MSHR_HH__