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gem5
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Declares a basic cache interface BaseCache. More...
#include <algorithm>#include <list>#include <string>#include <vector>#include "base/misc.hh"#include "base/statistics.hh"#include "base/trace.hh"#include "base/types.hh"#include "debug/Cache.hh"#include "debug/CachePort.hh"#include "mem/cache/mshr_queue.hh"#include "mem/cache/write_queue.hh"#include "mem/mem_object.hh"#include "mem/packet.hh"#include "mem/qport.hh"#include "mem/request.hh"#include "params/BaseCache.hh"#include "sim/eventq.hh"#include "sim/full_system.hh"#include "sim/sim_exit.hh"#include "sim/system.hh"Go to the source code of this file.
Classes | |
| class | BaseCache |
| A basic cache interface. More... | |
| class | BaseCache::CacheMasterPort |
| A cache master port is used for the memory-side port of the cache, and in addition to the basic timing port that only sends response packets through a transmit list, it also offers the ability to schedule and send request packets (requests & writebacks). More... | |
| class | BaseCache::CacheSlavePort |
| A cache slave port is used for the CPU-side port of the cache, and it is basically a simple timing port that uses a transmit list for responses to the CPU (or connected master). More... | |