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tsunami_io.cc
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1 /*
2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
3  * All rights reserved.
4  *
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6  * modification, are permitted provided that the following conditions are
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8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  * Authors: Ali Saidi
29  * Andrew Schultz
30  * Miguel Serrano
31  */
32 
37 #include "dev/alpha/tsunami_io.hh"
38 
39 #include <sys/time.h>
40 
41 #include <deque>
42 #include <string>
43 #include <vector>
44 
45 #include "base/time.hh"
46 #include "base/trace.hh"
47 #include "config/the_isa.hh"
48 #include "debug/Tsunami.hh"
49 #include "dev/alpha/tsunami.hh"
51 #include "dev/alpha/tsunamireg.h"
52 #include "dev/rtcreg.h"
53 #include "mem/packet.hh"
54 #include "mem/packet_access.hh"
55 #include "mem/port.hh"
56 #include "sim/system.hh"
57 
58 // clang complains about std::set being overloaded with Packet::set if
59 // we open up the entire namespace std
60 using std::string;
61 using std::ostream;
62 
63 //Should this be AlphaISA?
64 using namespace TheISA;
65 
66 TsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p)
67  : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency),
68  tsunami(p->tsunami)
69 {
70 }
71 
73  : BasicPioDevice(p, 0x100), tsunami(p->tsunami),
74  pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p)
75 {
76  // set the back pointer from tsunami to myself
77  tsunami->io = this;
78 
79  timerData = 0;
80  picr = 0;
81  picInterrupting = false;
82 }
83 
84 Tick
86 {
87  return SimClock::Frequency / params()->frequency;
88 }
89 
90 Tick
92 {
93  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
94 
95  Addr daddr = pkt->getAddr() - pioAddr;
96 
97  DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(),
98  pkt->getSize(), daddr);
99 
100  if (pkt->getSize() == sizeof(uint8_t)) {
101  switch(daddr) {
102  // PIC1 mask read
103  case TSDEV_PIC1_MASK:
104  pkt->set(~mask1);
105  break;
106  case TSDEV_PIC2_MASK:
107  pkt->set(~mask2);
108  break;
109  case TSDEV_PIC1_ISR:
110  // !!! If this is modified 64bit case needs to be too
111  // Pal code has to do a 64 bit physical read because there is
112  // no load physical byte instruction
113  pkt->set(picr);
114  break;
115  case TSDEV_PIC2_ISR:
116  // PIC2 not implemnted... just return 0
117  pkt->set(0x00);
118  break;
119  case TSDEV_TMR0_DATA:
120  pkt->set(pitimer.readCounter(0));
121  break;
122  case TSDEV_TMR1_DATA:
123  pkt->set(pitimer.readCounter(1));
124  break;
125  case TSDEV_TMR2_DATA:
126  pkt->set(pitimer.readCounter(2));
127  break;
128  case TSDEV_RTC_DATA:
129  pkt->set(rtc.readData(rtcAddr));
130  break;
131  case TSDEV_CTRL_PORTB:
132  if (pitimer.outputHigh(2))
133  pkt->set(PORTB_SPKR_HIGH);
134  else
135  pkt->set(0x00);
136  break;
137  default:
138  panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize());
139  }
140  } else if (pkt->getSize() == sizeof(uint64_t)) {
141  if (daddr == TSDEV_PIC1_ISR)
142  pkt->set<uint64_t>(picr);
143  else
144  panic("I/O Read - invalid addr - va %#x size %d\n",
145  pkt->getAddr(), pkt->getSize());
146  } else {
147  panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize());
148  }
149  pkt->makeAtomicResponse();
150  return pioDelay;
151 }
152 
153 Tick
155 {
156  assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
157  Addr daddr = pkt->getAddr() - pioAddr;
158 
159  DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
160  pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get<uint8_t>());
161 
162  assert(pkt->getSize() == sizeof(uint8_t));
163 
164  switch(daddr) {
165  case TSDEV_PIC1_MASK:
166  mask1 = ~(pkt->get<uint8_t>());
167  if ((picr & mask1) && !picInterrupting) {
168  picInterrupting = true;
169  tsunami->cchip->postDRIR(55);
170  DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
171  }
172  if ((!(picr & mask1)) && picInterrupting) {
173  picInterrupting = false;
174  tsunami->cchip->clearDRIR(55);
175  DPRINTF(Tsunami, "clearing pic interrupt\n");
176  }
177  break;
178  case TSDEV_PIC2_MASK:
179  mask2 = pkt->get<uint8_t>();
180  //PIC2 Not implemented to interrupt
181  break;
182  case TSDEV_PIC1_ACK:
183  // clear the interrupt on the PIC
184  picr &= ~(1 << (pkt->get<uint8_t>() & 0xF));
185  if (!(picr & mask1))
186  tsunami->cchip->clearDRIR(55);
187  break;
188  case TSDEV_DMA1_MODE:
189  mode1 = pkt->get<uint8_t>();
190  break;
191  case TSDEV_DMA2_MODE:
192  mode2 = pkt->get<uint8_t>();
193  break;
194  case TSDEV_TMR0_DATA:
195  pitimer.writeCounter(0, pkt->get<uint8_t>());
196  break;
197  case TSDEV_TMR1_DATA:
198  pitimer.writeCounter(1, pkt->get<uint8_t>());
199  break;
200  case TSDEV_TMR2_DATA:
201  pitimer.writeCounter(2, pkt->get<uint8_t>());
202  break;
203  case TSDEV_TMR_CTRL:
204  pitimer.writeControl(pkt->get<uint8_t>());
205  break;
206  case TSDEV_RTC_ADDR:
207  rtcAddr = pkt->get<uint8_t>();
208  break;
209  case TSDEV_RTC_DATA:
210  rtc.writeData(rtcAddr, pkt->get<uint8_t>());
211  break;
212  case TSDEV_KBD:
213  case TSDEV_DMA1_CMND:
214  case TSDEV_DMA2_CMND:
215  case TSDEV_DMA1_MMASK:
216  case TSDEV_DMA2_MMASK:
217  case TSDEV_PIC2_ACK:
218  case TSDEV_DMA1_RESET:
219  case TSDEV_DMA2_RESET:
220  case TSDEV_DMA1_MASK:
221  case TSDEV_DMA2_MASK:
222  case TSDEV_CTRL_PORTB:
223  break;
224  default:
225  panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get<uint8_t>());
226  }
227 
228  pkt->makeAtomicResponse();
229  return pioDelay;
230 }
231 
232 void
233 TsunamiIO::postPIC(uint8_t bitvector)
234 {
235  //PIC2 Is not implemented, because nothing of interest there
236  picr |= bitvector;
237  if (picr & mask1) {
238  tsunami->cchip->postDRIR(55);
239  DPRINTF(Tsunami, "posting pic interrupt to cchip\n");
240  }
241 }
242 
243 void
244 TsunamiIO::clearPIC(uint8_t bitvector)
245 {
246  //PIC2 Is not implemented, because nothing of interest there
247  picr &= ~bitvector;
248  if (!(picr & mask1)) {
249  tsunami->cchip->clearDRIR(55);
250  DPRINTF(Tsunami, "clearing pic interrupt to cchip\n");
251  }
252 }
253 
254 void
256 {
265 
266  // Serialize the timers
267  pitimer.serialize("pitimer", cp);
268  rtc.serialize("rtc", cp);
269 }
270 
271 void
273 {
282 
283  // Unserialize the timers
284  pitimer.unserialize("pitimer", cp);
285  rtc.unserialize("rtc", cp);
286 }
287 
288 void
290 {
291  rtc.startup();
292  pitimer.startup();
293 }
294 
295 TsunamiIO *
296 TsunamiIOParams::create()
297 {
298  return new TsunamiIO(this);
299 }
#define TSDEV_RTC_DATA
Definition: tsunamireg.h:140
#define DPRINTF(x,...)
Definition: trace.hh:212
void set(T v, ByteOrder endian)
Set the value in the data pointer to v using the specified endianness.
Emulation of the Tsunami CChip CSRs.
uint8_t readData(const uint8_t addr)
RTC read data.
Definition: mc146818.cc:232
void writeControl(const CtrlReg data)
Write control word.
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: tsunami_io.cc:255
#define panic(...)
Definition: misc.hh:153
Real-Time Clock (MC146818)
Definition: mc146818.hh:41
void postDRIR(uint32_t interrupt)
post an interrupt to the CPU.
#define TSDEV_DMA2_CMND
Definition: tsunamireg.h:131
void writeData(const uint8_t addr, const uint8_t data)
RTC write data.
Definition: mc146818.cc:139
Top level class for Tsunami Chipset emulation.
Definition: tsunami.hh:56
#define TSDEV_DMA2_MODE
Definition: tsunamireg.h:120
uint8_t mode1
Mode of PIC1.
Definition: tsunami_io.hh:78
void clearPIC(uint8_t bitvector)
Clear a posted interrupt.
Definition: tsunami_io.cc:244
void serialize(const std::string &base, CheckpointOut &cp) const
Serialize this object to the given output stream.
Port Object Declaration.
void startup() override
Start running.
Definition: tsunami_io.cc:289
uint8_t readCounter(unsigned int num)
#define TSDEV_TMR2_DATA
Definition: tsunamireg.h:126
TsunamiCChip * cchip
Pointer to the Tsunami CChip.
Definition: tsunami.hh:72
Tick Frequency
The simulated frequency of curTick(). (In ticks per second)
Definition: core.cc:47
#define TSDEV_DMA1_MASK
Definition: tsunamireg.h:121
#define TSDEV_DMA2_MASK
Definition: tsunamireg.h:122
#define TSDEV_DMA2_MMASK
Definition: tsunamireg.h:134
void serialize(const std::string &base, CheckpointOut &cp) const
Serialize this object to the given output stream.
Definition: mc146818.cc:269
void writeCounter(unsigned int num, const uint8_t data)
void startup()
Start ticking.
T get(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness.
Bitfield< 31 > n
Definition: miscregs.hh:1636
uint16_t timerData
The interval is set via two writes to the PIT.
Definition: tsunami_io.hh:103
bool picInterrupting
Is the pic interrupting right now or not.
Definition: tsunami_io.hh:87
bool outputHigh(unsigned int num)
#define TSDEV_TMR1_DATA
Definition: tsunamireg.h:125
const Params * params() const
Definition: tsunami_io.hh:121
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:145
#define TSDEV_TMR0_DATA
Definition: tsunamireg.h:124
uint8_t rtcAddr
Definition: tsunami_io.hh:97
Addr pioSize
Size that the device's address range.
Definition: io_device.hh:142
void makeAtomicResponse()
Definition: packet.hh:857
uint64_t Tick
Tick count type.
Definition: types.hh:63
#define TSDEV_DMA1_MMASK
Definition: tsunamireg.h:133
Declaration of top level class for the Tsunami chipset.
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: tsunami_io.cc:272
RTC(const std::string &n, const TsunamiIOParams *p)
Definition: tsunami_io.cc:66
#define TSDEV_PIC1_MASK
Definition: tsunamireg.h:111
Tsunami * tsunami
A pointer to the Tsunami device which be belong to.
Definition: tsunami_io.hh:90
#define TSDEV_PIC1_ACK
Definition: tsunamireg.h:115
#define TSDEV_RTC_ADDR
Definition: tsunamireg.h:139
#define TSDEV_PIC2_MASK
Definition: tsunamireg.h:112
#define TSDEV_DMA1_CMND
Definition: tsunamireg.h:129
Tsunami I/O Space mapping including RTC/timer interrupts.
Tick frequency() const
Return the freqency of the RTC.
Definition: tsunami_io.cc:85
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
#define TSDEV_DMA2_RESET
Definition: tsunamireg.h:118
#define TSDEV_PIC2_ISR
Definition: tsunamireg.h:114
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:245
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: tsunami_io.cc:154
TsunamiIO(const Params *p)
Initialize all the data for devices supported by Tsunami I/O.
Definition: tsunami_io.cc:72
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:143
TsunamiIOParams Params
Definition: tsunami_io.hh:113
uint8_t mode2
Mode of PIC2.
Definition: tsunami_io.hh:81
uint8_t mask2
Mask of the PIC2.
Definition: tsunami_io.hh:75
virtual const std::string name() const
Definition: sim_object.hh:117
Declaration of the Packet class.
std::ostream CheckpointOut
Definition: serialize.hh:67
virtual void startup()
Start ticking.
Definition: mc146818.cc:127
#define TSDEV_TMR_CTRL
Definition: tsunamireg.h:127
Intel8254Timer pitimer
Intel 8253 Periodic Interval Timer.
Definition: tsunami_io.hh:93
List of Tsunami CSRs.
void unserialize(const std::string &base, CheckpointIn &cp)
Reconstruct the state of this object from a checkpoint.
Definition: mc146818.cc:289
#define TSDEV_CTRL_PORTB
Definition: tsunamireg.h:123
#define TSDEV_DMA1_MODE
Definition: tsunamireg.h:119
uint8_t picr
Raw PIC interrupt register before masking.
Definition: tsunami_io.hh:84
Tick pioDelay
Delay that the device experinces on an access.
Definition: io_device.hh:145
#define PORTB_SPKR_HIGH
Definition: tsunamireg.h:150
#define TSDEV_DMA1_RESET
Definition: tsunamireg.h:117
void clearDRIR(uint32_t interrupt)
clear an interrupt previously posted to the CPU.
Tsunami I/O device is a catch all for all the south bridge stuff we care to implement.
Definition: tsunami_io.hh:52
TsunamiIO * io
Pointer to the TsunamiIO device which has the RTC.
Definition: tsunami.hh:66
#define TSDEV_PIC1_ISR
Definition: tsunamireg.h:113
uint8_t mask1
Mask of the PIC1.
Definition: tsunami_io.hh:72
unsigned getSize() const
Definition: packet.hh:649
void postPIC(uint8_t bitvector)
Post an PIC interrupt to the CPU via the CChip.
Definition: tsunami_io.cc:233
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: tsunami_io.cc:91
Bitfield< 0 > p
Addr pioAddr
Address that the device listens to.
Definition: io_device.hh:139
#define TSDEV_PIC2_ACK
Definition: tsunamireg.h:116
#define TSDEV_KBD
Definition: tsunamireg.h:137
Addr getAddr() const
Definition: packet.hh:639
void unserialize(const std::string &base, CheckpointIn &cp)
Reconstruct the state of this object from a checkpoint.

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