42 #include "arch/utility.hh" 
   46 #include "debug/Drain.hh" 
   47 #include "debug/MinorCPU.hh" 
   48 #include "debug/Quiesce.hh" 
   52     threadPolicy(params->threadPolicy)
 
   60                     params->itb, params->dtb, params->isa[
i]);
 
   64                     params->workload[
i], params->itb, params->dtb,
 
   70         threadContexts.push_back(tc);
 
   74     if (params->checker) {
 
   75         fatal(
"The Minor model doesn't support checking (yet)\n");
 
   98     if (!params()->switched_out &&
 
   99         system->getMemoryMode() != Enums::timing)
 
  101         fatal(
"The Minor CPU requires the memory system to be in " 
  106     for (
ThreadID thread_id = 0; thread_id < 
threads.size(); thread_id++) {
 
  136     threads[thread_id]->serialize(cp);
 
  142     threads[thread_id]->unserialize(cp);
 
  163     panic(
"No implementation for vtophy\n");
 
  171     DPRINTF(Drain, 
"[tid:%d] MinorCPU wakeup\n", tid);
 
  172     assert(tid < numThreads);
 
  189     for (
ThreadID tid = 0; tid < numThreads; tid++) {
 
  199         DPRINTF(Drain, 
"Minor CPU switched out, draining not needed.\n");
 
  203     DPRINTF(Drain, 
"MinorCPU drain\n");
 
  208         DPRINTF(Drain, 
"MinorCPU drained\n");
 
  211         DPRINTF(Drain, 
"MinorCPU not finished draining\n");
 
  219     DPRINTF(Drain, 
"MinorCPU drain done\n");
 
  232         DPRINTF(Drain, 
"drainResume while switched out.  Ignoring\n");
 
  236     DPRINTF(Drain, 
"MinorCPU drainResume\n");
 
  238     if (!
system->isTimingMode()) {
 
  239         fatal(
"The Minor CPU requires the memory system to be in " 
  243     for (
ThreadID tid = 0; tid < numThreads; tid++)
 
  252     DPRINTF(Drain, 
"MinorCPU memWriteback\n");
 
  260     assert(!switchedOut());
 
  261     BaseCPU::switchOut();
 
  287     threads[thread_id]->activate();
 
  291     BaseCPU::activateContext(thread_id);
 
  301     BaseCPU::suspendContext(thread_id);
 
  307     DPRINTF(Quiesce, 
"Event wakeup from stage %d\n", stage_id);
 
  315 MinorCPUParams::create()
 
  336         ret += (*i)->numInst;
 
A MasterPort is a specialisation of a BaseMasterPort, which implements the default protocol for the t...
void signalDrainDone()
Signal from Pipeline that MinorCPU should signal that a drain is complete and set its drainState...
void regStats(const std::string &name, BaseCPU &baseCpu)
Top level definition of the Minor in-order CPU model. 
Stats::Scalar quiesceCycles
Number of cycles in quiescent state. 
const std::string & name()
DrainState
Object drain/handover states. 
void resetLastStopped()
Reset stopped time to current time. 
void setStatus(Status newStatus)
Counter totalOps() const override
void wakeupOnEvent(unsigned int stage_id)
Interface for stages to signal that they have become active after a callback or eventq event where th...
MasterPort & getInstPort() override
Return a reference to the instruction port. 
void unserialize(CheckpointIn &cp) override
Unserialize an object. 
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation. 
The SimpleThread object provides a combination of the ThreadState object and the ThreadContext interf...
MinorCPU::MinorCPUPort & getInstPort()
Functions below here are BaseCPU operations passed on to pipeline stages. 
Minor::Pipeline * pipeline
pipeline is a container for the clockable pipeline stage objects. 
void reset()
Clears the time buffer and the activity count. 
MinorActivityRecorder * getActivityRecorder()
To give the activity recorder to the CPU. 
MinorCPU::MinorCPUPort & getDataPort()
Return the DcachePort belonging to Execute for the CPU. 
void drainResume() override
ThreadContext is the external interface to all thread state for anything outside of the CPU...
void serialize(CheckpointOut &cp) const override
Checkpoint lastStopped. 
DrainState drain() override
Drain interface. 
Cycles cyclesSinceLastStopped() const 
How long have we been stopped for? 
bool drain()
Try to drain the CPU. 
void unserialize(CheckpointIn &cp) override
Addr dbg_vtophys(Addr addr)
MasterPort & getDataPort() override
Return a reference to the data port. 
void init() override
Starting, waking and initialisation. 
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover. 
void initCPU(ThreadContext *tc, int cpuId)
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
void serialize(CheckpointOut &cp) const override
Serialize pipeline data. 
SimpleThread MinorThread
Minor will use the SimpleThread state for now. 
void activateStage(const int idx)
Marks a stage as active. 
void memWriteback() override
Minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline. 
static void init()
Initialise the class. 
uint64_t Addr
Address type This will probably be moved somewhere else in the near future. 
ThreadContext * getTC()
Returns the pointer to this SimpleThread's ThreadContext. 
void start()
Start ticking. 
Draining buffers pending serialization/handover. 
int64_t Counter
Statistics counter type. 
void takeOverFrom(BaseCPU *old_cpu) override
Fetch1 is responsible for fetching "lines" from memory and passing them to Fetch2. 
void wakeupFetch(ThreadID tid)
Wake up the Fetch unit. 
int16_t ThreadID
Thread index/ID type. 
void regStats()
Register {num,ticks}Cycles if necessary. 
MinorCPU(MinorCPUParams *params)
std::ostream CheckpointOut
void suspendContext(ThreadID thread_id) override
void wakeup(ThreadID tid) override
The dynamic instruction and instruction/line id (sequence numbers) definition for Minor...
std::vector< Minor::MinorThread * > threads
These are thread state-representing objects for this CPU. 
void signalDrainDone() const 
Signal that an object is drained. 
The constructed pipeline. 
void serialize(CheckpointOut &cp) const override
void unserialize(CheckpointIn &cp) override
MinorCPU is an in-order CPU model with four fixed pipeline stages: 
Minor::MinorStats stats
Processor-specific statistics. 
void activateContext(ThreadID thread_id) override
Thread activation interface from BaseCPU. 
virtual void initMemProxies(ThreadContext *tc)=0
Initialise the physical and virtual port proxies and tie them to the data port of the CPU...
The constructed pipeline. 
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
void switchOut() override
Switching interface from BaseCPU. 
const FlagsType init
This Stat is Initialized. 
void regStats() override
Stats interface from SimObject (by way of BaseCPU) 
Counter totalInsts() const override
Simple inst count interface from BaseCPU.