48 #include "debug/ElasticTrace.hh"
53 regEtraceListenersEvent(this),
56 depWindowSize(params->depWindowSize),
57 dataTraceStream(nullptr),
58 instTraceStream(nullptr),
59 startTraceInst(params->startTraceInst),
61 traceVirtAddr(params->traceVirtAddr)
64 fatal_if(!
cpu,
"Manager of %s is not of type O3CPU and thus does not "\
65 "support dependency tracing.\n",
name());
68 "Recommended size is 3x ROB size in the O3CPU.\n");
70 fatal_if(
cpu->numThreads > 1,
"numThreads = %i, %s supports tracing for"\
71 "single-threaded workload only",
cpu->numThreads,
name());
73 fatal_if(params->instFetchTraceFile ==
"",
"Assign instruction fetch "\
74 "trace file path to instFetchTraceFile");
75 fatal_if(params->dataDepTraceFile ==
"",
"Assign data dependency "\
76 "trace file path to dataDepTraceFile");
78 params->instFetchTraceFile);
83 ProtoMessage::PacketHeader inst_pkt_header;
84 inst_pkt_header.set_obj_id(
name());
89 ProtoMessage::InstDepRecordHeader data_rec_header;
90 data_rec_header.set_obj_id(
name());
103 inform(
"@%llu: regProbeListeners() called, startTraceInst = %llu",
121 inform(
"@%llu: No. of instructions committed = %llu, registering elastic"
154 inst_fetch_pkt.set_tick(
curTick());
156 inst_fetch_pkt.set_pc(req->
getPC());
157 inst_fetch_pkt.set_flags(req->
getFlags());
158 inst_fetch_pkt.set_addr(req->
getPaddr());
159 inst_fetch_pkt.set_size(req->
getSize());
175 has already retired (mostly squashed)", dyn_inst->seqNum);
188 auto itr_exec_info =
tempStore.find(dyn_inst->seqNum);
190 exec_info_ptr = itr_exec_info->second;
193 tempStore[dyn_inst->seqNum] = exec_info_ptr;
208 auto itr_exec_info =
tempStore.find(dyn_inst->seqNum);
211 " skipping.\n", dyn_inst->seqNum);
239 int8_t max_regs = dyn_inst->numSrcRegs();
240 for (
int src_idx = 0; src_idx < max_regs; src_idx++) {
242 PhysRegIndex src_reg = dyn_inst->renamedSrcRegIdx(src_idx);
247 InstSeqNum last_writer = itr_last_writer->second;
261 max_regs = dyn_inst->numDestRegs();
262 for (
int dest_idx = 0; dest_idx < max_regs; dest_idx++) {
268 dest_reg = dyn_inst->renamedDestRegIdx(dest_idx);
284 inst_reg_pair.second);
285 auto itr_regdep_map =
physRegDepMap.find(inst_reg_pair.second);
296 auto itr_exec_info =
tempStore.find(head_inst->seqNum);
308 head_inst->hasRequest() &&
309 head_inst->getFault() ==
NoFault) {
325 if (!head_inst->isNop()) {
331 auto itr_temp_store =
tempStore.find(head_inst->seqNum);
334 "store, skipping.\n", head_inst->seqNum);
354 if (head_inst->getFault() !=
NoFault) {
356 "skip adding it to the trace\n",
357 (head_inst->isMemRef() ?
"Load/store" :
"Comp inst."),
359 }
else if (head_inst->isMemRef() && !head_inst->hasRequest()) {
361 "skip adding it to the trace\n", head_inst->seqNum);
362 }
else if (!head_inst->readPredicate()) {
364 "skip adding it to the trace\n",
365 (head_inst->isMemRef() ?
"Load/store" :
"Comp inst."),
387 new_record->
instNum = head_inst->seqNum;
388 new_record->
commit = commit;
389 new_record->
type = head_inst->isLoad() ? Record::LOAD :
390 (head_inst->isStore() ? Record::STORE :
394 new_record->
reqFlags = head_inst->memReqFlags;
395 new_record->
virtAddr = head_inst->effAddr;
396 new_record->
asid = head_inst->asid;
397 new_record->
physAddr = head_inst->physEffAddrLow;
399 new_record->
size = head_inst->effSize;
400 new_record->
pc = head_inst->instAddr();
426 if (head_inst->isLoad() && !commit) {
431 std::set<InstSeqNum>::const_iterator dep_set_it;
441 "%lli\n", new_record->
instNum, *dep_set_it);
442 TraceInfo* reg_dep = trace_info_itr->second;
458 "%lli is skipped\n",new_record->
instNum, *dep_set_it);
466 if (head_inst->isStore()) {
487 (commit ?
"committed" :
"squashed"), new_record->
instNum);
508 bool find_load_not_store)
516 uint32_t num_go_back = 0;
521 while (num_go_back <
depWindowSize && from_itr != until_itr) {
522 if (find_load_not_store) {
542 past_record = *from_itr;
556 uint32_t num_go_back = 0;
557 Tick execute_tick = 0;
559 if (new_record->
isLoad()) {
563 }
else if (new_record->
isStore()) {
576 while (num_go_back <
depWindowSize && from_itr != until_itr) {
588 past_record = *from_itr;
611 Tick execute_tick)
const
618 Tick execute_tick)
const
626 Tick execute_tick)
const
635 Tick execute_tick)
const
648 auto itr_exec_info =
tempStore.find(temp_sn);
652 delete exec_info_ptr;
668 int64_t comp_delay = -1;
669 Tick execution_tick = 0, completion_tick = 0;
678 if (past_record->
isLoad()) {
684 }
else if (past_record->
isStore()) {
686 }
else if (past_record->
isComp()){
689 assert(execution_tick >= completion_tick);
690 comp_delay = execution_tick - completion_tick;
693 execution_tick, completion_tick, comp_delay);
712 int64_t comp_delay = -1;
713 Tick execution_tick = 0, completion_tick = 0;
731 assert(execution_tick >= completion_tick);
732 comp_delay = execution_tick - completion_tick;
734 execution_tick, completion_tick, comp_delay);
778 uint16_t num_filtered_nodes = 0;
781 while (num_to_write > 0) {
783 assert(temp_ptr->
type != Record::INVALID);
790 "is as follows:\n", temp_ptr->
instNum);
794 "size %i, flags %i\n", temp_ptr->
physAddr,
802 }
else if (temp_ptr->
isStore()) {
813 ProtoMessage::InstDepRecord dep_pkt;
814 dep_pkt.set_seq_num(temp_ptr->
instNum);
815 dep_pkt.set_type(temp_ptr->
type);
816 dep_pkt.set_pc(temp_ptr->
pc);
818 dep_pkt.set_flags(temp_ptr->
reqFlags);
819 dep_pkt.set_p_addr(temp_ptr->
physAddr);
823 dep_pkt.set_v_addr(temp_ptr->
virtAddr);
824 dep_pkt.set_asid(temp_ptr->
asid);
826 dep_pkt.set_size(temp_ptr->
size);
828 dep_pkt.set_comp_delay(temp_ptr->
compDelay);
835 dep_pkt.add_rob_dep(temp_ptr->
robDepList.front());
847 if (num_filtered_nodes != 0) {
852 dep_pkt.set_weight(num_filtered_nodes);
853 num_filtered_nodes = 0;
861 ++num_filtered_nodes;
868 depTrace.erase(dep_trace_itr_start, dep_trace_itr);
875 using namespace Stats;
878 .
desc(
"Number of register dependencies recorded during tracing")
882 .
name(
name() +
".numOrderDepStores")
883 .
desc(
"Number of commit order (rob) dependencies for a store recorded"
884 " on a past load/store during tracing")
888 .
name(
name() +
".numIssueOrderDepLoads")
889 .
desc(
"Number of loads that got assigned issue order dependency"
890 " because they were dependency-free")
894 .
name(
name() +
".numIssueOrderDepStores")
895 .
desc(
"Number of stores that got assigned issue order dependency"
896 " because they were dependency-free")
900 .
name(
name() +
".numIssueOrderDepOther")
901 .
desc(
"Number of non load/store insts that got assigned issue order"
902 " dependency because they were dependency-free")
907 .
desc(
"No. of nodes filtered out before writing the output trace")
912 .
desc(
"Maximum number or dependents on any instruction")
917 .
desc(
"Maximum size of the temporary store during the run")
921 .
name(
name() +
".maxPhysRegDepMapSize")
922 .
desc(
"Maximum size of register dependency map")
929 return Record::RecordType_Name(
type);
949 ElasticTraceParams::create()
int64_t compDelay
Computational delay after the last dependent inst.
Stats::Scalar numIssueOrderDepOther
Number of non load/store insts that got assigned an issue order dependency because they were dependen...
Counter value() const
Return the current value of this stat as its base type.
void compDelayPhysRegDep(TraceInfo *past_record, TraceInfo *new_record)
Calculate the computational delay between an instruction and a subsequent instruction that has a Phys...
void flushTraces()
Process any outstanding trace records, flush them out to the protobuf output streams and delete the s...
void regProbeListeners()
Register the probe listeners that is the methods called on a probe point notify() call...
ElasticTrace(const ElasticTraceParams *params)
Constructor.
A ProtoOutputStream wraps a coded stream, potentially with compression, based on looking at the file ...
bool isComp() const
Is the record a fetch triggering an Icache request.
void removeRegDepMapEntry(const SeqNumRegPair &inst_reg_pair)
When an instruction gets squashed the destination register mapped to it is freed up in the rename sta...
FullO3CPU< O3CPUImpl > * cpu
Pointer to the O3CPU that is this listener's parent a.k.a.
void regEtraceListeners()
Register all listeners.
decltype(nullptr) constexpr NoFault
void write(const google::protobuf::Message &msg)
Write a message to the stream, preprending it with the message size.
The elastic trace is a type of probe listener and listens to probe points in multiple stages of the O...
void assignRobDep(TraceInfo *past_record, TraceInfo *new_record)
The new_record has an order dependency on a past_record, thus update the new record's Rob dependency ...
std::unordered_map< InstSeqNum, InstExecInfo * > tempStore
Temporary store of InstExecInfo objects.
bool isStore() const
Is the record a store.
void addDepTraceRecord(const DynInstPtr &head_inst, InstExecInfo *exec_info_ptr, bool commit)
Add a record to the dependency trace depTrace which is a sequential container.
bool allProbesReg
Whther the elastic trace listener has been registered for all probes.
uint32_t depWindowSize
The maximum distance for a dependency and is set by a top level level parameter.
std::vector< TraceInfo * >::iterator depTraceItr
Typedef of iterator to the instruction dependency trace.
Addr getPC() const
Accessor function for pc.
std::vector< TraceInfo * > depTrace
The instruction dependency trace containing TraceInfo objects.
virtual void regStats()
Register statistics for this object.
void addSquashedInst(const DynInstPtr &head_inst)
Add an instruction that is at the head of the ROB and is squashed only if it is a load and a request ...
Tick Frequency
The simulated frequency of curTick(). (In ticks per second)
If you want a reference counting pointer to a mutable object, create it like this: ...
EventWrapper< ElasticTrace,&ElasticTrace::regEtraceListeners > regEtraceListenersEvent
Event to trigger registering this listener for all probe points.
void updateRegDep(const DynInstPtr &dyn_inst)
Record a Read After Write physical register dependency if there has been a write to the source regist...
void updateCommitOrderDep(TraceInfo *new_record, bool find_load_not_store)
Reverse iterate through the graph, search for a store-after-store or store-after-load dependency and ...
Stats::Scalar numIssueOrderDepStores
Number of store insts that got assigned an issue order dependency because they were dependency-free...
void recordExecTick(const DynInstPtr &dyn_inst)
Populate the execute timestamp field in an InstExecInfo object for an instruction in flight...
Stats::Scalar numOrderDepStores
Number of stores that got assigned a commit order dependency on a past load/store.
Tick curTick()
The current simulated tick.
void writeDepTrace(uint32_t num_to_write)
Write out given number of records to the trace starting with the first record in depTrace and iterati...
Stats::Scalar numIssueOrderDepLoads
Number of load insts that got assigned an issue order dependency because they were dependency-free...
Stats::Scalar maxPhysRegDepMapSize
Maximum size of the map that holds the last writer to a physical register.
void recordToCommTick(const DynInstPtr &dyn_inst)
Populate the timestamp field in an InstExecInfo object for an instruction in flight when it is execut...
uint64_t Tick
Tick count type.
ProtoOutputStream * dataTraceStream
Protobuf output stream for data dependency trace.
This class is a minimal wrapper around SimObject.
std::unordered_map< InstSeqNum, TraceInfo * > traceInfoMap
Map where the instruction sequence number is mapped to the pointer to the TraceInfo object...
bool hasLoadCompleted(TraceInfo *past_record, Tick execute_tick) const
Check if past record is a load that completed earlier than the execute tick.
void registerExitCallback(Callback *callback)
Register an exit callback.
std::list< InstSeqNum > physRegDepList
Tick getExecuteTick() const
Get the execute tick of the instruction.
Tick toCommitTick
Timestamp when instruction execution is completed in execute stage and instruction is marked as ready...
void regStats()
Register statistics for the elastic trace.
void updateIssueOrderDep(TraceInfo *new_record)
Reverse iterate through the graph, search for an issue order dependency for a new node and update the...
std::string resolve(const std::string &name) const
Returns relative file names prepended with name of this directory.
Request::FlagsType reqFlags
bool hasStoreCommitted(TraceInfo *past_record, Tick execute_tick) const
Check if past record is a store sent earlier than the execute tick.
const std::string & typeToStr() const
Return string specifying the type of the node.
std::vector< ProbeListener * > listeners
Flags getFlags()
Accessor for flags.
ProtoOutputStream * instTraceStream
Protobuf output stream for instruction fetch trace.
bool hasCompCompleted(TraceInfo *past_record, Tick execute_tick) const
Check if past record is a comp node that completed earlier than the execute tick. ...
Derived & name(const std::string &name)
Set the name and marks this stat to print at the end of simulation.
void clearTempStoreUntil(const DynInstPtr head_inst)
Clear entries in the temporary store of execution info objects to free allocated memory until the pre...
int16_t ThreadID
Thread index/ID type.
bool hasLoadBeenSent(TraceInfo *past_record, Tick execute_tick) const
Check if past record is a load sent earlier than the execute tick.
void fetchReqTrace(const RequestPtr &req)
Take the fields of the request class object that are relevant to create an instruction fetch request...
virtual const std::string name() const
bool isLoad() const
Is the record a load.
Stats::Scalar maxTempStoreSize
Maximum size of the temporary store mostly useful as a check that it is not growing.
Declaration of the Packet class.
std::set< InstSeqNum > physRegDepSet
Set of instruction sequence numbers that this instruction depends on due to Read After Write data dep...
std::list< InstSeqNum > robDepList
Stats::Scalar maxNumDependents
Maximum number of dependents on any instruction.
bool firstWin
Used for checking the first window for processing and writing of dependency trace.
const bool traceVirtAddr
Whether to trace virtual addresses for memory requests.
Tick executeTick
Timestamp when instruction was first processed by execute stage.
void schedule(Event &event, Tick when)
std::reverse_iterator< depTraceItr > depTraceRevItr
Typedef of the reverse iterator to the instruction dependency trace.
std::unordered_map< PhysRegIndex, InstSeqNum > physRegDepMap
Map for recording the producer of a physical register to check Read After Write dependencies.
Derived & desc(const std::string &_desc)
Set the description and marks this stat to print at the end of simulation.
const InstSeqNum startTraceInst
Number of instructions after which to enable tracing.
RegClass regIdxToClass(TheISA::RegIndex reg_idx, TheISA::RegIndex *rel_reg_idx=NULL)
Map a 'unified' architectural register index to its register class.
InstSeqNum lastClearedSeqNum
The last cleared instruction sequence number used to free up the memory allocated in the temporary st...
Helper template class to turn a simple class member function into a callback.
void addCommittedInst(const DynInstPtr &head_inst)
Add an instruction that is at the head of the ROB and is committed.
Stats::Scalar numRegDep
Number of register dependencies recorded during tracing.
fatal_if(p->js_features.size() > 16,"Too many job slot feature registers specified (%i)\n", p->js_features.size())
RecordType type
The type of trace record for the instruction node.
ProbeListenerArg generates a listener for the class of Arg and the class type T which is the class co...
Stats::Scalar numFilteredNodes
Number of filtered nodes.
const std::string name() const
Returns the name of the trace probe listener.
void compDelayRob(TraceInfo *past_record, TraceInfo *new_record)
Calculate the computational delay between an instruction and a subsequent instruction that has an ROB...
ProbePointArg< PacketInfo > Packet
Packet probe point.
static int numSimulatedInsts()