43 #include "debug/Decode.hh"
50 MinorCPUParams ¶ms,
58 nextStageReserve(next_stage_input_buffer),
59 outputWidth(params.executeInputWidth),
60 processMoreThanOneInput(params.decodeCycleInput),
61 decodeInfo(params.numThreads),
67 if (params.decodeInputBufferSize < 1) {
68 fatal(
"%s: decodeInputBufferSize must be >= 1 (%d)\n", name,
69 params.decodeInputBufferSize);
73 for (
ThreadID tid = 0; tid < params.numThreads; tid++) {
76 name +
".inputBuffer" + std::to_string(tid),
"insts",
77 params.decodeInputBufferSize));
127 if (!
inp.outputWire->isBubble())
134 for (
ThreadID tid = 0; tid < cpu.numThreads; tid++)
143 unsigned int output_index = 0;
153 if (inst->isBubble()) {
163 if (inst->isFault()) {
165 inst->fault->name());
187 output_inst->staticInst = static_micro_inst;
193 output_inst->predictedTaken = inst->predictedTaken;
194 output_inst->predictedTarget = inst->predictedTarget;
198 " %d output_index: %d lastMicroop: %s microopPC:"
209 parent_static_inst = static_inst;
221 " %d output_index: %d\n",
222 *output_inst, decode_info.
inputIndex, output_index);
224 parent_static_inst = static_inst;
232 output_inst->id.execSeqNum = decode_info.
execSeqNum;
235 dynInstAddTracing(output_inst, parent_static_inst, cpu);
244 insts_out.
insts[output_index] = output_inst;
292 if (!
inp.outputWire->isBubble())
303 case Enums::SingleThreaded:
304 priority_list.push_back(0);
306 case Enums::RoundRobin:
313 panic(
"Unknown fetch policy");
316 for (
auto tid : priority_list) {
334 return (*
inp.outputWire).isBubble();
340 std::ostringstream
data;
345 (*
out.inputWire).reportData(data);
Data members after this line are cycle-to-cycle state.
decltype(nullptr) constexpr NoFault
Decode(const std::string &name, MinorCPU &cpu_, MinorCPUParams ¶ms, Latch< ForwardInstData >::Output inp_, Latch< ForwardInstData >::Input out_, std::vector< InputBuffer< ForwardInstData >> &next_stage_input_buffer)
std::vector< InputBuffer< ForwardInstData > > & nextStageReserve
Interface to reserve space in the next stage.
void setFetchSeq(InstSeqNum seq)
Latch< ForwardInstData >::Input out
Output port carrying micro-op decomposed instructions to Execute.
const std::string & name()
unsigned int inputIndex
Index into the inputBuffer's head marking the start of unhandled instructions.
void activity()
Records that there is activity this cycle.
virtual StaticInstPtr fetchMicroop(MicroPC upc) const
Return the microop that goes with a particular micropc.
TheISA::PCState microopPC
std::vector< InputBuffer< ForwardInstData > > inputBuffer
bool isDrained()
Is this stage drained? For Decoed, draining is initiated by Execute halting Fetch1 causing Fetch2 to ...
std::vector< DecodeThreadInfo > decodeInfo
Decode collects macro-ops from Fetch2 and splits them into micro-ops passed to Execute.
InstSeqNum execSeqNum
Source of execSeqNums to number instructions.
InstSeqNum execSeqNum
'Execute' sequence number.
Latch< ForwardInstData >::Output inp
Input port carrying macro instructions from Fetch2.
unsigned int width() const
Number of instructions carried by this object.
Tick curTick()
The current simulated tick.
bool isBubble() const
BubbleIF interface.
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to decode from.
void activateStage(const int idx)
Marks a stage as active.
std::vector< ThreadID > randomPriority()
void resize(unsigned int width)
Resize a bubble/empty ForwardInstData and fill with bubbles.
MinorDynInstPtr insts[MAX_FORWARD_INSTS]
Array of carried insts, ref counted.
Minor::MinorActivityRecorder * activityRecorder
Activity recording for pipeline.
bool processMoreThanOneInput
If true, more than one input word can be processed each cycle if there is room in the output to conta...
std::vector< ThreadID > roundRobinPriority(ThreadID priority)
Thread scheduling utility functions.
const ThreadID InvalidThreadID
int16_t ThreadID
Thread index/ID type.
Dynamic instruction for Minor.
void evaluate()
Pass on input/buffer data to the output if you can.
TheISA::PCState pc
The fetch address of this instruction.
Enums::ThreadPolicy threadPolicy
Thread Scheduling Policy (RoundRobin, Random, etc)
virtual void advancePC(TheISA::PCState &pcState) const =0
#define MINORTRACE(...)
DPRINTFN for MinorTrace reporting.
The constructed pipeline.
const ForwardInstData * getInput(ThreadID tid)
Get a piece of data to work on, or 0 if there is no data.
MinorCPU is an in-order CPU model with four fixed pipeline stages:
bool inMacroop
True when we're in the process of decomposing a micro-op and microopPC will be valid.
bool isLastMicroop() const
ThreadID threadId
The thread to which this line/instruction belongs.
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
Trace::InstRecord * traceData
Trace information for this instruction's execution.
unsigned int outputWidth
Width of output of this stage/input of next in instructions.
ThreadID threadId
Thread associated with these instructions.