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decode.hh
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37  * Authors: Andrew Bardsley
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39 
47 #ifndef __CPU_MINOR_DECODE_HH__
48 #define __CPU_MINOR_DECODE_HH__
49 
50 #include "cpu/minor/buffers.hh"
51 #include "cpu/minor/cpu.hh"
52 #include "cpu/minor/dyn_inst.hh"
53 #include "cpu/minor/pipe_data.hh"
54 
55 namespace Minor
56 {
57 
58 /* Decode takes instructions from Fetch2 and decomposes them into micro-ops
59  * to feed to Execute. It generates a new sequence number for each
60  * instruction: execSeqNum.
61  */
62 class Decode : public Named
63 {
64  protected:
67 
72 
75 
77  unsigned int outputWidth;
78 
82 
83  public:
84  /* Public for Pipeline to be able to pass it to Fetch2 */
86 
87  protected:
91 
94  inputIndex(0),
95  inMacroop(false),
96  execSeqNum(InstId::firstExecSeqNum),
97  blocked(false)
98  { }
99 
101  inputIndex(other.inputIndex),
102  inMacroop(other.inMacroop),
103  execSeqNum(other.execSeqNum),
104  blocked(other.blocked)
105  { }
106 
107 
110  unsigned int inputIndex;
111 
117  bool inMacroop;
119 
122 
124  bool blocked;
125  };
126 
129 
130  protected:
132  const ForwardInstData *getInput(ThreadID tid);
133 
135  void popInput(ThreadID tid);
136 
140  public:
141  Decode(const std::string &name,
142  MinorCPU &cpu_,
143  MinorCPUParams &params,
146  std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);
147 
148  public:
150  void evaluate();
151 
152  void minorTrace() const;
153 
158  bool isDrained();
159 };
160 
161 }
162 
163 #endif /* __CPU_MINOR_DECODE_HH__ */
Data members after this line are cycle-to-cycle state.
Definition: decode.hh:90
bool blocked
Blocked indication for report.
Definition: decode.hh:124
const std::string & name() const
Definition: trace.hh:149
Decode(const std::string &name, MinorCPU &cpu_, MinorCPUParams &params, Latch< ForwardInstData >::Output inp_, Latch< ForwardInstData >::Input out_, std::vector< InputBuffer< ForwardInstData >> &next_stage_input_buffer)
Definition: decode.cc:48
Top level definition of the Minor in-order CPU model.
std::vector< InputBuffer< ForwardInstData > > & nextStageReserve
Interface to reserve space in the next stage.
Definition: decode.hh:74
Latch< ForwardInstData >::Input out
Output port carrying micro-op decomposed instructions to Execute.
Definition: decode.hh:71
Contains class definitions for data flowing between pipeline stages in the top-level structure portio...
Like a Queue but with a restricted interface and a setTail function which, when the queue is empty...
Definition: buffers.hh:563
unsigned int inputIndex
Index into the inputBuffer's head marking the start of unhandled instructions.
Definition: decode.hh:110
Id for lines and instructions.
Definition: dyn_inst.hh:70
TheISA::PCState microopPC
Definition: decode.hh:118
std::vector< InputBuffer< ForwardInstData > > inputBuffer
Definition: decode.hh:85
MinorCPU & cpu
Pointer back to the containing CPU.
Definition: decode.hh:66
bool isDrained()
Is this stage drained? For Decoed, draining is initiated by Execute halting Fetch1 causing Fetch2 to ...
Definition: decode.cc:327
std::vector< DecodeThreadInfo > decodeInfo
Definition: decode.hh:127
InstSeqNum execSeqNum
Source of execSeqNums to number instructions.
Definition: decode.hh:121
STL vector class.
Definition: stl.hh:40
DecodeThreadInfo()
Default Constructor.
Definition: decode.hh:93
Definition: trace.hh:140
Latch< ForwardInstData >::Output inp
Input port carrying macro instructions from Fetch2.
Definition: decode.hh:69
ThreadID getScheduledThread()
Use the current threading policy to determine the next thread to decode from.
Definition: decode.cc:297
uint64_t InstSeqNum
Definition: inst_seq.hh:40
void minorTrace() const
Definition: decode.cc:338
Classes for buffer, queue and FIFO behaviour.
bool processMoreThanOneInput
If true, more than one input word can be processed each cycle if there is room in the output to conta...
Definition: decode.hh:81
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:171
void evaluate()
Pass on input/buffer data to the output if you can.
Definition: decode.cc:124
ThreadID threadPriority
Definition: decode.hh:128
DecodeThreadInfo(const DecodeThreadInfo &other)
Definition: decode.hh:100
GenericISA::SimplePCState< MachInst > PCState
Definition: types.hh:43
The dynamic instruction and instruction/line id (sequence numbers) definition for Minor...
const ForwardInstData * getInput(ThreadID tid)
Get a piece of data to work on, or 0 if there is no data.
Definition: decode.cc:82
MinorCPU is an in-order CPU model with four fixed pipeline stages:
Definition: cpu.hh:79
Encapsulate wires on either input or output of the latch.
Definition: buffers.hh:243
bool inMacroop
True when we're in the process of decomposing a micro-op and microopPC will be valid.
Definition: decode.hh:117
Forward flowing data between Fetch2,Decode,Execute carrying a packet of instructions of a width appro...
Definition: pipe_data.hh:255
void popInput(ThreadID tid)
Pop an element off the input buffer, if there are any.
Definition: decode.cc:95
unsigned int outputWidth
Width of output of this stage/input of next in instructions.
Definition: decode.hh:77

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