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lru.cc
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40  * Authors: Erik Hallnor
41  */
42 
48 #include "mem/cache/tags/lru.hh"
49 
50 #include "debug/CacheRepl.hh"
51 #include "mem/cache/base.hh"
52 
53 LRU::LRU(const Params *p)
54  : BaseSetAssoc(p)
55 {
56 }
57 
58 CacheBlk*
59 LRU::accessBlock(Addr addr, bool is_secure, Cycles &lat)
60 {
61  CacheBlk *blk = BaseSetAssoc::accessBlock(addr, is_secure, lat);
62 
63  if (blk != nullptr) {
64  // move this block to head of the MRU list
65  sets[blk->set].moveToHead(blk);
66  DPRINTF(CacheRepl, "set %x: moving blk %x (%s) to MRU\n",
67  blk->set, regenerateBlkAddr(blk->tag, blk->set),
68  is_secure ? "s" : "ns");
69  }
70 
71  return blk;
72 }
73 
74 CacheBlk*
76 {
77  int set = extractSet(addr);
78  // grab a replacement candidate
79  BlkType *blk = nullptr;
80  for (int i = assoc - 1; i >= 0; i--) {
81  BlkType *b = sets[set].blks[i];
82  if (b->way < allocAssoc) {
83  blk = b;
84  break;
85  }
86  }
87  assert(!blk || blk->way < allocAssoc);
88 
89  if (blk && blk->isValid()) {
90  DPRINTF(CacheRepl, "set %x: selecting blk %x for replacement\n",
91  set, regenerateBlkAddr(blk->tag, set));
92  }
93 
94  return blk;
95 }
96 
97 void
99 {
100  BaseSetAssoc::insertBlock(pkt, blk);
101 
102  int set = extractSet(pkt->getAddr());
103  sets[set].moveToHead(blk);
104 }
105 
106 void
108 {
110 
111  // should be evicted before valid blocks
112  int set = blk->set;
113  sets[set].moveToTail(blk);
114 }
115 
116 LRU*
117 LRUParams::create()
118 {
119  return new LRU(this);
120 }
#define DPRINTF(x,...)
Definition: trace.hh:212
unsigned allocAssoc
The allocatable associativity of the cache (alloc mask).
Declares a basic cache interface BaseCache.
void insertBlock(PacketPtr pkt, CacheBlk *blk) override
Insert the new block into the cache.
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:83
Bitfield< 7 > i
Definition: miscregs.hh:1378
void invalidate(CacheBlk *blk)
Invalidate the given block.
Definition: lru.cc:107
Addr tag
Data block tag value.
Definition: blk.hh:86
Declaration of a LRU tag store.
ip6_addr_t addr
Definition: inet.hh:335
CacheBlk * findVictim(Addr addr)
Find an invalid block to evict for the address provided.
Definition: lru.cc:75
CacheBlk * accessBlock(Addr addr, bool is_secure, Cycles &lat) override
Access block and update replacement data.
Blktype ** blks
Cache blocks in this set, maintained in LRU order 0 = MRU.
Definition: cacheset.hh:64
void moveToHead(Blktype *blk)
Move the given block to the head of the list.
Definition: cacheset.hh:119
int way
Definition: blk.hh:109
Bitfield< 7 > b
Definition: miscregs.hh:1564
BaseTagsParams Params
Definition: base.hh:151
A Basic Cache block.
Definition: blk.hh:79
Definition: lru.hh:56
A BaseSetAssoc cache tag store.
void insertBlock(PacketPtr pkt, BlkType *blk)
Insert the new block into the cache.
Definition: lru.cc:98
SetType * sets
The cache sets.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
void invalidate(CacheBlk *blk) override
Invalidate the given block.
A Packet is used to encapsulate a transfer between two objects in the memory system (e...
Definition: packet.hh:245
CacheBlk * accessBlock(Addr addr, bool is_secure, Cycles &lat)
Access block and update replacement data.
Definition: lru.cc:59
int extractSet(Addr addr) const override
Calculate the set index from the address.
const unsigned assoc
The associativity of the cache.
void moveToTail(Blktype *blk)
Move the given block to the tail of the list.
Definition: cacheset.hh:141
int set
The set and way this block belongs to.
Definition: blk.hh:109
bool isValid() const
Checks that a block is valid.
Definition: blk.hh:203
Bitfield< 0 > p
Addr getAddr() const
Definition: packet.hh:639
Addr regenerateBlkAddr(Addr tag, unsigned set) const override
Regenerate the block address from the tag.
LRU(const Params *p)
Construct and initialize this tag store.
Definition: lru.cc:53

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