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mem_dep_unit.hh
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42 
43 #ifndef __CPU_O3_MEM_DEP_UNIT_HH__
44 #define __CPU_O3_MEM_DEP_UNIT_HH__
45 
46 #include <list>
47 #include <memory>
48 #include <set>
49 #include <unordered_map>
50 
51 #include "base/statistics.hh"
52 #include "cpu/inst_seq.hh"
53 #include "debug/MemDepUnit.hh"
54 
55 struct SNHash {
56  size_t operator() (const InstSeqNum &seq_num) const {
57  unsigned a = (unsigned)seq_num;
58  unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
59 
60  return hash;
61  }
62 };
63 
64 struct DerivO3CPUParams;
65 
66 template <class Impl>
67 class InstructionQueue;
68 
80 template <class MemDepPred, class Impl>
82 {
83  protected:
84  std::string _name;
85 
86  public:
87  typedef typename Impl::DynInstPtr DynInstPtr;
88 
90  MemDepUnit();
91 
93  MemDepUnit(DerivO3CPUParams *params);
94 
96  ~MemDepUnit();
97 
99  std::string name() const { return _name; }
100 
102  void init(DerivO3CPUParams *params, ThreadID tid);
103 
105  void regStats();
106 
108  bool isDrained() const;
109 
111  void drainSanityCheck() const;
112 
114  void takeOverFrom();
115 
117  void setIQ(InstructionQueue<Impl> *iq_ptr);
118 
120  void insert(DynInstPtr &inst);
121 
123  void insertNonSpec(DynInstPtr &inst);
124 
126  void insertBarrier(DynInstPtr &barr_inst);
127 
129  void regsReady(DynInstPtr &inst);
130 
132  void nonSpecInstReady(DynInstPtr &inst);
133 
135  void reschedule(DynInstPtr &inst);
136 
140  void replay();
141 
143  void completed(DynInstPtr &inst);
144 
146  void completeBarrier(DynInstPtr &inst);
147 
149  void wakeDependents(DynInstPtr &inst);
150 
154  void squash(const InstSeqNum &squashed_num, ThreadID tid);
155 
157  void violation(DynInstPtr &store_inst, DynInstPtr &violating_load);
158 
160  void issue(DynInstPtr &inst);
161 
163  void dumpLists();
164 
165  private:
167 
168  class MemDepEntry;
169 
170  typedef std::shared_ptr<MemDepEntry> MemDepEntryPtr;
171 
176  class MemDepEntry {
177  public:
180  : inst(new_inst), regsReady(false), memDepReady(false),
181  completed(false), squashed(false)
182  {
183 #ifdef DEBUG
184  ++memdep_count;
185 
186  DPRINTF(MemDepUnit, "Memory dependency entry created. "
187  "memdep_count=%i %s\n", memdep_count, inst->pcState());
188 #endif
189  }
190 
193  {
194  for (int i = 0; i < dependInsts.size(); ++i) {
195  dependInsts[i] = NULL;
196  }
197 #ifdef DEBUG
198  --memdep_count;
199 
200  DPRINTF(MemDepUnit, "Memory dependency entry deleted. "
201  "memdep_count=%i %s\n", memdep_count, inst->pcState());
202 #endif
203  }
204 
206  std::string name() const { return "memdepentry"; }
207 
210 
213 
216 
218  bool regsReady;
222  bool completed;
224  bool squashed;
225 
227 #ifdef DEBUG
228  static int memdep_count;
229  static int memdep_insert;
230  static int memdep_erase;
231 #endif
232  };
233 
235  inline MemDepEntryPtr &findInHash(const DynInstPtr &inst);
236 
238  inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
239 
240  typedef std::unordered_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
241 
242  typedef typename MemDepHash::iterator MemDepHashIt;
243 
246 
248  std::list<DynInstPtr> instList[Impl::MaxThreads];
249 
252 
258  MemDepPred depPred;
259 
268 
271 
273  int id;
274 
283 };
284 
285 #endif // __CPU_O3_MEM_DEP_UNIT_HH__
#define DPRINTF(x,...)
Definition: trace.hh:212
MemDepHash memDepHash
A hash map of all memory dependence entries.
bool loadBarrier
Is there an outstanding load barrier that loads must wait on.
std::shared_ptr< MemDepEntry > MemDepEntryPtr
Bitfield< 7 > i
Definition: miscregs.hh:1378
InstSeqNum storeBarrierSN
The sequence number of the store barrier.
void violation(DynInstPtr &store_inst, DynInstPtr &violating_load)
Indicates an ordering violation between a store and a younger load.
std::list< DynInstPtr >::iterator ListIt
ListIt listIt
The iterator to the instruction's location inside the list.
void regStats()
Registers statistics.
Bitfield< 8 > a
Definition: miscregs.hh:1377
void replay()
Replays all instructions that have been rescheduled by moving them to the ready list.
bool storeBarrier
Is there an outstanding store barrier that loads must wait on.
bool memDepReady
If all memory dependencies have been satisfied.
~MemDepEntry()
Frees any pointers.
int id
The thread id of this memory dependence unit.
void setIQ(InstructionQueue< Impl > *iq_ptr)
Sets the pointer to the IQ.
std::vector< MemDepEntryPtr > dependInsts
A vector of any dependent instructions.
Declaration of Statistics objects.
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:2475
void wakeDependents(DynInstPtr &inst)
Wakes any dependents of a memory instruction.
~MemDepUnit()
Frees up any memory allocated.
void completed(DynInstPtr &inst)
Completes a memory instruction.
Stats::Scalar insertedLoads
Stat for number of inserted loads.
bool squashed
If the instruction is squashed.
InstructionQueue< Impl > * iqPtr
Pointer to the IQ.
void takeOverFrom()
Takes over from another CPU's thread.
Impl::DynInstPtr DynInstPtr
Definition: mem_dep_unit.hh:87
void nonSpecInstReady(DynInstPtr &inst)
Indicate that a non-speculative instruction is ready.
bool regsReady
If the registers are ready or not.
Stats::Scalar conflictingStores
Stat for number of conflicting stores that had to wait for a store.
size_t operator()(const InstSeqNum &seq_num) const
Definition: mem_dep_unit.hh:56
void insert(DynInstPtr &inst)
Inserts a memory instruction.
Stats::Scalar conflictingLoads
Stat for number of conflicting loads that had to wait for a store.
void moveToReady(MemDepEntryPtr &ready_inst_entry)
Moves an entry to the ready list.
bool completed
If the instruction is completed.
uint64_t InstSeqNum
Definition: inst_seq.hh:40
Memory dependence entries that track memory operations, marking when the instruction is ready to exec...
void dumpLists()
Debugging function to dump the lists of instructions.
MemDepEntryPtr & findInHash(const DynInstPtr &inst)
Finds the memory dependence entry in the hash map.
void regsReady(DynInstPtr &inst)
Indicate that an instruction has its registers ready.
STL list class.
Definition: stl.hh:54
void insertNonSpec(DynInstPtr &inst)
Inserts a non-speculative memory instruction.
Stats::Scalar insertedStores
Stat for number of inserted stores.
std::list< DynInstPtr > instList[Impl::MaxThreads]
A list of all instructions in the memory dependence unit.
MemDepPred depPred
The memory dependence predictor.
Memory dependency unit class.
Definition: mem_dep_unit.hh:81
MemDepEntry(DynInstPtr &new_inst)
Constructs a memory dependence entry.
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:171
void init(DerivO3CPUParams *params, ThreadID tid)
Initializes the unit with parameters and a thread id.
void insertBarrier(DynInstPtr &barr_inst)
Inserts a barrier instruction.
void issue(DynInstPtr &inst)
Issues the given instruction.
std::string name() const
Returns the name of the memory dependence unit.
Definition: mem_dep_unit.hh:99
InstSeqNum loadBarrierSN
The sequence number of the load barrier.
std::string name() const
Returns the name of the memory dependence entry.
void squash(const InstSeqNum &squashed_num, ThreadID tid)
Squashes all instructions up until a given sequence number for a specific thread. ...
std::list< DynInstPtr > instsToReplay
A list of all instructions that are going to be replayed.
void drainSanityCheck() const
Perform sanity checks after a drain.
std::unordered_map< InstSeqNum, MemDepEntryPtr, SNHash > MemDepHash
void reschedule(DynInstPtr &inst)
Reschedules an instruction to be re-executed.
bool isDrained() const
Determine if we are drained.
void completeBarrier(DynInstPtr &inst)
Completes a barrier instruction.
MemDepUnit()
Empty constructor.
A standard instruction queue class.
Definition: inst_queue.hh:82
std::string _name
Definition: mem_dep_unit.hh:84
DynInstPtr inst
The instruction being tracked.
MemDepHash::iterator MemDepHashIt

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