44 #ifndef __CPU_O3_INST_QUEUE_HH__
45 #define __CPU_O3_INST_QUEUE_HH__
60 struct DerivO3CPUParams;
86 typedef typename Impl::O3CPU
O3CPU;
89 typedef typename Impl::CPUPol::IEW
IEW;
131 std::string
name()
const;
343 return lhs->seqNum > rhs->seqNum;
347 typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare>
364 typedef typename std::map<InstSeqNum, DynInstPtr>::iterator
NonSpecMapIt;
552 #endif //__CPU_O3_INST_QUEUE_HH__
Stats::Scalar iqMiscInstsIssued
Stat for number of miscellaneous instructions issued.
int wbOutstanding
Number of instructions currently in flight to FUs.
void regStats()
Registers statistics.
std::list< ThreadID > * activeThreads
Pointer to list of active threads.
Stats::Scalar iqFloatInstsIssued
Stat for number of floating point instructions issued.
unsigned getCount(ThreadID tid)
Returns the number of used entries for a thread.
Struct for comparing entries to be added to the priority queue.
Cycles is a wrapper class for representing cycle counts, i.e.
Stats::Scalar fpAluAccesses
void doSquash(ThreadID tid)
Does the actual squashing.
void scheduleReadyInsts()
Schedules ready instructions, adding the ready ones (oldest first) to the queue to execute...
Stats::Scalar intAluAccesses
void violation(DynInstPtr &store, DynInstPtr &faulting_load)
Indicates an ordering violation between a store and a load.
Stats::Scalar iqInstsAdded
Stat for number of instructions added.
InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
Constructs an IQ.
bool queueOnList[Num_OpClasses]
Tracks if each ready queue is on the age order list.
std::list< DynInstPtr > instsToExecute
List of instructions that are ready to be executed.
void dumpInsts()
Debugging function to dump out all instructions that are in the IQ.
int wakeDependents(DynInstPtr &completed_inst)
Wakes all dependents of a completed instruction.
void insertNonSpec(DynInstPtr &new_inst)
Inserts a new, non-speculative instruction into the IQ.
InstSeqNum squashedSeqNum[Impl::MaxThreads]
The sequence number of the squashed instruction.
Impl::DynInstPtr DynInstPtr
void scheduleNonSpec(const InstSeqNum &inst)
Schedules a single specific non-speculative instruction.
DynInstPtr getInstToExecute()
Returns the oldest scheduled instruction, and removes it from the list of instructions waiting to exe...
Stats::Scalar iqInstsIssued
MemInterface * dcacheInterface
Cache interface.
FU completion event class.
Stats::Scalar iqMemInstsIssued
Stat for number of memory instructions issued.
bool operator()(const DynInstPtr &lhs, const DynInstPtr &rhs) const
A vector of scalar stats.
void insertBarrier(DynInstPtr &barr_inst)
Inserts a memory or write barrier into the IQ to make sure loads and stores are ordered properly...
void addToOrderList(OpClass op_class)
Add an op class to the age order list.
void setActiveThreads(std::list< ThreadID > *at_ptr)
Sets active threads list.
unsigned numEntries
The number of entries in the instruction queue.
std::list< DynInstPtr > instList[Impl::MaxThreads]
List of all the instructions in the IQ (some of which may be issued).
Declaration of Statistics objects.
virtual const char * description() const
Return a C string describing the event.
DynInstPtr inst
Executing instruction.
This is a simple scalar statistic, like a counter.
void setTimeBuffer(TimeBuffer< TimeStruct > *tb_ptr)
Sets the global time buffer.
std::vector< bool > regScoreboard
A cache of the recently woken registers.
Stats::Scalar fpInstQueueWrites
Impl::CPUPol::IssueStruct IssueStruct
std::list< DynInstPtr > blockedMemInsts
List of instructions that have been cache blocked.
void processFUCompletion(DynInstPtr &inst, int fu_idx)
Process FU completion event.
bool isFull()
Returns whether or not the IQ is full.
unsigned numFreeEntries()
Returns total number of free entries.
IQPolicy
IQ Resource Sharing Policy.
int fuIdx
Index of the FU used for executing.
bool hasReadyInsts()
Returns if there are any ready instructions in the IQ.
Stats::Scalar intInstQueueWakeupAccesses
void blockMemInst(DynInstPtr &blocked_inst)
Defers a memory instruction when it is cache blocked.
Stats::Scalar iqSquashedNonSpecRemoved
Stat for number of non-speculative instructions removed due to a squash.
void addIfReady(DynInstPtr &inst)
Moves an instruction to the ready queue if it is ready.
Pool of FU's, specific to the new CPU model.
Array of linked list that maintains the dependencies between producing instructions and consuming ins...
A simple distribution stat.
void completeMemInst(DynInstPtr &completed_inst)
Completes a memory operation.
TimeBuffer< IssueStruct > * issueToExecuteQueue
The queue to the execute stage.
IEW * iewStage
Pointer to IEW stage.
Stats::Scalar intInstQueueWrites
void addToProducers(DynInstPtr &new_inst)
Adds an instruction to the dependency graph, as a producer.
ReadyInstQueue readyInsts[Num_OpClasses]
List of ready instructions, per op class.
void commit(const InstSeqNum &inst, ThreadID tid=0)
Commits all instructions up to and including the given sequence number, for a specific thread...
std::map< InstSeqNum, DynInstPtr > nonSpecInsts
List of non-speculative instructions that will be scheduled once the IQ gets a signal from commit...
std::list< ListOrderEntry > listOrder
List that contains the age order of the oldest instruction of each ready queue.
Stats::Scalar iqBranchInstsIssued
Stat for number of branch instructions issued.
void addReadyMemInst(DynInstPtr &ready_inst)
Adds a ready memory instruction to the ready list.
unsigned count[Impl::MaxThreads]
Per Thread IQ count.
void takeOverFrom()
Takes over execution from another CPU's thread.
TimeBuffer< TimeStruct > * timeBuffer
The backwards time buffer.
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
Cycles commitToIEWDelay
Delay between commit stage and the IQ.
Stats::Scalar iqSquashedInstsIssued
Stat for number of squashed instructions that were ready to issue.
Stats::Formula fuBusyRate
Number of times the FU was busy per instruction issued.
std::string name() const
Returns the name of the IQ.
std::list< ListOrderEntry >::iterator ListOrderIt
std::list< DynInstPtr > retryMemInsts
List of instructions that were cache blocked, but a retry has been seen since, so they can now be ret...
TimeBuffer< TimeStruct >::wire fromCommit
Wire to read information from timebuffer.
DynInstPtr getBlockedMemInstToExecute()
Gets a memory instruction that was blocked on the cache.
void resetState()
Resets all instruction queue state.
Memory dependency unit class.
~InstructionQueue()
Destructs the IQ.
DynInstPtr getDeferredMemInstToExecute()
Gets a memory instruction that was referred due to a delayed DTB translation if it is now ready to ex...
int16_t ThreadID
Thread index/ID type.
void deferMemInst(DynInstPtr &deferred_inst)
Defers a memory instruction when its DTB translation incurs a hw page table walk. ...
void squash(ThreadID tid)
Squashes instructions for a thread.
Stats::Vector2d statIssuedInstType
Stat for total number issued for each instruction type.
DependencyGraph< DynInstPtr > dependGraph
int countInsts()
Debugging function to count how many entries are in the IQ.
bool freeFU
Should the FU be added to the list to be freed upon completing this event.
Stats::Scalar iqSquashedOperandsExamined
Stat for number of squashed instruction operands examined when squashing.
void resetEntries()
Resets max entries for all threads.
Stats::Scalar fpInstQueueReads
static const OpClass Num_OpClasses
std::priority_queue< DynInstPtr, std::vector< DynInstPtr >, pqCompare > ReadyInstQueue
std::map< InstSeqNum, DynInstPtr >::iterator NonSpecMapIt
int entryAmount(ThreadID num_threads)
Number of entries needed for given amount of threads.
void rescheduleMemInst(DynInstPtr &resched_inst)
Reschedules a memory instruction.
Stats::Scalar iqSquashedInstsExamined
Stat for number of squashed instructions examined when squashing.
O3CPU * cpu
Pointer to the CPU.
ListOrderIt readyIt[Num_OpClasses]
Iterators of each ready queue.
Stats::Scalar iqIntInstsIssued
Stat for number of integer instructions issued.
Stats::Vector fuBusy
Number of times the FU was busy.
void drainSanityCheck() const
Perform sanity checks after a drain.
Entry for the list age ordering by op class.
std::list< DynInstPtr >::iterator ListIt
unsigned maxEntries[Impl::MaxThreads]
Max IQ Entries Per Thread.
void setIssueToExecuteQueue(TimeBuffer< IssueStruct > *i2eQueue)
Sets the timer buffer between issue and execute.
void cacheUnblocked()
Notify instruction queue that a previous blockage has resolved.
void moveToYoungerInst(ListOrderIt age_order_it)
Called when the oldest instruction has been removed from a ready queue; this places that ready queue ...
Stats::Scalar iqNonSpecInstsAdded
Stat for number of non-speculative instructions added.
void printInsts()
Debug function to print all instructions.
Stats::Formula issueRate
Number of instructions issued per cycle.
unsigned numPhysRegs
The number of physical registers in the CPU.
A 2-Dimensional vecto of scalar stats.
Stats::Scalar fpInstQueueWakeupQccesses
Stats::Scalar intInstQueueReads
MemDepUnit memDepUnit[Impl::MaxThreads]
The memory dependence unit, which tracks/predicts memory dependences between instructions.
bool addToDependents(DynInstPtr &new_inst)
Adds an instruction to the dependency graph, as a consumer.
void insert(DynInstPtr &new_inst)
Inserts a new instruction into the IQ.
FUPool * fuPool
Function unit pool.
FUCompletion(DynInstPtr &_inst, int fu_idx, InstructionQueue< Impl > *iq_ptr)
Construct a FU completion event.
bool isDrained() const
Determine if we are drained.
void recordProducer(DynInstPtr &inst)
Records the instruction as the producer of a register without adding it to the rest of the IQ...
IQPolicy iqPolicy
IQ sharing policy for SMT.
std::list< DynInstPtr > deferredMemInsts
List of instructions waiting for their DTB translation to complete (hw page table walk in progress)...
InstructionQueue< Impl > * iqPtr
Pointer back to the instruction queue.
A standard instruction queue class.
unsigned totalWidth
The total number of instructions that can be issued in one cycle.
void dumpLists()
Debugging function to dump all the list sizes, as well as print out the list of nonspeculative instru...
Stats::Distribution numIssuedDist
Distribution of number of instructions in the queue.
unsigned freeEntries
Number of free IQ entries left.
Stats::Vector statFuBusy
Distribution of the cycles it takes to issue an instruction.
void replayMemInst(DynInstPtr &replay_inst)
Replays a memory instruction.
Impl::CPUPol::MemDepUnit MemDepUnit
Impl::CPUPol::TimeStruct TimeStruct
ThreadID numThreads
Number of Total Threads.