DRAM specific generator is for issuing request with variable page hit length and bank utilization. More...

#include <generators.hh>

Inheritance diagram for DramGen:

Public Member Functions
	DramGen (const std::string &_name, MasterID master_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, unsigned int addr_mapping, unsigned int nbr_of_ranks)
	Create a DRAM address sequence generator. More...

PacketPtr	getNextPacket ()
	Get the next generated packet. More...

void	genStartAddr (unsigned int new_bank, unsigned int new_rank)
	Insert bank, rank, and column bits into packed address to create address for 1st command in a series. More...

Public Member Functions inherited from RandomGen
	RandomGen (const std::string &_name, MasterID master_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit)
	Create a random address sequence generator. More...

void	enter ()
	Enter this generator state. More...

Tick	nextPacketTick (bool elastic, Tick delay) const
	Determine the tick when the next packet is available. More...

Public Member Functions inherited from BaseGen
	BaseGen (const std::string &_name, MasterID master_id, Tick _duration)
	Create a base generator. More...

virtual	~BaseGen ()

std::string	name () const
	Get the name, useful for DPRINTFs. More...

virtual void	exit ()
	Exit this generator state. More...

Protected Attributes
const unsigned int	numSeqPkts
	Number of sequential DRAM packets to be generated per cpu request. More...

unsigned int	countNumSeqPkts
	Track number of sequential packets generated for a request. More...

Addr	addr
	Address of request. More...

bool	isRead
	Remember type of requests to be generated in series. More...

const unsigned int	pageSize
	Page size of DRAM. More...

const unsigned int	pageBits
	Number of page bits in DRAM address. More...

const unsigned int	bankBits
	Number of bank bits in DRAM address. More...

const unsigned int	blockBits
	Number of block bits in DRAM address. More...

const unsigned int	nbrOfBanksDRAM
	Number of banks in DRAM. More...

const unsigned int	nbrOfBanksUtil
	Number of banks to be utilized for a given configuration. More...

unsigned int	addrMapping
	Address mapping to be used. More...

const unsigned int	rankBits
	Number of rank bits in DRAM address. More...

const unsigned int	nbrOfRanks
	Number of ranks to be utilized for a given configuration. More...

Protected Attributes inherited from RandomGen
const Addr	startAddr
	Start of address range. More...

const Addr	endAddr
	End of address range. More...

const Addr	blocksize
	Block size. More...

const Tick	minPeriod
	Request generation period. More...

const Tick	maxPeriod

const uint8_t	readPercent
	Percent of generated transactions that should be reads. More...

const Addr	dataLimit
	Maximum amount of data to manipulate. More...

Addr	dataManipulated
	Counter to determine the amount of data manipulated. More...

Protected Attributes inherited from BaseGen
const std::string	_name
	Name to use for status and debug printing. More...

const MasterID	masterID
	The MasterID used for generating requests. More...

Additional Inherited Members
Public Attributes inherited from BaseGen
const Tick	duration
	Time to spend in this state. More...

Protected Member Functions inherited from BaseGen
PacketPtr	getPacket (Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags=0)
	Generate a new request and associated packet. More...

Detailed Description

DRAM specific generator is for issuing request with variable page hit length and bank utilization.

Currently assumes a single channel configuration.

Definition at line 315 of file generators.hh.

Constructor & Destructor Documentation

DramGen::DramGen	(	const std::string &	_name,
		MasterID	master_id,
		Tick	_duration,
		Addr	start_addr,
		Addr	end_addr,
		Addr	_blocksize,
		Tick	min_period,
		Tick	max_period,
		uint8_t	read_percent,
		Addr	data_limit,
		unsigned int	num_seq_pkts,
		unsigned int	page_size,
		unsigned int	nbr_of_banks_DRAM,
		unsigned int	nbr_of_banks_util,
		unsigned int	addr_mapping,
		unsigned int	nbr_of_ranks
	)

inline

Create a DRAM address sequence generator.

Parameters

_name	Name to use for status and debug
master_id	MasterID set on each request
_duration	duration of this state before transitioning
start_addr	Start address
end_addr	End address
_blocksize	Size used for transactions injected
min_period	Lower limit of random inter-transaction time
max_period	Upper limit of random inter-transaction time
read_percent	Percent of transactions that are reads
data_limit	Upper limit on how much data to read/write
num_seq_pkts	Number of packets per stride, each of _blocksize
page_size	Page size (bytes) used in the DRAM
nbr_of_banks_DRAM	Total number of banks in DRAM
nbr_of_banks_util	Number of banks to utilized, for N banks, we will use banks: 0->(N-1)
addr_mapping	Address mapping to be used, 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo assumes single channel system